VLSI

Clocked CMOS logic, often referred to as dynamic CMOS logic, is a design

technique used in digital circuits where the logic gates are synchronized with a
clock signal. This approach leverages the clock signal to control the timing of
operations, thereby achieving faster switching speeds and lower power
consumption compared to static CMOS logic. Here's a detailed explanation:

Key Concepts of Clocked CMOS Logic

1. Dynamic Behavior:

In clocked CMOS logic, the circuit relies on the charge stored in capacitors
to maintain the logic state temporarily. Unlike static CMOS logic, which
continuously draws power to maintain the state, dynamic logic uses a
clock signal to refresh the state periodically.

2. Precharge and Evaluate Phases:

Precharge Phase:

During this phase, the clock signal is low (0). The output node of the
dynamic gate is precharged to a high voltage level (usually \(V_{DD}\))
by a PMOS transistor.

Evaluate Phase:

When the clock signal goes high (1), the PMOS transistor turns off, and
the NMOS transistors evaluate the logic based on the input signals.
The output node discharges to ground (0) if the logic conditions are
met, otherwise, it remains high.

3. Structure:

A typical dynamic CMOS logic gate consists of:

A PMOS precharge transistor connected between the output node and

\(V_{DD}\).

An NMOS evaluation network that forms the logic function and

connects to the output node and ground.

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 An output node where the logic state is temporarily stored.

4. Advantages:

Speed:

Dynamic logic gates can switch faster than static gates because they
require fewer transistors and have lower parasitic capacitance.

Power Efficiency:

Power is consumed only during the evaluate phase, and less during
the precharge phase, leading to lower average power consumption
compared to static logic.

5. Disadvantages:

Clock Dependency:

The logic relies on a clock signal, making it sensitive to clock skew and
jitter.

Charge Leakage:

Over time, the charge on the capacitors can leak away, potentially
leading to incorrect logic states if not refreshed frequently enough.

Noise Sensitivity:

Dynamic logic is more susceptible to noise and charge sharing effects,

which can corrupt the stored logic state.

Applications
High-Speed Computing:

Used in high-performance processors and digital signal processors (DSPs)

where speed is critical.

Power-Sensitive Designs:

Employed in portable and battery-operated devices to minimize power

consumption.

Examples of Clocked CMOS Logic Families

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 Domino Logic:

A form of dynamic logic where each stage feeds into the next, precharging
and evaluating in a domino-like cascade.

NORA Logic:

Combines static and dynamic logic stages to mitigate some of the noise
and leakage issues inherent in purely dynamic designs.

Summary
Clocked CMOS logic leverages the timing of a clock signal to dynamically control
the logic states, enabling faster operation and lower power consumption
compared to static CMOS logic. However, it introduces challenges related to clock
synchronization, charge leakage, and noise susceptibility, requiring careful design
and timing considerations.

CMOS Domino Logic: Key Points

1. Overview:

CMOS domino logic is a modified form of clocked CMOS logic.

It uses a single clock to precharge and evaluate a series of cascaded

dynamic logic blocks.

2. Structure:

Each logic gate includes a static CMOS buffer.

During the precharge phase (\(\phi = 0\)), the output node of the dynamic
gate is precharged high, and the output of the buffer is low.

3. Operation Phases:

Precharge Phase (\(\phi = 0\)):

Output node precharges to a high voltage.

Buffer output is low.

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 Transistors in subsequent logic blocks are turned off.

Evaluate Phase (\(\phi = 1\)):

Output conditionally discharges based on the logic input.

Buffer output conditionally goes high.

This sequential evaluation causes each gate in the cascade to make at

most one transition (1 → 0), while the buffer only transitions from (0 →
1).

4. Sequential Evaluation:

Each stage evaluates in sequence like falling dominos.

Ensures only one transition per gate, facilitating a clear timing sequence.

5. Clock Utilization:

A single clock can manage the precharge and evaluate phases for all gates
within a block.

6. Limitations:

Non-inverting Structures:

Only non-inverting structures are possible.

Buffer Requirement:

Each gate must be buffered, which is necessary for preventing loading

issues.

Charge Redistribution:

Charge redistribution can be problematic, causing potential errors.

7. Minimizing Limitations:

Complex Logic Circuits:

In circuits like arithmetic logic units, XOR gates (needed for inversion)
can be implemented as complementary gates driven by the last
domino circuit.

8. Static Operation (with Weak P-Transistor):

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 Weak P-Transistor Inclusion:

Adding a weak p-transistor (low gain, small W/L ratio) allows for low-
frequency or static operation.

Balances leakage effects without significantly fighting pull-down

transistors.

Pull-Up Speed:

Pull-up time is much slower than pull-down speed.

Current Draw:

Current during evaluation should be low to avoid impacting static

power dissipation.

Suggested value: 10 µA.

9. Precharge Transistor:

Can be eliminated if the time between evaluations allows the weak pull-up
to charge the output node.

10. Claims and Performance:

Claims of improved noise margin and charge redistribution moderation by

adding a weak p-transistor are not valid for high-speed circuits due to the
slow response time of the weak p-device.

The addition may impact speed performance.

11. Latching Mechanism:

A weak p-feedback transistor can be added to make the gate latching,

ensuring the output state is held stable during subsequent operations.

Diagram References
Fig. 5.10a: Basic domino logic gate with a buffer.

Fig. 5.10b: Domino gate made static with a weak p-transistor.

Fig. 5.10c: Latching domino gate with a weak p-feedback transistor.

Summary

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 CMOS domino logic enhances clocked CMOS logic by enabling sequential
evaluation of cascaded dynamic logic blocks using a single clock. While it
introduces certain limitations and complexities, such as the need for buffering and
handling charge redistribution, it offers advantages in speed and efficient
clocking. Including weak p-transistors can allow for static operation and improved
noise margins but may impact high-speed performance.

Pseudo-nMOS Gate: Key Points

1. Basic Structure:

The pseudo-nMOS gate is an extension of the nMOS inverter.

It uses a single p-transistor as the load device, with its gate connected to \
(V_{ss}\) (ground).

2. Comparison to Conventional MOS:

In conventional MOS, the load is typically a depletion or enhancement

MOS transistor.

In pseudo-nMOS, this load is replaced by a p-device.

3. Transistor Ratio Design:

The design requires careful selection of the ratio of the p-transistor load to
the n-driver transistors.

This ratio (\( \beta_{load} / \beta_{driver} \)) must ensure sufficient gain for
consistent logic levels.

4. Ratioed Transistor Sizes:

Ensuring correct switching involves adjusting transistor sizes to achieve

the desired gain ratio.

The effective \( \beta_{load} / \beta_{driver} \) ratio must align with the

values predicted by the specific design equations (such as Eq. 2.37 in the
referenced material).

5. Static Power Dissipation:

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 A major issue with the pseudo-nMOS gate is static power dissipation.

Since the p load is always on, current flows through the gate whenever the
n pull-down is activated, resulting in continuous power consumption.

6. Transistor Count:

An n-input pseudo-nMOS gate consists of \( n + 1 \) transistors.

This includes the single p-transistor load and the n pull-down transistors
corresponding to each input.

7. Capacitive Load:

In a complementary gate, each input faces a capacitive load of at least two

unit gate loads due to the input capacitance of the unit-sized transistors.

In pseudo-nMOS gates, the minimum load can be one unit gate load, using
only one transistor per input function term.

8. Trade-offs in Driver Transistor Size:

If minimum-sized driver transistors are used, the pull-up gain (from the p
load) must be reduced to maintain adequate noise margins.

This reduction in pull-up gain slows the rise time of the gate.

9. Performance Comparison:

Despite the potential for reduced input capacitance, the pseudo-nMOS

gate does not offer significant advantages over conventional MOS gates
with depletion loads.

The key disadvantage is the static power dissipation due to the always-on
p load.

Summary
The pseudo-nMOS gate is a variation of the nMOS inverter that uses a single p-
transistor as the load device. This design requires careful selection of the
transistor size ratio to ensure proper gain and logic levels. However, the gate
suffers from static power dissipation when the pull-down network is active,
leading to continuous power consumption. While it can reduce input capacitance,
the pseudo-nMOS gate does not provide significant advantages over conventional

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 MOS depletion load gates, and its use is limited by the static power dissipation
issue.

Basic Dynamic CMOS Gate: Detailed Explanation

Structure and Operation

1. Basic Components:

n-Transistor Logic Structure: The core logic block that determines the
logic function.

p-Transistor (Precharge): Connects the output node to \(V_{DD}\) during

the precharge phase.

n-Transistor (Evaluate): Connects the output node to \(V_{SS}\) (ground)

during the evaluate phase.

2. Precharge Phase (\(\phi = 0\)):

During this phase, the p-transistor is active, charging the output node to \
(V_{DD}\).

The n-transistor (ground switch) is off, preventing any discharge path to

ground.

3. Evaluate Phase (\(\phi = 1\)):

The n-transistor becomes active, allowing the output node to discharge to

\(V_{SS}\) based on the logic function.

The p-transistor is off, isolating the output node from \(V_{DD}\).

Alternative Configuration
n-Transistor Precharge:

The output node is precharged to \(V_{SS}\) using an n-transistor.

A p-transistor discharges the output to \(V_{DD}\) based on the logic

function.

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 Timing and Capacitance
Input Capacitance:

The input capacitance is similar to a pseudo-nMOS gate.

Pull-Up Time:

Improved due to the active p-transistor switch charging the node.

Pull-Down Time:

Increased due to the n-transistor (ground switch) discharging the node.

Problems and Limitations

1. Input Timing Constraint:

Inputs must only change during the precharge phase. If inputs change
during the evaluate phase, charge redistribution can corrupt the output
voltage.

2. Charge Redistribution:

If the inputs are not stable during the evaluate phase, transient charges
can affect the output, leading to incorrect logic levels.

3. Cascading Issues:

Simple single-phase dynamic CMOS gates cannot be directly cascaded.

During the evaluate phase, the output of one gate (if used as an input to
another) may not stabilize quickly enough, causing timing issues in
subsequent stages.

Example Problem with Cascading

Scenario:

Consider two cascaded dynamic CMOS gates (as in Fig. 5.4):

1. Both gates are precharged, charging their output nodes to \(V_{DD}\).

2. During the evaluate phase, the first gate’s output conditionally

discharges based on its input.

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 3. The second gate's evaluation is delayed due to the finite discharge
time of the first gate’s output.

This delay means the second gate may not have accurate input states
immediately during its evaluate phase, leading to potential logic errors.

Summary
Dynamic CMOS Gate:

Combines n-transistor logic with precharge and evaluate phases

controlled by a single clock.

Ensures fast pull-up times but can have slower pull-down times due to the
ground switch.

Proper operation depends on input changes only during the precharge

phase to avoid charge redistribution issues.

Cascading such gates directly can lead to timing problems, as the output
of one gate might not be stable in time for the next gate's evaluation
phase.

This detailed explanation covers the structure, operation, advantages, and

challenges of basic dynamic CMOS gates, providing a clear understanding of their
behavior and limitations.

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