System Design using Verilog

Contents of the lecture

(1) Truth Table of 4 Bit Binary to Gray Code converter
(2) Structure Model of 4 Bit Binary to Gray Code converter
(3) Behavior Model of 4 Bit Binary to Gray Code converter
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(4) Dataflow Model of 4 Bit Binary to Gray Code converter

(5) Test Bench
 Truth Table of 4 Bit Binary to Gray Code converter

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
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0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0 60
 Verilog Code of a 4 Bit Binary to Gray Code converter

Behaviour Model G0= B0 xor B1

module binarytogray (b3,b2,b1,b0,g3,g2,g1,g0);
G1= B1 xor B2
input b3,b2,b1,b0 ;
G2= B2 xor B3
output g3,g2,g1,g0; G3= B3
reg g3,g2,g1,g0;
always @(b3,b2,b1,b0) Dataflow Model
begin module binarytogray (b3,b2,b1,b0,g3,g2,g1,g0);
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g0=b1 ^ b0; input b3,b2,b1,b0 ;

g1=b2 ^ b1; output g3,g2,g1,g0;
g2=b3 ^ b2; assign g0=b1 ^ b0;
G3=b3; assign g1=b2 ^ b1;
end assign g2=b3 ^ b2;
endmodule assign g3=b3;
endmodule

Structure Model
module binarytogray
(b3,b2,b1,b0,g3,g2,g1,g0);
input b3,b2,b1,b0 ;
output g3,g2,g1,g0;
xor x0(g0,b0,b1);
xor x1(g1,b1,b2);
xor x2(g2,b2,b3);
buf a1 (g3,b3);
endmodule 61
 Test Bench of 4 Bit Binary to Gray Code converter

Behaviour Model
module binarytogray (b3,b2,b1,b0,g3,g2,g1,g0);
input b3,b2,b1,b0 ;
output g3,g2,g1,g0;
reg g3,g2,g1,g0;
always @(b3,b2,b1,b0)
begin
g0=b1 ^ b0;
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g1=b2 ^ b1;
g2=b3 ^ b2;
g3=b3;
end
endmodule
Test Bench
module testbench;
reg b3; reg b2; reg b1; reg b0; wire g3; wire g2; wire g1; wire g0;
binarytogray uut (b3,b2,b1,b0,g3,g2,g1,g0);
initial
begin
$monitor($time,“b3=%b,b2=%b,b1=%b,b0=%b,g3=%b, g2=%b, g1=%b,
g0=%b", b3,b2,b1,b0,g3,g2,g1,g0);
#5 b3=0;b2=0;b1=0;b0=1
#5 b3=0;b2=1;b1=0;b0=1
#5 b3=1;b2=0;b1=0;b0=1
#5 b3=0;b2=0;b1=1;b0=1
#5 $finish;
end
endmodule 62
 System Design using Verilog

Contents of the lecture

(1) Truth Table of 4 Bit Gray to Binary Code converter
(2) Structure Model of 4 Bit Gray to Binary Code converter
(3) Behavior Model of 4 Bit Gray to Binary Code converter
GMR Institute of Technology

(4) Dataflow Model of 4 Bit Gray to Binary Code converter

(5) Test Bench
 Truth Table of 4 Bit Gray to Binary Code converter

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
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0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 0
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0 64
 Verilog Code 4 Bit of 4 Bit Gray to Binary Code converter

Behaviour Model b[0]= b[1] xor g[0]

module gray_to_binary(g,b);
b[1]= b[2] xor g[1]
input [3:0]g;
b[2]= g[3] xor g[2]
output [3:0]b; b[3]= g[3]
reg [3:0]b;
always@(g) Dataflow Model
begin module gray_to_binary(g,b);
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b[3]=g[3]; input [3:0]g;

b[2]=g[3]^g[2]; inout [3:0]b;
b[1]=b[2]^g[1]; assign b[3]=g[3];
b[0]=b[1]^g[0]; assign b[2]=g[3]^g[2];
end assign b[1]=b[2]^g[1];
endmodule assign b[0]=b[1]^g[0];
endmodule

Structure Model
module gray_to_binary(g,b);
input [3:0]g;
inout [3:0]b;
buf b1 (b[3],g[3]);
xor x1 (b[2],g[3],g[2]);
xor x2 (b[1],b[2],g[1]);
xor x3 (b[0],b[1],g[0]);
endmodule
65
 Test Bench 4 Bit of 4 Bit Gray to Binary Code converter

Structure Model
module gray_to_binary(g,b);
input [3:0]g;
inout [3:0]b;
buf b1 (b[3],g[3]);
xor x1 (b[2],g[3],g[2]);
xor x2 (b[1],b[2],g[1]);
xor x3 (b[0],b[1],g[0]);
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endmodule

Test Bench
module testbench;
reg [3:0]g; wire [3:0]b;
gray_to_binary uut (.g(g),.b(b));
initial
begin
$monitor($time,"g=%b,b=%b", g,b);
#5 g=4'b0000;
#5 g=4'b0001;
#5 g=4'b0010;
#5 g=4'b0011;
#5 g=4'b0100;
#5 g=4'b1011;
#5 $finish;
end 66