Topics

1. Introductory Concepts
2. Numbering Systems
3. Boolean Algebra
4. Combinational Logic
5. Flip-Flops – Part 2
6. Arithmetic Circuit
7. Counters & Shift Registers
8. Logic Families

Chp 5 Flip Flops 1

 Flip-Flops (F/F)
1. Introduction
2. Nand / Nor Latch
3. SC F/F
4. JK F/F
5. D F/F , D Latch
6. Asynchronous Control (Clear/Preset)
7. Timing Parameters
8. One-shot Devices
9. Schmmit Trigger Invertors

Chp 5 Flip Flops 2

5.7
Introducing Data FF (D FF)

D CLK Q
D Q
0 0
CLK Q 1 1

D CLK Q
D Q
0 0
CLK Q 1 1

Q follows D at NGT
or PGT

Chp 5 Flip Flops 3

5.7 Given D & CLK waveforms, D Q

obtain the Q waveform

CLK Q

CLK

Q ‘1’
First, draw upward
arrows on PGT, and lines
through them

Chp 5 Flip Flops 4

5.7 Given D & CLK waveforms, D Q

obtain the Q waveform

CLK Q

CLK

Q ‘1’

Chp 5 Flip Flops 5

5.7 Given D & CLK waveforms, D Q

obtain the Q waveform

CLK Q

CLK

Q ‘1’

D=0, D=1, D=0, D=1, work out

Q=0 Q=1 Q=0 Q=1 the rest
yourself

Chp 5 Flip Flops 6

5.7 Given D & CLK waveforms, D Q

obtain the Q waveform

CLK Q

CLK

Q ‘1’

D=0, D=1, D=0, D=1, D=1, D=0, D=1,

Q=0 Q=1 Q=0 Q=1 Q=1 Q=0 Q=1

Chp 5 Flip Flops 7

5.7
Implementing D FF using JK FF

D J Q Q
CLK CLK

K Q Q

J
D K CLK Q
0 0 No change Just requiring K to be
Opposite of D, so that it
1 0 1 will help to do J=1, K=0
OR J=0, K=1
0 1 0
1 1 Q0 THUS SETTING SET OR
CLEAR USING ONLY D

Chp 5 Flip Flops 8

5.8 Given D & EN waveforms,
D Q Q
obtain the Q waveform
EN Q /Q

EN

Q ‘0’
First, draw lines through
transitions of EN When EN is 1, it will follow D.
waveform When EN is 0, it will remain the
same state as before !!

Chp 5 Flip Flops 11

5.8 Given D & EN waveforms,
D Q Q
obtain the Q waveform
EN Q /Q

EN

Q ‘0’

Chp 5 Flip Flops 12

5.8 Given D & EN waveforms,
D Q Q
obtain the Q waveform
EN Q /Q

EN

Q ‘0’

Disabled, Enabled, Disabled, Enabled, Disabled,

no Q follows no Q follows no
change D change D change

Chp 5 Flip Flops 13

5.8 Given D & EN waveforms,
D Q Q
obtain the Q waveform
EN Q /Q

EN

Q ‘0’

Latched at Transparent at Latched at Transparent at Latched at

Q=0 Q=D Q=1 Q=D Q=1

Chp 5 Flip Flops 14

5.8
D latch vs D FF, obtain the Q waveforms for comparison

CLK
or EN

D
D Q Qck

Qck
CLK Q

D Q Qen Qen

EN Q

Chp 5 Flip Flops 15

5.8
D latch vs D FF, obtain the Q waveforms for comparison

CLK
or EN

D
D Q Qck

Qck
CLK Q

D Q Qen Qen

EN Q

Chp 5 Flip Flops 16

5.4
Synchronous Control Inputs

S and C inputs in the clocked SC Flip Flops

J and K inputs in the JK Flip Flops
D input in the D Flip Flops
All the above must work together with the
clock input to effect a change in the Q outputs
Therefore, these inputs (S, C, J, K, D) are
called the Synchronous Control Inputs

Chp 5 Flip Flops 17

5.4
Synchronous vs Asynchronous system

SYNCHRONOUS
Output can change
state only when the
clock makes an active
transition
ASYNCHRONOUS
Outputs can change
state any time when
one or more inputs
change

Chp 5 Flip Flops 18

5.9 Introducing Asynchronous Control inputs
(Preset and Clear)
NO TRIANGLE
HERE
There is no triangle at the
J Preset Q
Preset and Clear inputs. This
CLK
means that they are LEVEL-
K
Clear
Q triggered. i.e. not edge-
NO TRIANGLE triggered
HERE

Chp 5 Flip Flops 19

5.9 Introducing Asynchronous Control inputs
(Preset and Clear)

There are bubbles at the

J Preset Q
Preset and Clear inputs. This
CLK
means that these are active-
K
Clear
Q LOW inputs.

Chp 5 Flip Flops 20

5.9 Introducing Asynchronous Control inputs
(Preset and Clear)

When Preset and Clear are

J Preset Q
not active,
CLK

K Q
the FF operates under the
Clear
control of J, K and clock.
This is known as clocked
operation

Chp 5 Flip Flops 21

5.9 Clocked JK FF with Preset & Clear
Preset Clear J K CLK Qn+1 Remarks
1 1 0 0 Qn No change
1 1 0 1 0 Clear
JPresetQ
1 1 1 0 1 Set
CLK
1 1 1 1 Qn Toggle
K Q
Clear

When Preset & Clear are inactive –FF is in Clocked Operation

Chp 5 Flip Flops 22

 FOR ACTIVE LOW, WHEN BOTH PRESET &
CLEAR=1, IT WILL BE A CLOCKED OPERATION
5.9 Clocked JK FF with Preset & Clear
Preset Clear J K CLK Qn+1 Remarks
1 1 0 0 Qn No change
J Preset Q 1 1 0 1 0 Clear
CLK 1 1 1 0 1 Set
K Q 1 1 1 1 Qn Toggle
Clear
0 0 X X X 1 Invalid
0 1 X X X 1 Set
INVALID WILL ALWAYS
GIVE THE OPPOSITE OFF 1 0 X X X 0 Clear
THE ACTIVE (ACTIVE LOW
: OUTPUT = 1 INVALID)

When Preset & Clear are inactive –FF is in Clocked Operation

When Preset or Clear is active – they override Clocked Operation

Chp 5 Flip Flops 23

5.9
Given the input waveforms, obtain the Q waveform

CLK
+5V

Preset
J Preset Q

CLK Clear

K Q
Clear
Q ‘1’ First, draw downward
arrows on NGT, and lines
through them. Also lines
through transitions of Preset
& Clear

Chp 5 Flip Flops 24

5.9
Given the input waveforms, obtain the Q waveform

CLK
+5V

Preset
J Preset Q

CLK Clear

K Q
Clear
Q ‘1’

Chp 5 Flip Flops 25

5.9
Given the input waveforms, obtain the Q waveform

+5V
CLK

Preset
J Q
Preset
CLK
Clear
K Q
Clear

Q ‘1’

Preset & Clear

inactive, no NGT, Preset & Clear
no change inactive, NGT,
J=K=1, toggle

Chp 5 Flip Flops 26

5.9
Given the input waveforms, obtain the Q waveform

+5V
CLK

Preset
J Q
Preset
CLK
Clear
K Q
Clear

Q ‘1’

Preset is active, Preset & Clear

override clock inactive, no
operation, Q=1 NGT, no change

Chp 5 Flip Flops 27

5.9
Given the input waveforms, obtain the Q waveform

+5V
CLK

Preset
J Q
Preset
CLK
Clear
K Q
Clear

Q ‘1’

Preset & Clear

inactive, NGT, Preset & Clear
J=K=1, toggle Clear is active,
inactive, NGT, override CLK
J=K=1, toggle operation. Q=0

Chp 5 Flip Flops 28

5.9
Given the input waveforms, obtain the Q waveform

+5V
CLK

Preset
J Q
Preset
CLK
Clear
K Q
Clear

Q ‘1’

Preset & Clear Preset & Clear

inactive, no inactive, NGT,
NGT, no J=K=1, toggle
change

Chp 5 Flip Flops 29

5.4
Why – Timing Parameters
Theoretically, transitions occur in 0 second:

In reality, transitions take time:

Also, circuit takes time to respond

This results in a series of timing considerations

Chp 5 Flip Flops 30

5.4
Timing Parameters

Setup Time, tS & Hold Time, tH

Propagation Delay, tPLH, & tPHL

Maximum Clock Frequency, fMAX

Minimum Clock Pulse Width, tW(L) & tW(H)

Maximum rise time tR & fall time tF of the CLK

Asynchronous Active Pulse Width, tW(Clear) & tW(Preset)

Chp 5 Flip Flops 31

5.4 FOR CONTROL INPUT !!!

Setup tS & Hold Time tH

Synchoronous
50%
Control input

Clock input
50%

tS tH Hold time = Time required from 100% to

50%
Setup Time = Time
required from 50% to
100%

Chp 5 Flip Flops 32

5.11 Propagation Delay, tPLH & tPHL

CLK CLK
50% 50%

50% 50%

Q
Q

tPLH tPHL

Delay going from Delay going from

LOW to HIGH HIGH to LOW

**Delay time between CLK
REACHES 50% and Q
REACHES 50% !!!**

Chp 5 Flip Flops 33

5.11
Maximum Clock Frequency, fMAX

Highest frequency that may be applied to the clock input

of a FF and still have it triggered reliably

T = Period

fMAX = 1 / T MIN

Chp 5 Flip Flops 34

5.11
Clock Pulse Width, tW(L) & tW(H)

Minimum pulse width of CLK signal for reliable triggering

CLK
tW(H) tW(L)

Chp 5 Flip Flops 35

 From 10% to 90% !!!
5.11
Clock Rise Time tR & Fall Time tF
Maximum rise time tR and fall time tF of the CLK
signal transitions required for reliable triggering

CLK CLK 90%

90%
10%
10%

tR
tF

Chp 5 Flip Flops 36

5.11
Asynchronous Active Pulse Width

Minimum time PRESET or CLEAR input must be

active to reliably set or clear the FF

tW(Clear) /
tW(Preset)

Chp 5 Flip Flops 37

5.11 Typical FF Timing Values (ns)

TTL CMOS
7474 74LS112 74C74 74HC112
tS 20 20 60 25
tH 5 0 0 0
tPHL – from CLK to Q 40 24 200 31
tPLH– from CLK to Q 25 16 200 31
tPHL – from /CLR to Q 40 24 225 41
tPLH– from /PRE to Q 25 16 225 41
tW(L) – CLK LOW time 37 15 100 25
tW(H) – CLK HIGH time 30 20 100 25
tW(L) – at /PRE or /CLR 30 15 60 25
fmax – in MHz 15 30 5 20

Chp 5 Flip Flops 38

5.11 Answer the following questions using the Table in
the previous slide.
1. Assume that Q = 0. How long can it take for Q to go HIGH
when a PGT occurs at the CLK input of a 7474?
2. Assume that Q = 1. How long can it take for Q to go LOW in
response to the /CLR input of a 74HC112?
3. What is the narrowest pulse that should be applied to the
/CLR input of the 74LS112 FF to clear Q reliably?
4. Which FF in the table requires that the control inputs
remain stable after the occurrence of the active clock
transition?
5. For which FFs must the control inputs be held stable for a
minimum time prior to the active clock transition?
ALL FF

Chp 5 Flip Flops 39

5.11 Answer the following questions using the Table in
the previous slide.
1. Assume that Q = 0. How long can it take for Q to go HIGH
when a PGT occurs at the CLK input of a 7474? 25ns
2. Assume that Q = 1. How long can it take for Q to go LOW in
response to the /CLR input of a 74HC112? 41ns
3. What is the narrowest pulse that should be applied to the
/CLR input of the 74LS112 FF to clear Q reliably? 15ns
4. Which FF in the table requires that the control inputs
remain stable after the occurrence of the active clock
transition? 7474
5. For which FFs must the control inputs be held stable for a
minimum time prior to the active clock transition? all

Chp 5 Flip Flops 40

5.14
Flip-Flop Applications

1. Switch debouncing (already covered)

2. Detecting an input sequence
3. Data storage & transfer
4. Frequency division / Counting
5. … others
a circuit in which the
outputs follow a
Most of these applications predetermined
fall into the category of sequence of states

sequential circuits

Chp 5 Flip Flops 41

5.16
Detecting an input sequence (i)

A
X
B

The above circuit cannot detect the input sequence:

As X become 1 regardless of which input goes HIGH first

How to have X=1 only if A goes HIGH first,
and then B goes HIGH some time later ?
See next slide for a possible solution.

Chp 5 Flip Flops 42

5.16
Detecting an input sequence (ii)
A A
A J X
B CLK B B
K X
X

A is fed to J, A become ‘1’ A become ‘1’

B is fed to before B, after B,
CLK. K=0 therefore, X therefore, X
always. X can becomes ‘1’ on remains ‘0’ on
only change PGT of B. PGT of B.
on PGT of B.

Therefore X=1 only if A goes HIGH first

Chp 5 Flip Flops 43

5.17
Parallel Data Transfer / Storage

D Q Q1=X

CLK
Q
X
Y
Combinational D Q Q2=Y
Z
Logic Circuit
CLK
Q

Outputs may
change at Q3=Z
different time D Q

CLK
Q
On NGT, X, Y, Z is
transferred to Q

Chp 5 Flip Flops 44

5.19 Frequency Division and counting

1 J A 1 J B 1 J C
CLK CLK CLK
1 K /A 1 K /B 1 K /C

The Clock Pulse A few FF are All J & K = 1

is applied to the cascaded, with
CLK of the first the CLK
FF. connected to the
previous Q.

**FEEDING Q to CLK !!** While keeping J and K at 1

Chp 5 Flip Flops 45

5.19 Frequency Division and counting

1 J A 1 J B 1 J C
CLK CLK CLK
1 K /A 1 K /B 1 K /C

With J=K=1, A B’s CLOCK

comes from A, i.e. C’s CLOCK comes
will toggle at from B, i.e. C will
every NGT of B will toggle at
every NGT of A toggle at every
the CLOCK NGT of B

Chp 5 Flip Flops 46

5.19 Frequency Division and counting

1 J A 1 J B 1 J C
CLK CLK CLK
1 K /A 1 K /B 1 K /C

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CLK

Chp 5 Flip Flops 47

5.19 Frequency Division and counting

1 J A 1 J B 1 J C
CLK CLK CLK
1 K /A 1 K /B 1 K /C

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CLK

Chp 5 Flip Flops 48

5.19 Frequency Division and counting

1 J A 1 J B 1 J C
CLK CLK CLK
1 K /A 1 K /B 1 K /C

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CLK

Chp 5 Flip Flops 49

5.19 Frequency Division and counting

1 J A 1 J B 1 J C
CLK CLK CLK
1 K /A 1 K /B 1 K /C

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CLK

Chp 5 Flip Flops 50

 **REGARDLESS OF ORIGINAL DUTY CYCLE, THIS WILL
CAUSE THE NEW DUTY CYCLE TO BECOME 50% !!!!
5.19 How is Frequency Division Achieved?
If the Clock Frequency (fCLK) is given as 16KHz
16 KHz
CLK
T
A
fCLK / 2 = T T of A is double T of CLK => freq of A is ½ freq of CLK
8 KHz
B
fA/2 = fCLK / 4 Likewise …
= 4 KHz
C
fB/2 = fCLK / 8
= 2 KHz For N FFs the frequency of the last FF
is 1/2N of the CLK frequency
Thus PERIOD T WILL BE x 2 !!!

Chp 5 Flip Flops 51

5.19 How is Counting achieved?
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

CLK

LSB
A 0 1 0 1

0 0 1 1
B

MSB 0 0 0 0
C

000 010 100 110 000* 010 100 110 000*

001 011 101 111 001 011 101 111
Useful to have number counting from 0 to 7
for this case !! cycle repeats

Chp 5 Flip Flops 52

5.19 State Transition Diagram
CBA
000
111
001
Shows the
110 counting
sequence 010

101
011
100

Chp 5 Flip Flops 53

5.19
MOD number (i)
The MOD number of the counter is 8 (23) in the
previous example.

MOD number is the number of states the counter goes

through in each complete cycle before it RECYLES
back to its starting state

Chp 5 Flip Flops 54

5.19
MOD Number (ii)

1 J A 1 J B 1 J C 1 J D
CLK CLK CLK CLK

1 K /A 1 K /B 1 K /C 1 K /D

MOD number = 2N N= number of FF

e.g.
N= 3 , MOD number = 23 = 8
N= 4 , MOD number = 24 = 16
…

Chp 5 Flip Flops 55

5.20
Flip-Flop Related Devices
Multivibrators

Multivibrator is a circuit that generates nearly

rectangular waveforms with controlled time durations
and repetition rates

Chp 5 Flip Flops 56

5.20
Flip-Flop Related Devices
Multivibrators
I am a Bistable
I am a Monostable multivibrator (Flip Flop), I
multivibrator, have 2 stable states.
(One-Shot) I have
1 stable state. J Q
CLK

K /Q I am a Astable
Q
T
multivibrator
Q (Oscillator), I
have No stable
RT CT state.

Chp 5 Flip Flops 57

5.20
Monostable Multivibrator (One-Shot)

There are 2 types of One-Shot devices:

Nonretriggerable One-Shot
Retriggerable One-Shot

Chp 5 Flip Flops 58

5.20 Monostable Multivibrator (One-Shot)
Nonretriggerable One-Shot
Q Normally low
Trigger
Input T
Q Normally high

RT CT

It has a STABLE output state, normally Q=0

When T input is triggered, it switches to QUASI-STABLE
state (Q=1) for a fixed period, tp, (tP = 0.7RTCT) and returns
to STABLE state until triggered again
**THIS WILL BE THE
tp (FIXED PERIOD ) is not the same PERIOD FORMULA UNLESS STATED
MENTIONED in the normal wave form !! OTHERWISE**
Thus INCREASING THE DUTY CYCLE !!!

Chp 5 Flip Flops 59

5.20
Given the T waveform, obtain the Q & /Q waveform
for Nonretriggerable One-Shot
a b c d e f

T
d and f WOULD NOT
RE-EXTEND THE tp !!!

Q It will be voided !!!!

tP tP tP tP Thus the name NON-

RETRIGGERABLE !!
/Q
**tp = Pulse Width

Triggers at d & f have No effect on Q since it’s already high

Chp 5 Flip Flops 60

5.20 Monostable Multivibrator (One-Shot)
Retriggerable One-Shot

Similar to Nonretriggerable One-shot

BUT
Can be retriggered while it is in the quasi-stable state.

It begins a new tp interval each time a trigger pulse

is applied, regardless of its current state of Q.

Chp 5 Flip Flops 61

5.20
Given the T waveform, obtain the Q waveform for
Retriggerable One-Shot

Q tp
tp tp
Notice that even
though Q is already
‘1’, it can still
response to further
trigger

Chp 5 Flip Flops 62

5.20 Applications of monostable circuits (i)

Q tp tp tp

Widening narrow pulse (BOTH)

Q
tp tp tp
Narrowing wide pulse (BOTH)

Chp 5 Flip Flops 63

5.20
Applications of monostable circuits (ii)

Blocking unwanted pulse

(Using retriggerable One-Shot)

Chp 5 Flip Flops 64

5.24
Astable Multivibrator -
Schmitt-Trigger Inverter
Given
Standard
If input is inverter 7404
slow
changing
Oscillations may
5V occur at output if
i/p input stays in the
0V forbidden region
(neither ‘0’ nor
5V
o/p ‘1’) for too long
0V

Chp 5 Flip Flops 65

5.24 Standard Inverter vs
Schmitt-Trigger Inverter
VT+ is
Vo Vo called the
VT- is
called the positive
negative going
Hi Hi
going threshold
threshold (Higher
(Lower Trigger)
Trigger)

Lo Lo

0.8 2 Vi VT- VT+ Vi

Standard Inverter Schmitt-Trigger Inverter

Chp 5 Flip Flops 66

5.24 Standard Inverter vs
Schmitt-Trigger Inverter
Increasing
Vo Vo input must
Decreasing
input must go higher
go lower than VT+
Hi Hi
than VT- for the
for the output to
output to switch to
switch to Lo
Hi
Lo Lo

0.8 2 Vi VT- VT+ Vi

Standard Inverter Schmitt-Trigger Inverter

Chp 5 Flip Flops 67

5.24 How Schmitt-Trigger Inverter get
round the unwanted oscillation problem

Output has
5V
VT+ clean
i/p
transition,
0V independen
VT-
t of rate of
5V input
o/p
0V transition.

Chp 5 Flip Flops 68

5.24 Schmitt-Trigger Inverter Application
Schmitt-Trigger Oscillator
**WILL PRODUCE 50% DUTY CYCLE REGARDLESS !!**

e.g. for 74LS14, if given

5V
RT=1K, CT=470nF, then
f = 0.8/RTCT = 1.7KHz
Vo
CT
IC Freq(f) Rmax
>=100pF
7414 0.8/RC 500 ohms
74LS14 0.8/RC 2 Kohm
74HC14 1.2/RC 10Mohm

Chp 5 Flip Flops 69

5.24 Schmitt-Trigger Inverter Application
Schmitt-Trigger Oscillator

Brief explanation: Assume

5V
Vo was Hi initially. CT will
charge towards Vo, when
VCT goes above VT+, Vo
VCT Vo
switch to Lo. This causes
CT
CT to discharge, when VCT
goes below VT-, Vo switch
to Hi. This causing CT to
charge up again. The cycle
repeats, results in
rectangular pulses at Vo.

Chp 5 Flip Flops 70

5.24
Summary on Multivibrators
**OSCILLATOR NOT INVERTER !!**

Schmitt-Trigger oscillator generates rectangular

pulses
Flip Flops can change the frequency of rectangular
pulses. (Frequency divider)
One-shot can change the pulse width of rectangular
pulses

Remember? - Multivibrator isa circuit that generates

nearly rectangular waveforms with controlled time
durations and repetition rates

Chp 5 Flip Flops 71

Chp 5 Flip Flops 72