UART

Data rate about 230 Kbps to 460 Kbps

Num of Lines Transmitter Tx, Receiver Rx

Type Asynchronous
Commn full-duplex
Distance about 50 feet
devices use independent clocks.
Clock necessary for the baud rates
Hardware
complexity lesser
8 bits of data, one start bit and one
Protocol stop bit
error checking mechanisms: parity
Error bit
Software
addressing no need for addressing

Master-slave arch cannot support a multi-master

 USART I2C
Defined by the clock pulse stream
on the XCK pin 100 kbps, 400 kbps, and 3.4 Mbps

4 (Tx, Rx, XCK (clock), and XDIR

(direction)) 2-wire (data and clock)
Synchronous
Half duplex
Higher
common clock signal between
multiple masters and multiple slaves.

more
start and stops bits. an ACK bit for
every 8 bits of data
error checking mechanisms:
ACK/NACK bit
Each master , slave devices have soft
addresses

master/slave, supports a multi-master

good choice for short-distanced, low-
speed
D-sub connector (DB9) - COM port
in PCs peripheral devices like sensors
 SPI

about 10 Mbps to 20 Mbps

four signals: clock (SCLK), master
output/slave input (MOSI), master
input/slave output (MISO), slave
select (SS), each slave needs its own
slave select line
Synchronous
full-duplex
highest
one common serial clock between
master and slave.

less

specific protocols per manufacturer

slave connected with the master is

addressed by a slave select line.
master/slave, cannot support a multi-
master

memory devices