Microelectronics Journal 53 (2016) 134–155

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

A comparative study of various current mirror configurations:

Topologies and characteristics
Bhawna Aggarwal a,n, Maneesha Gupta a, A.K. Gupta b
a
Netaji Subhash Institute of Technology, Delhi University, Sector-3, Dwarka, New Delhi 110078, India
b
National Institute of Technology, Kurukshetra, Haryana, India

art ic l e i nf o a b s t r a c t

Article history: Current mirror is a fundamental unit, widely used for current amplification, biasing and active load in
Received 16 July 2015 various analog/mixed mode integrated circuits. Its efficient design plays a major role in deciding the
Received in revised form overall performance of these circuits. In literature, various techniques have been developed and proposed
25 March 2016
to improve the performance parameters of a current mirror like accuracy, input resistance, output re-
Accepted 17 April 2016
sistance and bandwidth etc. This paper is an effort to bring all these techniques on a single platform and
compare their advantages and disadvantages. Here, a detailed survey of various current mirror topologies
Keywords: has been carried out and these topologies have been categorized on the basis of various characteristic
Current mirror parameters. The discussed circuits have been simulated using Mentor Graphics Eldo spice in TSMC
Accuracy
0.18 mm CMOS, BSIM3 and Level 53 technology. In order to get a fair comparison among these techniques,
Input resistance
simulations under similar conditions using a supply voltage of 1.8 V have been performed.
Output resistance
Bandwidth & 2016 Elsevier Ltd. All rights reserved.
Low voltage circuits

1. Introduction [9,10]. Low voltage applications like bluetooth filters, universal

A current mirror (CM) is a unity gain current amplifier which
provides output current proportional to input current at its high
impedance output node. It also maintains output current constant
regardless of loading. Under ideal conditions, gain of a CM must
remain independent of frequency and output current should be
independent of voltage at the output node [1].
A CM can be used as a dc current source, current amplifier,
active load and for biasing in most of analog and mixed signal
circuits, such as operational amplifiers, operational transconduc-
tance amplifiers, second generation current conveyors, operational
mirrored amplifiers, current feedback operational amplifiers,
analog filters, analog-to-digital and digital-to-analog converters
etc. [1–10]. Thus, CM being a fundamental unit, its efficient design
affects the overall performance of these integrated circuits [2].
Important factors influencing performance of a CM are:
(i) Accuracy, defined as precision of copying input current at the
output node. (ii) Input/output compliance voltage, given as mini-
mum voltage required at input/output node of a CM for its proper
operation. (iii) Input resistance. (iv) Output resistance.
(v) Bandwidth [2,3,11–15]. CMs with very high accuracy are re-
quired in several applications of critical importance like biome-
dical circuits, bio-amplifiers and implantable microstimulators etc.
biquad filters, amplifiers, operational amplifiers and biomedical
circuits etc. require CMs operating at low compliance voltages [6–
8,16–18]. CMs with low input and high output resistances are re-
quired to minimize the loading effect. Such CMs are required as
tail current sources to improve the common-mode rejection ratio,
power supply rejection ratio and dc gain factor of differential pairs
[1,19]. High bandwidth in a CM is desirable feature for increasing
speed of the devices like current-steering digital-to-analog con-
verters, high-speed current mode amplifiers and current con-
veyors etc. [2,5,15]. Moreover, due to increased demand of smaller
portable devices, a lot of effort is being directed towards designing
circuits (including CMs) operating at lower supply voltage [20–23].
In this paper, a survey of different CM configuration has been
carried out. This survey as per author's knowledge broadly covers
the CMs based on their performance characteristics, though it may
not be exhaustive. The intention is to largely classify and cate-
gorize fundamental CM topologies available in literature that im-
prove the characteristic parameters (mentioned above) of a basic
CM.
The paper is organized as follows: In Section 2, basic CMs de-
signed to improve the performance characteristics of a simple CM
have been discussed. It also explains their operational principle
along with main advantages and disadvantages. Section 3 consists

n
Corresponding author.

http://dx.doi.org/10.1016/j.mejo.2016.04.015
0026-2692/& 2016 Elsevier Ltd. All rights reserved.
 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155 135

iIN iOUT
iIN iOUT
M3
vOUT 5
0.25

5 5
M1 M2
0.25 0.25
5 5
0.25 M1 M2
0.25

(a) (b)

iOUT
iIN
iIN
iOUT +
5 5
0.25 0.25
5
M4 M3 0.25 M4 M3
+
5
- VDS,sat.+VT
0.25
vOUT

5 5
M1 M2 5
0.25 0.25 M1 M2
0.25
+
5
- VDS,sat.+VT 0.25
-

(c)
(d)
Fig. 1. Basic Current Mirrors (a–d). (a) Simple CM, (b) Wilson CM, (c) Improved Wilson CM, and (d) cascode CM.

of techniques that reduce the required compliance voltage,
thereby reducing voltage headroom of the circuit. Structures
suggested in literature to reduce input resistance for a CM are
summarized in Section 4. In Section 5, CM topologies that provide
high output resistance are explained. Techniques used to improve
bandwidth of CMs are summarized in Section 6. Low voltage CM
techniques available in literature along with their description are
discussed in Section 7. Some of the very high performance CMs
available in literature are described in Section 8. An effort has been
carried out to simulate these circuits on similar platform to get a
fair comparison amongst them. These simulated results are in-
cluded in every section and finally Section 9 concludes the paper.
2. Basic current mirrors
MOSFET based simple CM is shown in Fig. 1(a). In this circuit, if
MOSFETs M1 and M2 operate in saturation region, output current (
iOUT) is proportional to input current (iIN) by the ratio of their as-
pect ratios. In case of identical MOSFETs, iIN ¼iOUT and the circuit
simply replicates or mirrors the input current at its output term-
inal and hence the name current mirror [1]. If the aspect ratio of
M2 is greater than that of M1, the circuit behaves as current am-
plifier, whose gain is directly proportional to the ratio of their
aspect ratios. However, gain of such circuits is fixed and has to be
decided at the time of fabrication. Various programmable CMs
[4,24–30] were proposed in literature that offer electronic tun-
ability of the gain in current amplifiers.
In simple CM (Fig. 1(a)), due to channel length modulation ef-
fect, the replication of input current at output node is not perfect.
Its current mirroring accuracy depends on the drain–source vol-
tages of MOSFETs and channel length modulation parameter (λ).
The input resistance (rin), output resistance (rout) and bandwidth
(ω0) of a simple CM are given as [1,3]:
1
rin = 1/gm1, rout = r02 = , ω 0 ≈ g m1/( Cgs1 + Cgs2 ),
λiD2 (1)
where gm is transconductance, r0 is incremental output resistance,
iD is drain current and Cgs is gate–source capacitance of respective
MOSFET. Eq. (1) shows that performance parameters of a simple
CM are limited by gm, r0 and Cgs of a MOSFET.
In case of short channel MOS devices used to design smaller,
high frequency and low power consumption equipments, the error
in output current due to channel length modulation effect in-
creases further [1,18]. It has been noticed that a reduction in size
of MOSFET leads to an increase in its transconductance along with
decrease in its output resistance [1]. In short channel MOSFETs, the
effect of reduction in output resistance is more prominent than
increase in transconductance. Hence, simple CMs designed with
these MOSFETs suffer from lower accuracy and lower output re-
sistance, thereby adversely affecting overall circuit performance.
Moreover, these CM circuits suffer from poor matching and
136 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155

operate on low supply voltage. Thus, the trend towards short

channel devices necessitates the requirement of designing CMs
with improved performance characteristics.
Various topologies have been developed in literature to im-
prove the performance characteristics of a simple CM. Wilson CM
(Fig. 1(b)) was proposed by Wilson [31]. In this CM, MOSFET M3
provides negative current feedback that not only improves the
current mirroring accuracy but also increases output resistance of
CM by a factor of gmr0. However, due to mismatch in vDS of basic
CM pair, perfect current mirroring accuracy is not achieved in
Wilson CM. Super Wilson CM was suggested by Wilson as a four
Fig. 3. PER in current mirroring accuracy for basic CMs discussed in Section 2.
MOSFET variant of Wilson CM [32] and was used by Schlotzhauer
and Viswanathian; Hart and Barker under the label improved
Wilson CM (Fig. 1(c)) [33,34]. In this circuit, diode connected
MOSFET (M4), added in input branch tries to equalize vDS of
MOSFETs forming primary CM pair and hence provides much
higher current mirroring accuracy than Wilson CM. This im-
provement is achieved in improved Wilson CM while maintaining
compliance voltages, input resistance and output resistance simi-
lar to Wilson CM. The output resistance of Wilson and improved
Wilson CMs is given as:
gm1r01gm3 r03
rout ≈
g m2 (2)

It has been observed that in order to achieve improvement in Fig. 4. Input current vs. input voltage characteristics for basic CMs discussed in
performance parameters of a CM, designer has to use more Section 2.
number of MOSFETs, which leads to an increase in effective
parasitic capacitance of the circuit. Bandwidth of a CM majorly
depends upon its input time constant and thereby input capaci-
tance [35]. Generally, increase in parasitic capacitances leads to an
increase in the effective input capacitance and hence lowers the
bandwidth for the circuit. However, in both Wilson and improved
Wilson CMs, presence of a real zero before dominant pole causes
increase in their bandwidths. This also leads to peaking in their
frequency response [36,37].
Cascode CM shown in Fig. 1(d) also enhances output resistance
and accuracy of a simple CM [1,3]. Its output resistance is given as:

rout = r03 + r02 ( 1 + r03 ( gm3 + gmb3 ) ) ≈ gm3 r03 r02 (3)

In cascode CM, if (W/L)2/(W/L)1 ¼ (W/L)3/(W/L)4, vDS2 follows
vDS1 as long as M2 and M3 remain in saturation (here W/L is aspect
ratio of the corresponding MOSFET). Moreover, M3 tries to main-
tain M2 in saturation region irrespective of variations in output
voltage (shielding effect), thereby iOUT closely tracks iIN. Its output
compliance voltage is 2vDS,sat þVT (here, vDS,sat is the minimum
drain to source voltage required for a MOSFET to operate in sa-
turation region and VT is its threshold). This compliance voltage is
similar to that of Wilson and improved Wilson CMs, and is higher
than the minimum voltage required for M2 and M3 to operate in
saturation region (2vDS,sat) by a value ‘VT’ [3]. The output resistance
Fig. 5. Output voltage vs. output current characteristics at iIN ¼ 10 mA for basic CMs
discussed in Section 2.
and hence the performance of a cascode CM can be further im-
proved by using double cascode CM. The approximate output re-
sistance of a double cascode CM is (gmr0)2r0, however it leads to
further increase in voltage headroom. In modern CMOS low vol-
tage circuits, this problem assumes significance as it leads to re-
stricted usage of cascode CM, in spite of its better current mir-
roring accuracy, higher output resistance and larger bandwidth
[1,18].

Fig. 6. Input resistance as a function of frequency at iIN ¼10 mA for basic CMs dis-
Fig. 2. Current transfer characteristics for basic CMs discussed in Section 2. cussed in Section 2.
 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155 137

improved significantly in Wilson and cascode CMs. Their curves

Fig. 7. Output resistance as a function of frequency at iIN ¼ 10 mA for basic CMs
discussed in Section 2.
for input current vs. input voltage are plotted in Figs. 4 and 5 show
variation in their output current (at iIN ¼10 mA) with output vol-
tage. Fig. 4 illustrates that improvements achieved in Wilson,
improved Wilson and cascode CMs are at the cost of increase in
input compliance voltage and Fig. 5 reflects that in simple CM
channel length modulation effect is maximal. It also shows that
output compliance voltage for Wilson, improved Wilson and cas-
code CMs are approximately similar. Input and output resistances
vs. frequency curves (at iIN ¼ 10 mA) for these CMs are shown in
Figs. 6 and 7 respectively. These figures show that the enhanced
topologies discussed above improve accuracy and output re-
sistance significantly, but at the cost of increased in input re-
sistance. The frequency response plotted in Fig. 8 reflects that
Wilson and improved Wilson CMs have higher bandwidth with
little peaking in their frequency response curves. The comparative
results given in Table 1, show that the improvements in Wilson,
improved Wilson and cascode CMs are achieved at the cost of
higher input and output compliance voltages. Power consumption
of a simple CM should be minimal, however Table 1 shows that
simple CM consumes slightly more power. This is due to the fact
that in a simple CM, output current at the specified input current
(10 mA) was found to be slightly higher than its expected value of
10 mA, though it was almost equal to 10 mA in other configurations.

3. Current mirrors with lower compliance voltage

Fig. 8. Frequency response at iIN ¼10 mA, of basic CMs discussed in Section 2. requirement

Table 1 Various techniques have been reported in literature for the

Comparative results of basic CM architectures for higher accuracy. design of CMs with lower voltage headroom. A few important
techniques are detailed in Section 3.1 and their simulation results
Simple CM Wilson CM Improved Cascode CM
Wilson have been discussed in Section 3.10.

Mirroring accuracya Very poor Poor Very good Very good 3.1. High swing cascode CM (compound CM)
% Error ratio (PER)b 54.89 17.47 0.52 0.51
Vin,dropa(V) 0.5–0.95 1–1.8 1–1.8 1–1.8
Vout,mina(V) 0.1–0.4 0.5–0.9 0.5–1.1 0.5–0.9 In cascode CM (discussed in Section 2), output compliance
Input resistanceb (Ω) 4.5 k 9k 10 k 9k voltage can be reduced by VT, while maintaining MOSFETs M2 and
Output resistanceb (Ω) 200 k 18 M 14 M 14 M M3 in saturation region. The circuit of high swing cascode CM
Bandwidthb (Hz) 1.46 G 3.26 G 3.17 G 908.67 M shown in Fig. 9(a), achieves this low compliance voltage require-
Peaking in frequency Nil 0.12 1.08 Nil
responseb (dB)
ment, while maintaining output resistance equivalent to that of
Power consumedb (W) 33.12 m 25.12 m 28.56 m 28.69 m cascode CM [38]. The reduction in output compliance voltage is
achieved by segregating MOSFETs (M1 and M4) and biasing them
a
For input current range 0–500 mA. separately as shown in Fig. 9(a). In this circuit, the aspect ratio of
b
At input current¼ 10 mA.
M4 is chosen to be one-fourth as compared to rest of the MOSFETs
in the circuit, leading to reduction in the output compliance vol-
These basic CMs along with other circuits to be discussed in the tage by ‘VT’. However, in high swing cascode CM of Fig. 9(a), since
paper have been simulated using Mentor Graphics Eldo spice in vDS1≠vDS2, iOUT is not an accurate replica of iIN [3].
TSMC 0.18 mm CMOS, BSIM3 and Level 53 technology. All the CM
topologies described in the paper have been simulated under ap- 3.2. Low voltage cascode CM
proximately similar conditions to get a fair comparison among
them. To simulate these circuits, a supply voltage of 1.8 V along The structure of low voltage cascode CM is shown in Fig. 9(b)
with a load of 1 kΩ was used. Here, aspect ratio of the MOSFETs [18]. In this circuit, all the MOSFETs operate in saturation region
forming primary CM pair has been chosen to be 5 mm/0.25 mm. and vGS3 ¼vGS4 is ensured by proper selection of their aspect ratios.
However, these circuits may operate at other aspect ratios as well. The gate terminal of M1 is shorted with drain terminal of M4 in
DC analysis of all the circuits has been carried out by varying iIN for order to reduce the minimum voltage headroom by a value ‘VT’.
a sweep of 0–500 mA. However, many CM topologies are specially Here, if VB ¼vGS4 þ (vGS1  VT1)¼vGS3 þ(vGS2  VT2), M1 and M4 will
designed to operate at low currents, thus for the sake of generality operate in saturation region. This structure ensures high accuracy
all the comparisons like percentage error in mirroring accuracy, as vDS1 ¼vDS2 due to shielding effect of M3 and offers output re-
input resistance, output resistance and bandwidth have been sistance equivalent to a conventional cascode CM, while reducing
carried out at a small value of input current equal to 10 mA. the output compliance voltage by ‘VT’. However, it requires an
The current transfer characteristics for these basic CMs, de- additional circuit to generate the required value of VB.
signed for higher accuracy are shown in Fig. 2. To reflect the im-
provement achieved in current mirroring accuracy, their percen- 3.3. Improved high swing cascode CM
tage error ratio (PER) is plotted in Fig. 3. These figures indicate that
current mirroring accuracy of a simple CM is quite poor and is Improved high swing cascode CM shown in Fig. 9(c), generates
138 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155

biasing voltage VB required in low voltage cascode CM with the
help of MOSFET M5 [3]. This configuration provides precise current
mirroring and a high output resistance equivalent to a cascode CM,
while maintaining output compliance voltage equal to 2VDS,sat. The
negative feedback due to M4 equalizes the drain–source voltage of
mirroring MOSFETs (M1 and M2) and eliminates any error due to
channel length modulation effect. However, this is achieved at the
cost of higher power consumption as it requires two reference
current sources.
3.4. Self-biased high swing cascode CM
In self-biased high swing cascode CM (Fig. 9(d)), voltage ‘VB’ of
low voltage cascode CM (Fig. 9(b)) is obtained with the help of a
resistor R. The resistance of R is adjusted in such a manner that the
potential drop across it is VDS,sat and output compliance voltage of
the circuit is 2VDS,sat. Self-biased high swing cascode CM requires
only one reference current source and hence dissipates lower
power. It also maintains a higher output resistance and current
mirroring accuracy equivalent to a conventional cascode CM while
providing high swing operation. However, in self-biased high
swing cascode CM input resistance increases by ‘R’ and since
voltage drop across R need to track VDS,sat for different values of
input current, its output voltage swing is restricted as compared to
high swing cascode CM [3].
3.5. Low voltage tail current source
The low voltage tail current source reported by You et al., de-
signed to operate at low compliance voltage while providing high
output resistance is shown in Fig. 9(e) [11]. It is also known as
bootstrapped configuration. In this circuit, output MOSFET (M2)
mirrors the current injected in M1 and an error amplifier A tries to
maintain equal vDS voltages of both the MOSFETs. This configura-
tion forces a similar change at input node that occurs at output
node with the help of two feedback loops; one formed by negative
feedback consisting of amplifier A and MOSFET M1 at input side
and second one formed by positive feedback consisting of ampli-
fier A and MOSFET M2 at output side. These feedback loops ensure
identical voltages at input and output nodes and thereby reduce
the error due to channel length modulation effect. In this circuit, if
vOUT (voltage at output terminal of CM) varies, the variation in vDS2
(and thereby in vDS1 due to feedback action) is absorbed by am-
plifier A by suitably adjusting the gate voltage of M1 and M2, as
drain current of M1 is fixed (equal to iIN).
In case of matched MOSFETs M1 and M2, the output resistance
of the CM is found to be equivalent to output resistance of input
current source iIN, which is equal to gmr02 in case of cascode cur-
rent source. However, in this CM due to feedback action any
change in vOUT leads to a corresponding change in vIN (voltage at
input terminal of CM). In case of non-ideal current source iIN, this
may further lead to changes in input current. Moreover, its output
resistance is negative due to positive feedback loop at output side
and stability of the circuit can be affected if positive feedback

Fig. 9. CMs with lower compliance voltage requirement (a–l). (a) High swing cascode CM [38]. (b) Low voltage cascode CM [18]. (c) Improved high swing cascode CM [3].
(d) Self-biased high swing cascode CM [14]. (e) Low voltage tail current source [11]. (f) Low voltage CM exploiting positive shunt feedback [39]. (g) Level shifted simple CM
[16]. (h) Level shifted cascode CM [16]. (i) Level shifted simple CM with unbalanced differential amplifier [16]. (j) Triode region simple CM [41]. (k) Triode region cascode CM
[17]. (l) Triode region cascode CM with adaptive biasing [17].
 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155
Fig. 9. (continued)
overcomes negative feedback.
3.6. Low voltage CM exploiting positive shunt feedback
The circuit of low voltage CM based on positive shunt feedback
is shown in Fig. 9(f) [39]. This circuit is based on bootstrapped
configuration discussed in Section 3.5. It exploits the positive
shunt feedback configuration to maintain high output resistance
and good current mirroring accuracy, while maintaining low va-
lues of input and output compliance voltages. In this CM, with
139
increase in vOUT, due to channel length modulation effect iOUT in-
creases, thus output resistance is positive.
In this circuit, voltage appearing at the input terminal (vIN) is
decoupled from vOUT by using an additional feedback circuit con-
sisting of MOSFET M3 and amplifier A at input side. This maintains
the drain current of M1 constant irrespective of changes in output
voltage. However, stability of the circuit can also be affected if
positive feedback overcomes negative feedback.
3.7. Level shifted CM
The gate–drain connections used at input side of simple and
cascode CMs increase their input compliance voltages by ‘VT’ and
‘2VT’ respectively, than the required values for proper operation of
these circuits. In level shifting technique, a voltage drop lower
than VT is introduced between drain and gate terminals of the
MOSFET connected as diode at input side. This technique helps in
lowering the input compliance voltage (and thereby output com-
pliance voltage in certain cases) of the circuit without affecting its
dc operation and input and output resistances. The structures of
level shifted low voltage simple and cascode CMs are shown in
Fig. 9(g) and (h) respectively [16]. Here, the required level shift is
obtained either by a constant gate–source voltage across MOSFET
ML1 or through a constant base–emitter voltage across Bipolar
Junction Transistor (BJT) Q1. In this technique, polarity of level
shifting transistors must be opposite to that of mirroring transis-
tors. However, level shifters implemented with MOS transistors
suffer from the fact that if body effect becomes significant, the
mirroring transistors may turn off. DC level shifters implemented
by BJTs face a limitation that in an integrated circuit fabrication of
only one type of mirror (either n-type or p-type) is possible. These
limitations can be overcome by use of an unbalanced differential
pair instead of level shifting transistors as shown in Fig. 9(i)
[16,40]. In this circuit, MOSFETs ML1, ML2 and biasing current
sources IB1 and IB2 are used to implement the unbalanced differ-
ential pair. The difference of the gate voltage of ML1 and ML2
provides the required voltage shift with requisite polarity. The
required voltage difference for proper operation of the circuit can
be obtained by optimal selection of the aspect ratios of ML1 and
ML2 along with bias currents IB1 and IB2. In level shifter im-
plementation using unbalanced differential pair the gate–source
voltage of PMOS is stacked over gate–source voltage of NMOS, thus
it needs slightly more supply voltage than the technique used in
Fig. 9(g).
This level shifting technique can reduce the input and output
compliance voltages of simple and cascode CMs to vDS,sat. and
2vDS,sat. respectively. However, it increases the power consumption
and complexity of the circuit. Moreover, in this technique the gate
source capacitances of level shifting transistors appear in shunt
with Cgs of basic CM pair, thus bandwidth of the circuit gets
reduced.
3.8. Triode region simple CM
A low voltage simple CM with input MOSFET working in triode
region proposed by Prodanov and Green is shown in Fig. 9(j) [41].
In this circuit, diode connected MOSFET Mb1 biased by a constant
current source IB, shifts the drain voltage of MOSFET M1 to ensure
that it operates in triode region. In the circuit, considering MOSFET
Mb1 in saturation region, it can be seen that:
⎛ 2IB ⎞
vDS1 = vGS1 − ⎜⎜ VT + ⎟⎟
⎝ βMb1 ⎠ (4)
where β is the transconductance parameter of the corresponding
MOSFET. Eq. (4) shows that M1 operates in triode region and the
140 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155

current flowing through it can be calculated as:

Good till (10 mA, as

Triode region cas-

0–1.06 (till 10 mA)

β1 β
iD1 =
2
( vGS1 − VT )2 − β 1 IB = iIN + IB
(5)

IB ¼ 10 mA)
Mb1

code CM

33.98 m
0.1–0.5

1.5 M
Eq. (5) shows that drain current of M1 depends upon biasing

20 k
0.51
current IB and ratio of transconductance parameters of M1 and
Mb1. This occurs because the potential difference between gate

Poor (with an offset

Triode region sim-
and drain terminals of M1 is fixed irrespective of the variations in

current of 48 mA)
input current and depends on the device parameters of Mb1 and

0.025–0.425
its biasing current IB. In the circuit, assuming M1 and M2 to be

116.11 m
ple CM

0.2–0.4
matched and i2 operating in saturation region, current through M2

26.78

1.6 k
70 k
using Eq. (5) can be given as:
⎛ β ⎞
iD2 = iOUT = iIN + ⎜ 1 + 1 ⎟ IB

with differential amplifier

Level shifted simple Level shifted simple CM
⎝ βMb1 ⎠ (6)

Eq. (6) shows that the output current contains an additional

offset term. This circuit operates at low voltage due to small vol-
tage drop (equal to vGS1) at node X. However, accuracy of this CM is

41.345 m
not very good due to presence of channel length modulation effect

0.1–0.4

200 k
54.45
0.5–1
Poor
in M2. Moreover, due to triode mode operation of M1, bandwidth

5k
of the CM is also poor.

Poor with an offset

current of 45 mA
3.9. Triode region cascode CM

The circuit of triode region cascode CM is shown in Fig. 9(k)

111.02 m
0.1–0.4
0–0.45
21.66
[17]. In this circuit, MOSFETs M1 and M2 behave as primary CM

1.5 k
70 k
CM
pair operating in saturation region. MOSFETs M3 and M4 behave as
active resistors appropriately biased through diode connected

CM exploiting posi-
MOSFET M5 and operate in triode region. This circuit resembles a
simple CM, with M1 and M2 having source degeneration and iOUT
tive feedback

Equal to load
closely tracks iIN. The mirror has higher output resistance
Very good

resistance
523.47 m
0.1–0.45
equivalent to a conventional cascode CM, even at a output voltage

0.2–1.8

4.8 k
0.84
lower than 2vDS,sat., due to degeneration resistor (MOSFET M4).
This CM operates at a lower supply voltage but its operative cur-
rent range is limited, as iIN must be lower than IB.

Equal to load
This limitation can be overcome with the help of adaptive
Tail current

resistance
biasing method shown in Fig. 9(l) [17]. In this technique, in addi-
0.4–0.45

523.10 m
0.1–0.45
source

tion to output branch (MOSFETs M2 and M4), input current is also

Better

0.24

300

mirrored in a branch composed of MOSFETs M5 and M7 and ‘A’

times of the input current is copied in branch constituted by
swing cascode CM

MOSFETs M6 and M9. Hence, biasing current provided by MOSFETs

High swing cas- Improved high swing Self-biased high

M6 and M9 is equivalent to A  iOUT. This ensures proper operation

of circuit for all values of input current when A 41, as biasing
current remains greater than iIN. However, the accuracy of triode
26.86 m
0.1–0.7
0.6–1.6
Better
Comparative results of CMs with lower compliance voltage requirement.

800 k
17.43

region cascode CM is not as good as that of conventional cascode

5k

CM.

3.10. Simulation results of CMs with lower compliance voltage

requirement
cascode CM

30.48 m
0.1–0.7

Comparative simulation results of these techniques based on

Better

0.5–1
18.02

3M
6k

parameters discussed in Section 2, are summarized in Table 2. The

comparison reveals that tail current source (Fig. 9(e)) employing
positive feedback reduces the input and output compliance vol-
For input current range 0–500 mA.

tages maximally, while maintaining good accuracy and low input

code CM

resistance. However, due to requirement of a voltage amplifier it

25.61 m
0.1–0.7
20.37
0.5–1
Good

14 M

At input current ¼ 10 mA.

consumes more power. It is observed that in comparison to triode

4k

region simple CM, triode region cascode CM has very high output
resistance and improved current mirroring accuracy.
Input resistanceb (Ω)
Mirroring accuracya

% Error ratio (PER)b

Output resistanceb

Power consumedb
Vout,mina (V)
Vin,dropa (V)

4. Current mirrors with lower input resistance

(W)
Table 2

(Ω)

A lower input resistance is required by a CM to avoid loading

b
a

effect at its input side. Conventionally input resistance of a CM can

 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155 141

VDD

VDD
IB=10u

IB=10u IB=50u IB=10u

iIN
- A
iIN iOUT
VD =1.5V
iOUT
A 5 M3
0.25
36
M5 M4 M3
0.18
M1 M2 iIN 5 iOUT
0.25
0.25 0.25
5 5
M1 M2
0.25 0.25 M1 M2

5 3.6 3.6
5
0.25 0.54 0.54
0.25

Fig. 10. CMs with lower input resistance (a–f). (a) Active CM [42]. (b) FVF CM [44]. (c) Schematic of very low input resistance CM [46].

Table 3 4.2. Flipped voltage follower (FVF) CM

Comparative results of different CM topologies for lower input resistance.
The circuit of FVF CM shown in Fig. 10(b), offers low input re-
Active CM FVF CM Very low input im-
pedance CM sistance due to negative feedback provided by MOSFET M5 and
current source IB [44,45]. Here, drain current in M5 remains con-
Mirroring accuracya Good Good till Good stant due to biasing current source IB. Thus, vGS5 and thereby vDS1
150 mA
remain constant at a value dependent on biasing current IB, lead-
% Error ratio (PER)b 10.61 0.1 30.16
Vin,dropa (V) 1.5 (equal to 0.495–0.53 0.87–1.4 ing to lower input resistance of the CM. In FVF CM, the variations
VD) in input current are absorbed by M1 causing an appropriate
Vout,mina (V) 0.1–0.4 0.15–0.6 0.2–0.6 change in its gate–source voltage which is reflected in the output
b
Input resistance (Ω) 300 930 10
current (iOUT) due to CM action. Diode connected MOSFET M4
Output resistanceb (Ω) 250 k 8.6 M 350 k
Power consumedb (W) 1.1 m 99.86 m 247.98 m provides proper biasing to gate terminals of M3 and M5. Input
compliance voltage and input resistance of FVF CM are very small
a
For input current range 0–500 mA. and are given as:
b
At input current¼ 10 mA.
1
vIN, min . ≈ VDS1, sat .; rin ≈
be reduced either by increasing width of input transistor or by gm1gm4 r04 (8)
raising its dc biasing current, though at the cost of higher chip area
FVF CM operates at low voltage, offers very low input resistance
and increased power consumption. Various topologies have been
and high output resistance equivalent to a conventional cascode
reported in literature to improve the input resistance of a CM by
CM. However, its range of operation is limited as the MOSFETs M1–
using active feedback techniques and are summarized in Section
4.1 and their comparative simulation results are illustrated in M5 must operate in saturation region, with a further restriction
Section 4.4. that this limitation cannot be improved even by increasing supply
voltage of the circuit [44].
4.1. Active CM
4.3. CM with very low input resistance
An active CM shown in Fig. 10(a) maintains a constant voltage
equal to VD at the input terminal irrespective of the input current, The conceptual schematic of very low input resistance CM
with the help of an amplifier A [13,42,43]. Thus, the variations in proposed by Baghtash and Azhari is shown in Fig. 10(c) [46]. Here,
input current do not affect vDS of MOSFT M1. This leads to sig- a MOSFET M3 is connected in series with the input terminal of
nificant reduction in input resistance of the CM and minimizes the MOSFET M1 and gate voltage of M3 is controlled by an inverting
loading effect on previous stage. Input resistance of the mirror is amplifier A. The amplifier helps in maintaining a near constant
given as: potential at the source terminal of M3 by appropriately adjusting
the gate voltage of M3 corresponding to the variations in iIN. This
rin = 1/Av gm (7)
leads to reduction in input resistance of the CM by a factor equal to
where Av is the voltage gain of amplifier A. Eq. (7) shows that input the gain of amplifier A.
resistance of active CM gets reduced by a factor of Av as compared Three different MOSFET implementations of amplifier A were
to a simple CM. Active CM improves the accuracy to certain extent discussed in [46]. In first implementation two MOSFETs (NMOS
by reducing the input resistance of CM. However in this circuit, and PMOS), operating in saturation region were used. In second
range of input current is limited by the value of reference voltage ( implementation to increase the gain of amplifier, self-cascode to-
VD). A larger value of VD permits a higher input current while pology (elaborated in Section 5.3) has been used. In third im-
maintaining MOSFET M1 in saturation region. plementation, to further increase the gain of amplifier, two stages
142 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155

iOUT
VDD
D
5 IB=10u
VD A M3 iOUT ID2
0.25 D
iIN
iIN 5 M3
0.25 M2= mW/L ID
+
G VGS2 G
M4
- ID1 +
5
M1 M2 M1 M2
0.25 M1= W/L VGS
- S
5 5 +
5 5 0.25 0.25
0.25 0.25 VGS1
- S

VDD VDD

20
M7
0.58 2 M6 0.18
iIN
0.18 2
M4 IB=10u IB=10u
iOUT
VB=0.8V
50 iOUT
M3
0.25
Cex=0.1u M4 M3 -A M5
0.9 5
iIN 5 5
0.25 0.25
0.25 0.25
M2 M5
M1
5 M1 M2
5
0.25
0.25 5 5
0.25 0.25

VDD

IB1=10u
IB=10u
IB=10u

M6
VB=0.8V iOUT
5
0.25
M4 M3 M5

5 5
iIN 5
0.25 0.25
0.25

M1 M2
5
0.25 5
0.25

Fig. 11. CMs with higher output resistance (a–f). (a) Active-feedback cascode CM [47]. (b) Regulated cascode CM [48]. (c) Two transistor composite structure of self-cascode
MOSFET along with its equivalent structure [31]. (d) Low voltage CM based on self-cascode MOSFET [9] (capacitance with capacitor (shown dotted) is of capacitively
compensated self-cascode CM [56]). (e) Schematic of low voltage CM with super-cascode configuration [53]. (f) Simple implementation of CM shown in Fig. 4 (e) [53].
 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155 143

were used in cascade. This architecture reduced the input re-
sistance of the circuit in the range of a few mΩ, without increasing
its supply voltage requirement.
4.4. Simulation results of CMs with lower input resistance
Comparative simulation results of the CM topologies discussed
in Section 4.1, for improvement in input resistance is given in
Table 3. All these topologies represent a great improvement in
input resistance. The simulations carried out demonstrate that the
input compliance voltage of active CM is dependent on biasing
voltage VD and a lower input resistance is achieved only for small
frequency range. Furthermore, it consumes a significant amount of
power as well. Table 3 depicts that the CM structure suggested by
Baghtash and Azhari [46] provide very low input resistance at the
cost of increased input compliance voltage. The comparison shows
that FVF CM provides a lower input resistance at comparatively
lower input and output compliance voltages. However, its oper-
ating current range is comparatively low, as was discussed in
Section 4.2.
5. Current mirrors with higher output resistance
Some techniques like Wilson CM, improved Wilson CM and
cascode CM discussed in Section 2 for improving the accuracy of a
simple CM increase its output resistance as well. A few more
techniques available in literature for enhancement of output re-
sistance of a CM are detailed in Section 5.1, followed by their si-
mulation results in Section 5.5.
5.1. Active feedback cascode CM
Active feedback cascode CM proposed by Yang and Allstot
(Fig. 11(a)) improves the performance of a cascode CM without
increasing its voltage headroom [47]. This CM in addition to the
series feedback present in cascode configuration, employs a ne-
gative series feedback through voltage amplifier A. The negative
feedback offered by amplifier A maintains the drain voltage of M2
constant (equal to VD) irrespective of the variations in output
voltage. This makes the output current constant and independent
of the changes in output voltage leading to a significant increase in
the output resistance. The output resistance offered by an active-
feedback cascode CM is Av  gm3r03 times that of a simple CM. This
configuration provides output resistance equivalent to a double
cascode CM, while its required voltage headroom is equivalent to
that of a conventional cascode CM. However, it operates well as
long as M2 operates in saturation region. This condition depends
on voltage VD, input current and load impedance at output node of
the CM.
5.2. Regulated cascode CM
5.3. CM based on self-cascode MOSFET
Self cascode MOSFET structure helps in providing higher output
resistance without increasing the required output voltage. A self-
cascode MOSFET is a two MOSFET structure as shown in Fig. 11(c),
which can be treated as a single composite MOSFET with much
higher effective channel length and output resistance [50]. For
optimal operation, aspect ratio of M2 must be higher than that of
M1. Assuming equal lengths of M1 and M2 and width of M2 to be
‘m’ times larger than M1, dc-equivalent width and length of the
composite structure are given as:
Weq . = W2; L eq . = L2 + mL1 (10)
Eq. (10) shows that the composite structure behaves as a long-
channel transistor, when m 4 1. Since drain currents of M1 and M2
are equal, current density of M2 is much lower than M1 and the
composite structure has much lower output conductance due to
lower current density at the drain terminal. Equivalent output
resistance (r0,eq.) and trans-conductance (gm,eq.) of the composite
structure are given as [51,52]:
g m2
r0, eq . ≈ (m + 1) r02; gm, eq . ≈
m+1 (11)
In composite structure, M1 always operates in triode region,
hence there is no appreciable increment in equivalent vDS,sat. Self-
cascode structure offers higher output resistance equivalent to a
conventional cascode configuration while consuming output vol-
tage headroom comparable to a single MOSFET and can be used to
design high performance low voltage circuits.
A low voltage CM based on self-cascode MOSFET, with output
resistance similar to a conventional cascode CM is shown in Fig. 11
(d) [51]. In the circuit, M2 operates in triode region, thus output
compliance voltage of the CM is less than vDS2,sat. þvDS3,sat., which
is much lower than a conventional cascode CM. MOSFET M4 is
used as a level shifter to reduce input compliance voltage of the
circuit. However, accuracy of this CM is lower than that of a con-
ventional cascode CM.
5.4. Low voltage CM with super-cascode configuration
The schematic of low voltage CM with super-cascode config-
uration at output side is shown in Fig. 11(e) [53,54]. This circuit
forces equal drain–source voltages of MOSFETs M1 and M2 form-
ing primary CM pair, by means of MOSFET M4, current source IB,
and voltage source VB. Biasing potential at gate terminal of MOS-
FET M5 is provided through drain terminal of M3 and the requisite
Table 4
Comparative results of different CM topologies for higher output resistance.
Regulated Low voltage CM Low supply voltage CM
cascode CM based on self- with super cascode
cascode MOSFET configuration

In regulated cascode CM shown in Fig. 11(b), the amplifier A of Mirroring Very good Good Very good
active feedback cascode CM (Fig. 11(a)) is implemented as a accuracya
% Error ratio 0.38 18.93 0.09
common-source stage [3,48,49]. This configuration provides sig- (PER)b
nificant improvement in output resistance due to negative feed- Vin,dropa (V) 0.05–1 0.05–0.4 0.265–0.275
back provided by common-source MOSFET M4 and biasing current Vout,mina (V) 0.69–0.72 0.2–0.4 0.3–0.6
source IB. Its small-signal output resistance is given as: Input resistanceb 4.86 k 2k 60
(Ω)
rout = r02 + r03 + r02 gm3 r03 ( 1 + gm4 r04 ) ≈ r02 ( gm3 r03 )( gm4 r04 ) (9) Output 826 M 5.44 M 15 G
resistanceb (Ω)
Eq. (9) shows that output resistance of this CM is approxi- Power consumedb 25.76 m 30.06 m 39.37 m
(W)
mately equal to that of a double cascode CM, while its output
compliance voltage is similar to a conventional cascode CM. a
For input current range 0–500 mA.
However, it consumes higher power than cascode CM. b
At input current¼10 mA.
144 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155
Fig. 12. Techniques to improve bandwidth of a CM (a–e). (a) Simple CM with resistive compensation technique [15]. (b) Improved high-swing cascode CM with resistive
compensation technique [15]. (c) Resistively compensated simple CM with active replacement [55]. (d) Simple CM with inductive compensation [58].
polarity is achieved with the help of inverting amplifier A. Output
resistance of the circuit increases further if the amplifier's gain is
greater than unity. A simple implementation of this CM is shown
in Fig. 11(f). In this circuit, amplifier A is formed by MOSFET M6
and current source IB1. Here, MOSFETs M3, M5, M6 and current
sources IB and IB1 implement a super-cascode transistor. This cir-
cuit has very high output resistance in GΩ range, given as:
rout ≈ gm6 r06 gm5 r05 gm3 r03 r02
In this configuration, negative feedback loop formed by super-
cascode transistor ensures vDS1 ¼ vDS2, thereby nullifying any error
in accuracy due to channel length modulation effect. However, it
requires higher number of current sources and hence consumes
more power.
5.5. Simulation results of CMs with higher output resistance
Simulation results of these CM topologies reported for im-
proving output resistance are summarized in Table 4. Their com-
parative study shows that these topologies not only increase
output resistance of a CM but also improve its current mirroring
accuracy. The simulations represent that CM with super-cascode
configuration provides maximum improvement in output re-
sistance, though with slight increase in power consumption.
6. Techniques to improve bandwidth of a current mirror
Bandwidth of a CM decides overall speed of the circuit. It
mainly depends on capacitance Cgs and gm of the MOSFETs forming
primary CM pair and can be improved to a certain extent by in-
creasing dc biasing current of these MOSFETs. However, this leads
to increase in power consumption. Moreover, in devices based on
short channel MOSFETs, bandwidth gets increased due to reduc-
tion in Cgs. However, with the advancement in technology, devices
operating at even higher bandwidth and having higher speed are
required. Thus, various techniques have been designed to improve
the bandwidth of a CM. Some important ones are discussed in
Section 6.1 and their simulation results are presented in Section
6.4.
(12)
6.1. Resistive compensation technique
An efficient and effective technique to improve the bandwidth
of a CM by applying resistive compensation scheme was reported
in literature by Voo and Toumazou [15]. In this technique, band-
width of the CMs whose transfer function is similar to that of a low
pass filter can be enhanced by adding a compensating resistor
between common gate terminals of the MOSFETs forming primary
CM pair. Simple CM and improved high-swing cascode CM in-
corporating resistive compensation technique are shown in Fig. 12
(a) and (b) respectively. Here, the compensating resistor delays the
response of the CM and introduces a pair of pole and zero in its
transfer function. Bandwidth of the circuit is increased by properly
adjusting the value of compensating resistor to cancel dominant
pole of the transfer function by the zero introduced due to use of
compensating resistor. The transfer function of simple CM with
resistive compensation is given as [15]:
iOUT (s ) gm2 ( sCgs1R + 1)
= 2
iIN (s ) s Cgs1Cgs2 R + s ( Cgs1 + Cgs2 ) + gm1 (13)
In Eq. (13), if R is chosen to be equal to 1/gm1, bandwidth in-
creases by a factor of 2. Bandwidth can be further improved by
increasing the value of compensating resistor, though this leads to
peaking in frequency response. This compensation technique
 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155 145

increases the bandwidth of CM without influencing its dc
characteristics.
In fully monolithic integrated circuits utilization of passive re-
sistors is not preferred, as they are either made of poly-silicon or
by diffusion process and require large chip area and have large
tolerances. A technique to replace these passive resistors with
active components was suggested by Voo and Toumazou [55] and
is shown in Fig. 12(c). Here R is replaced by MOSFET M3 whose
channel resistance must be equal to 1/gm1 for optimal bandwidth.
To achieve this, gate voltage of M3 is controlled by voltage Vtu
produced by MOSFETs M4, M5 and M8. In the circuit, M3 operates
in triode region while M4, M5 and M8 operate in saturation region.
The channel resistance of M3 is given as:
1 poles in the modified CM depends on the value of inductor used.
r03 =
μCox (W /L )3 ( vGS 3 − VT )
Equal aspect ratios and biasing currents of M1 and M4 leads to
equal voltages at nodes 1 and 2, this ensures vGS3 ¼vGS5. Hence,
channel resistance of M3 can be maintained equal to 1/gm1, by
tuning Itu and controlling vGS5 and thereby vGS3. Though, this
technique replaces passive resistors with MOSFETs, it consumes
more power.
6.3. Inductive series-peaking technique
Fig. 12(d) shows a technique used to increase the bandwidth of
a CM using inductor [58,59]. A compensating inductor is added
between gate terminals of the MOSFETs forming primary CM pair.
The transfer function of simple CM with inductive compensation is
given as [58]:
iOUT (s ) g m2 / g m1
= 3
iIN (s ) s LCgs1Cgs2/gm1 + s2LCgs2 + s ( Cgs1 + Cgs2 )/gm1 + 1 (16)
The inductor appears in series with Cgs of the MOSFETs and
leads to peaking in frequency response of the circuit, hence known
as inductive series-peaking technique. The inductor introduced
does not affect the dc characteristics of the CM. New location of
(14) Maximum bandwidth with minimal ringing in time domain can be
achieved through this technique by properly sizing the peaking-
inductor, based on the criterion of critical damping. If Cgs2»Cgs1 and
L¼ Cgs2/(4gm12), bandwidth approximately twice that of simple CM
can be achieved with almost no ringing [58]. However, this tech-
nique suffers from inherent problems of on-chip inductor
fabrication.
6.4. Simulation results of techniques to improve bandwidth of a CM

6.2. Capacitive compensation technique The comparative results obtained at the time of simulation for
various techniques suggested for improvement in bandwidth of a
The circuit of low voltage CM with capacitive compensation CM discussed above are shown in Table 5. These results show that
technique is shown in Fig. 11(d) [56,57]. Here, an external capa- bandwidth of a CM can be improved significantly by using re-
citance Cex is added between the gate and source terminals of level sistive compensation technique and inductive-series peaking
shifting MOSFET M4. The total input capacitance of this circuit is technique, without altering dc characteristics of the CM. However,
given as [56]: inductive compensation technique has inherent disadvantage of
complexity involved in implementation of on-chip inductor. Al-
Cin = Cgd4 + Cgs1 + Cgd1 −
( Cgs4 + Cgd1 + Cex ) though, capacitive compensation technique helps in increasing the
r04 gm4 (15) bandwidth but its application is restricted to limited CMs.

Hence, the additional capacitance (Cex), decreases the effective

input capacitance by Cex/(r04gm4) and shifts the dominant pole
location away from the imaginary axis in s-plane leading to in-
crease in bandwidth. Capacitive compensation technique provides
increase in bandwidth without altering dc characteristics and
power consumption of the circuit. However, application of this
technique is limited to the CMs that have level-shifting MOSFET at
input side similar to the CM shown in Fig. 11(d).
7. Low voltage current mirrors
Nowadays, with advancement in technology small portable
devices operating at lower supply voltage are in demand. With
down scaling of transistor dimensions, the threshold voltage is not
being scaled down by the same factor. This places a constraint on
scaling of supply voltage. For low voltage circuit design, either VT

Table 5
Comparative results of different techniques to improve bandwidth of a CM.

Simple CM Improved high swing cascode CM Low voltage CM based on self-cascode

MOSFET

Without Resistance Inductance Without Resistance Without Capacitance

compensation compensation compensation compensation compensation compensation compensation

Mirroring accuracya Very poor Very poor Very poor Very good Very good Very good Very good
% Error ratio (PER)b 0.5–0.95 0.5–0.95 0.5–0.95 0.5–1 0.5–1 0.05–0.4 0.05–0.4
Vin,dropa (V) 0.1–0.4 0.1–0.4 0.1–0.4 0.1–0.7 0.1–0.7 0.2–0.4 0.2–0.4
Vout,mina (V) 4.5 k 4.5 k 4.5 k 6k 6k 2k 4k
Input resistanceb 200 k 200 k 200 k 3M 3M 350 k 5M
(Ω)
Output resistanceb 33.12 m 33.178 m 33.18 m 30.48 m 30.48 m 30.06 m 30.06 m
(Ω)
Bandwidthb (Hz) 1.46 G 2.69 G (R ¼5 kΩ) 3.48 G (L ¼ 350 nH) 858.07 M 1.15 G (R¼ 10 kΩ) 15.85 M 292.98 M
(C ¼0.1 mF)
Peaking in fre- Nil Nil Very little Nil Nil Nil Nil
quency responseb

a
For input current range 0–500 mA.
b
At input current¼ 0 mA.
146 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155

iIN
iOUT
iIN iOUT
iIN VB=1.5V

iOUT
M4 M3 VDD =1V VDD=1V
5 5 M1 M2
M2 0.25 VB=1V 0.25
M1 VX VY
5 5
5 5 M1 M2 0.25 0.25
0.25 0.25
5 5
0.25 VB=0.75V 0.25

VDD

IDSS=10u IDSS=10u

iIN iOUT

M4 M3
5 5
0.25 0.25

M1 M2
5
5
0.25
0.25

Fig. 13. Low voltage CMs (a–d). (a) FGMOS transistors based simple CM [20]. (b) FGMOS transistors based cascode CM [21]. (c) Bulk-driven simple CM [22]. (d) Bulk-driven
cascode CM [23].

has to be reduced or threshold voltage drop has to be isolated from
signal path. Various techniques have been developed for operating
CM with low supply voltage. A few important techniques are listed
in Section 7.1 and their simulation results are discussed in Section
7.6.
7.1. FGMOS transistors based simple CM
Floating Gate MOS (FGMOS) transistor has multiple control
gates which are capacitively coupled to the floating gate [20]. The
gate terminals at which signal and biasing voltages are applied are
denoted as signal gate and bias gate respectively. In FGMOS tran-
sistors, effective threshold voltage seen through the signal gate can
be adjusted or even practically be canceled by varying the dc
voltage applied at the bias gate [20,60–63]. Thus, supply voltage
requirement of a circuit can be reduced by replacing MOSFETs
with FGMOS transistors having lower effective threshold voltage.
Fig. 13(a) shows a low-voltage simple CM implemented using two-
input FGMOS transistors [20]. In the circuit, one of the input
terminals of each FGMOS transistor is connected to a dc bias vol-
tage (VB), while the other terminal is used as a conventional input
terminal. Supply voltage requirement of both input and output
sides become independent of threshold voltage as it is almost
removed from the signal path and can be reduced to the level
required for signal variations only [20].
FGMOS transistor based CMs face the problem of charge being
accumulated on the floating gate, at the time of fabrication process
which reduces the controllability of threshold voltage. However,
removal of this trapped charge in FGMOS transistor is possible by
using the methods suggested in [64,65]. As compared to a con-
ventional MOSFET, FGMOS transistor has smaller transconduc-
tance, larger output conductance and poor bandwidth due to
presence of parasitic capacitors [66,67]. Furthermore, the fabrica-
tion process of these CMs is more complex and occupies more
silicon area due to requirement of multiple polysilicon layers
[20,21,67]. It has also been observed that in low nanometer
technologies floating gate approach is not so good due to gate
leakage.
7.2. FGMOS transistors based cascode CM
A low voltage cascode CM based on FGMOS transistors is
shown in Fig. 13(b) [21]. Here, transistors M1–M4 are two-input
floating-gate transistors. In these transistors, biasing voltage VB is
used to form the conduction channel. In this circuit, similar to a
conventional cascode CM, vDS2 is equal to vDS1, if (W/L)2/(W/L)1 ¼
(W/L)3/(W/L)4. This ensures that the output current is equal to
input current, if all FGMOS transistors are maintained in saturation
region. This CM operates at a much lower voltage in comparison to
a conventional cascode CM. However, it faces the problems dis-
cussed in previous sub-section.
7.3. Bulk-driven CM
The circuit of a simple bulk-driven CM is shown in Fig. 13(c)
[22]. A bulk-driven CM utilizes a bulk-drain connection instead of
 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155 147

drain–gate connection used in a simple CM. Here, an input signal is 7.5. Multi-threshold CMs
applied at the bulk-terminals instead of gate-terminals. This fea-
ture removes the requirement of threshold voltage from signal In literature the possibility of multi-threshold (multi-VT) tran-
path and thereby reduces the required supply voltage. An inver- sistors have also been explored to reduce the required supply
sion layer is formed in MOSFETs M1 and M2 by connecting their voltage of various CMs [68,69]. In Fig. 10(b), if M5 have lower
gate terminals with a positive supply voltage (VDD), greater than or threshold voltage as compared to M1 and M2 the supply voltage
requirement of overall circuit can be correspondingly reduced.
equal to |VT|. In the circuit, negligible values of bulk currents have
This occurs as in this circuit for all MOSFETs to operate in sa-
to be ensured and hence source–bulk junctions can only be slightly
turation region following condition must be satisfied:
forward biased. This leads to triode mode operation of M1. How-
ever, M2 is free to operate in saturation region and the expression VDD > VT 5 + VOV 5 + VDSsat1 + ΔVB (19)
for output current in relation to input current can be found as [22]: where VOV5 is overdrive voltage of M5 and ΔVB is difference of
β ⎛ i2 i v2 ⎞
voltage appearing at gate terminal of M3 as compared to VDD. In
iD2 = iOUT = 2 ⎜⎜ 2 IN2 + IN + DS1 ⎟⎟ ( 1 + λvDS2 ) case the biasing voltage at gate terminal of M5 is realized by a
2 ⎝ β1 vDS1 β1 4 ⎠ (17) transistor bias circuit, then ΔVB has to be greater than VDSsat [69].
Eq. (17) shows that if aspect ratios of M1 and M2 are chosen to In similar fashion multi-VT approach can be used in different
ways in various CMs to reduce their supply voltage requirement. In
be equal, then iOUT≠iIN. Hence, better current matching can be
Fig. 10(b), supply voltage requirement can be reduced by using M1
obtained by careful selection of unequal aspect ratios of the two
of higher VT as compared to M2 [70]. Moreover, supply voltage
MOSFETs. Input and output resistances of the bulk-driven CM are
requirement of simple CM (shown in Fig. 1(a)) can also be reduced
given as [22]: by taking M1 of higher VT than M2 [70]. Though, in these cases the
1 ⎛⎜ 2 2ϕF − vBS ⎞ reduction in power supply is obtained with slight compromise in
1 ⎟⎟; 1
rin = = rout = current mirroring accuracy. Multi-VT approach reduces the supply
gmb gm ⎜⎝ γ ⎠ λiD, sat . (18) voltage requirement, however, at the cost of increase in fabrication
area and leakage current. Hence, this technique is more commonly
Eq. (18) shows that input resistance of bulk-driven CM is
used in digital circuits based on 65 nm or lower nanometer
greater than simple gate-driven CM, while its output resistance is
technologies.
comparatively lower. However, for the entire input current range
its corresponding input compliance voltage is very low as com- 7.6. Simulation results of low voltage CMs
pared to a gate-driven CM.
Table 6 shows the comparative simulation results of the CM
topologies discussed in Section 7.1. This comparison reveals that
7.4. Bulk-driven cascode CM
improvement achieved in input and output compliance voltages is
more in case of bulk-driven CMs, though at the cost of reduction in
The circuit of low voltage bulk-driven cascode CM is shown in
accuracy and increase in power consumption.
Fig. 13(d) [21,23]. This configuration significantly improves the
current mirroring accuracy as compared to a simple bulk-driven
CM, as both the MOSFETs forming primary CM pair (M1 and M2) 8. High-performance current mirrors reported in literature
operate in triode region. Furthermore, cascoding of the devices
increase output resistance of the CM to much higher values in Various architectures using the techniques discussed above
comparison to a simple bulk-driven CM. In this circuit, a lower have been proposed in literature to obtain very high performance
value of input voltage is required for a given drain current. How- low voltage CMs. Some of these important architectures are listed
ever, bandwidth of bulk-driven cascode CM is smaller than a gate- in Section 8.1 and their simulation results are discussed in Section
driven cascode CM due to its comparatively large input capaci- 8.9.
tance. Thus, bulk-driven cascode CM can be operated at a lower
8.1. Active-input regulated cascode CM [13]
supply voltage compared to a gate-driven CM with some com-
promise in other performance parameters.
The circuit of an active-input regulated cascode CM is shown in
Fig. 14(a) [13]. The circuit combines input stage of active CM
Table 6
Comparative results of CM topologies for low voltage operation. (Fig. 10(a)) with active-feedback cascode output stage (Fig. 11(a)).
In this circuit, amplifiers A1 and A2 improve input and output
FGMOS FGMOS cas- Bulk-driven Bulk-driven resistances by a factor of Av1 and Av2 respectively (here Avi is the
simple CM code CM simple CM cascode CM voltage gain of amplifier Ai). These amplifiers also improve the
Mirroring Poor Excellent No matching Very poor
accuracy of CM significantly. Here, since vDS1 and vDS2 are fixed to
accuracya a constant value (VD), the circuit can be operated even when the
% Error ratio 53.3 0.84 – – MOSFETs are in triode region. However, accuracy of the CM gets
(PER)b reduced when the output voltage approaches VD. As this config-
Vin,dropa (V) 0.5–1.5 0.2–1.8 0–0.25 0–0.22
uration uses two amplifiers to compare voltage at input and out-
Vout,mina (V) 0.2–0.45 0.2–0.45 0.2–0.3 0.6–0.8
Input resistanceb 9k 13 M 350 350 put nodes, more power is consumed and it requires larger chip
(Ω) area. Moreover, to certain extent the accuracy of CM depends on
Output resistanceb 200 k 28 k 15 k 30 k the gain of these amplifiers.
(Ω)
Power consumedb 33.18 m 25.165 m 411.71 m 1.3 m 8.2. Wide swing triode-region cascode CM [41]
(W)

a
For input current range 0–500 mA. The structure of wide swing triode region cascode CM is shown
b
At input current¼ 10 mA. in Fig. 14(b) [41]. This circuit operates at low supply voltage as M1
148 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155

Fig. 14. High-performance CMs reported in literature (a–k). (a) Active input regulated cascode CM [13]. (b) Wide swing triode region cascode CM [41]. (c) Regulated body-
driven CM [71]. (d) Regulated body-driven CM with possible implementation of amplifier A [71]. (e) FGMOS transistors based wide range CM [72]. (f) CMOS implementation
of FGMOS transistors based wide range CM [72]. (g) Schematic of low voltage high performance Ramirez et al. CM along with implementation of its differential amplifier [73].
(h) Schematic of high performance compact all cascode CM [75–77]. (i) Resistively compensated SBCCM with high output resistance [2]. (j) High-performance self-biased
cascode CM with active resistances [2]. (k) High output resistance low power accurate CM [78].
B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155 149

Fig. 14. (continued)

150 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155
and M2 operate in triode region due to level shifter MOSFETs Mb1
and Mb2 respectively. Here, negative feedback provided by Mb1
and Mb2 along with biasing current sources IB1 and IB2 ensures
equal drain voltages of MOSFETs M1 and M2. This architecture
offers output resistance equivalent to a conventional cascode CM
as M3 is connected in cascode configuration with M2 and is ap-
proximately given as:
βMb
rout ≈ g r03 r0Mb
βMb + β2 m3
This CM has a good symmetry and does not contain any offset
term in the output current as compared to triode region simple
CM (Fig. 9(j)). However, it can be observed from the circuit that:
vY = vGS2 and vX = vDS2 + vGS 3
Hence, voltage at node X is always greater than voltage at node
Y. This leads to slight mismatch in vDS1 and vDS2 which lowers the
accuracy of the CM in comparison to that of a conventional cas-
code CM.
8.3. Regulated body-driven (bulk-driven) CMOS CM [71]
A bulk-driven cascode CM (Fig. 13(d)) has better accuracy than
a bulk-driven simple CM (Fig. 13(c)). However, its accuracy is not
good due to mismatch in vDS1 and vDS2 and its operative current
range is very restricted. The schematic of regulated body-driven
CM that overcomes these disadvantages is shown in Fig. 14(c) [71].
In this circuit, an amplifier A is used with MOSFET M3 to maintain
equal drain voltages of MOSFETs forming primary CM pair (M1 and
M2). Since, M1 and M2 are matched and have equal vSB, vSG and vSD
, the CM has high accuracy. The gate terminals of these MOSFETs
are connected to negative supply voltage (VSS) in order to max-
imize the operating current swing. Negative feedback provided by
the cascode configuration of M3 and amplifier A increases the
output resistance of CM considerably and is given as:
rout ≈ Av gm3 r03 r02
Eq. (22) shows that output resistance of body-driven regulated
CM can be made larger than a conventional cascode CM irre-
spective of triode mode operation of MOSFETs M1 and M2, by al-
lowing larger values of Av. Implementation of feedback amplifier A
is shown in Fig. 14(d). Here, the desired value of biasing current IB,
is achieved with the help of biasing voltage VB. Voltage drops
across input and output terminals of the CM are given as:
IB + iIN
vIN ≈ and vOUT ≈ vIN + vSD, sat 3
β ( VDD − VSS − VT )
Eq. (23) depicts that when iIN ¼ 0, vIN,min is few mV only. This
leads to very low values of input and output compliance voltages.
In the circuit, feedback provided by amplifier A and MOSFET M3
improves accuracy of the CM, but it is not as good as conventional
cascode CM. The variation in output current leads to mismatch in
drain currents of M6 and M7 due to channel length modulation
effect. This mismatch further causes a difference in drain–source
voltage of M1 and M2, reducing the accuracy of CM. Furthermore,
the minimum supply voltage required by this circuit is largely
determined by the gate-driven MOSFETs M3–M7.
8.4. FGMOS transistors based wide range CM [72]
FGMOS transistors based simple CM (Fig. 13(a)) has a lower
compliance voltage at lower currents, but with increase in input
current required compliance voltage also increases, rendering it
unusable at low supply voltage. However, this limitation can be
reduced, by proportionately increasing the value of VB with
increase in input current (iIN). The circuit where iIN is fed back to
produce a voltage proportional to iIN is shown in Fig. 14(e) [72]. In
this circuit, MOSFETs M4 and M5 behave as a CM pair and provide
feedback through resistor R to produce a voltage proportional to iIN
which is applied at biasing gate terminal X. Any change in iIN leads
to a proportionate change in VB, thereby lowering the compliance
voltage at higher values of iIN. Fig. 14(f) shows the CMOS im-
plementation of the circuit, where resistor R is replaced by a diode
connected MOSFET (M6) [72]. In this circuit to ensure proper
(20)
biasing of FGMOS transistors even at low input currents, a biasing
current source (IB) is used to maintain a constant current flow
through M6. Furthermore, MOSFET M7 is used in cascode config-
uration with M2 in order to increase output resistance of the CM
and MOSFETs M8 and M9 are used for proper biasing of the circuit.
(21)
Although FGMOS transistors based CMs have a lower supply vol-
tage requirement, they suffer from the problems of fabrication
complexity, charge trapping and poor bandwidth as discussed in
Section 7.1.
8.5. Low supply voltage high-performance CM with low input and
output voltage requirements [73]
The schematic of high performance CM proposed by Ramirez-
Angulo et al. having low input and output voltage requirements is
shown in Fig. 14(g) [73,74]. MOSFET M3 along with current source
IB and constant voltage source VC forms a negative shunt feedback
loop on input side, which significantly lowers the input resistance.
Very high output resistance is achieved in the circuit by combining
a regulated cascode output stage formed by differential amplifier
Ad and cascoding MOSFET M4. Moreover, amplifier Ad helps the CM
to operate with high degree of accuracy over a wide dynamic
range. Low voltage implementation of differential amplifier Ad is
also shown in Fig. 14(g). In this circuit, a dc-level shifter (M7) is
required only for the technologies in which the threshold voltage
of NMOS is higher than that of PMOS. Input and output resistances
of the circuit are respectively given as:
(22)
rin ≈ 1/gm1gm3 r03; rout ≈ r02 gm4 r04 Avd (24)
Above expression for rout is valid if all the MOSFETs operate in
saturation region and can provide a value in GΩ range. The circuit
has an added advantage that even when output MOSFETs go out of
saturation region and operate in triode mode, the CM remains
functional with a comparatively higher output resistance. How-
ever, this circuit consumes more power as compared to conven-
tional cascode and high-swing cascode CMs.
(23)
8.6. Low voltage high performance compact all cascode CMOS CM
[75–77]
A very high performance compact CM with very low input re-
sistance, very high output resistance, high mirroring accuracy, low
input-output voltage requirements and high bandwidth was re-
ported by Ramirez-Angulo et al. [75]. The conceptual schematic of
the circuit is shown in Fig. 14(h). It uses a double nested shunt
feedback loop at input side to lower input resistance to extremely
low values. This double nested shunt feedback loop is im-
plemented by the amplifier A1 and FVF formed by MOSFETs M1
and M1C and biasing current source IB. Furthermore, the CM uti-
lizes a cascode configuration along with an amplifier A2 connected
in series feedback at output side. The cascode amplifier A2 im-
proves output resistance of the CM by a factor of Av2 and enhances
its current matching accuracy to a large extent as vDS1 ¼vDS2. Input
and output resistances of the circuit are respectively given as:
rin ≈ 1/gm1gm1C r01C Av1rout ≈ Av2 r02 gm2C r02C (25)
 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155 151

Three different techniques have been suggested for im-
plementation of auxiliary amplifiers A1 and A2. In first technique
reported in [75] amplifiers A1 and A2 were implemented by
common source PMOS amplifier with gain approximately equal to
gmr0. However, this implementation required that threshold vol-
tage of PMOS must be greater than that of NMOS, which is not
always possible. In second technique suggested in [76], folded
cascode amplifiers with gain (gmr0)2 were used. This im-
plementation provided significant improvements in input and
output resistances and all the MOSFETs remained in saturation
mode irrespective of the fabrication technology used. Third tech-
nique reported in [77], used cascode amplifiers based on NMOS
transistors to achieve similar input and output resistances as
achieved in [76], with better performance. However, this im-
plementation requires higher supply voltage.
8.7. A very high performance self-biased cascode current mirror [2]
A very high performance self-biased cascode CM shown in
Fig. 14(i) was reported by Maneesha et al. [2]. It combines wide
swing characteristic of self-biased cascode CM (Fig. 9(d)) and
bandwidth enhancement characteristic of resistive compensation
technique (Fig. 12(a)). As discussed in Section 6.1, the proper
choice of compensating resistor R1 cancels the dominant pole
appearing in frequency response by the zero introduced, thereby
improving bandwidth of the circuit. Modified transfer function of
the circuit is given as:
iout (s ) − g m2 g m3
= dominates when M5 operates in saturation mode and positive
iin (s )
(
C2 C3 s2 + s ( gm2 C3 +gm3 C2 +gm1C3
C2 C3 )+ gm3 gm1
C2 C3
From Eq. (26), bandwidth of the circuit is obtained as:
g m1 g m3
ω0 =
C2 C3
Comparison of Eq. (27) with the bandwidth of high-swing
cascode CM (Fig. 9(a)), shows that this technique improves the
bandwidth by a factor of √2.
In this CM, super-cascode configuration implemented at the
output terminal, (suggested in [53]) offers output resistance the-
oretically in GΩ range and is given as:
rout ≈ gm6 r06 gm5 r05 gm3 r03 r02
The circuit has been made compatible with fully monolithic
integrated circuit design, by replacing passive resistors by active
resistors, as shown in Fig. 14(j). In this modified circuit, for opti-
mum bandwidth, channel resistance of M7 (operating in triode
region) needs to track 1/gm1. The desired resistances are achieved
by adjusting the aspect ratios of M7 and M10. This low voltage CM
has wider bandwidth, very high output resistance and good cur-
rent mirroring accuracy. However, it offers higher input resistance
due to presence of resistor (R) or MOS diode (M10) at input side.
8.8. An ultra-high compliance, high output resistance low power
accurate CM [78]
An accurate low power CM with high output resistance sug-
gested by Azhari et al. [78] is shown in Fig. 14(k). This structure
lowers input compliance voltage and input resistance of the CM to
a great extent due to negative shunt feedback provided by FVF
configuration, formed by MOSFETs M1, M3 and current source IB1
and positive series type feedback provided by MOSFETs M1–M4.
This CM offers very high output resistance due to negative series
feedback formed by MOSFETs M4 and M5 in combination with
MOSFETs MA and MAC acting as an amplifier. Moreover, MOSFETs
M1–M4 provide positive shunt feedback at output side, which
further enhances its output resistance. The circuit is designed in
such a way that even if M5 leaves saturation region and enter into
triode region, input current is copied at the output node accu-
rately, as positive feedback compensates the effect by increasing
vG2. This characteristic of the CM helps in reducing the required
compliance voltage at the output node. Here, negative feedback
) (26) feedback dominates when M5 is in triode region.
In this circuit, to achieve positive value of output resistance,
MOSFETs M1 and M2 must operate in triode region and to obtain
positive value of input resistance, gain of the amplifier (formed by
MOSFETs MA and MAC) should be very high. However, the circuit
(27)
becomes unstable under certain conditions due to positive feed-
back loops both at input and output sides.
8.9. Simulation results of high performance CMs discussed in Section
8.1
Eldo Spice simulation results of these high performance CMs
have been discussed here. For simulation of these circuits, para-
(28) meters such as transistor sizes and bias current values have been

Table 7
Comparative results of different high performance CM topologies.

Active input Wide swing Regulated FGMOS High performance High performance Self-biased High output re-
regulated cas- triode region bulk-driven based wide Ramirez et al. CM compact all cascode cascode CM sistance Azhari
code CM cascode CM CM range CM CM et al. CM
Mirroring accuracya Poor Excellent Very good Very good Excellent (with off- Excellent (with off- Very good Very good till
set term) set term) 100 mA

% Error ratio (PER)b 18.46 0.71 10 3.05 0.18 0.0036 3.4 5.48
Vin,dropa (V) 1.5 (for VD 0.05–0.475 0–0.55 0.2–0.525 0.314–0.328 0.53 1–1.7 0.03–0.141
¼ 1.5 V)
Vout,mina (V) 0.5–0.9 0.1–0.5 0.1–0.6 0.1–0.3 0.3–0.5 0.6–0.65 0.2–0.6 0.1–0.12
Input resistanceb (Ω) 400 2k 850 8.5 k 100 10 5k 50
Output resistanceb 30 M 17 M 4M 30 M 700 M 3.5 G 9G 1G
(Ω)
Bandwidthb (Hz) 1.3 G 991.97 M 83.24 M 7.087 M 1.23 G 1.06 G 2.25 G 54 M
Peaking in fre- 8.9 0.34 Nil Nil 10 Nil 7.76 Nil
b
quency response
(dB)
Power consumedb 51.08 m 30.38 m 58.95 m 40.39 m 39.22 m 51.36 m 58.14 m 32.14 m
(W)

a
For input current range 0–500 mA.
b
At input current¼ 10 mA.
152 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155

Fig. 15. Current transfer characteristics for various high performance CMs dis-
cussed in Section 8.

Fig. 20. Frequency response at iIN ¼ 10 mA, of various high performance CMs dis-
cussed in Section 8.

Fig. 16. PER in current mirroring accuracy for various high performance CMs dis-
cussed in Section 8.

Fig. 21. Input referred noise as a function of frequency for various high perfor-
mance CMs discussed in Section 8.

Fig. 17. Input current vs. input voltage characteristics for various high performance
CMs discussed in Section 8.

Fig. 22. Curves showing variation in output current for temperature change from
 25 °C to þ75 °C for various high performance CMs discussed in Section 8.

chosen in accordance to the values given by the authors in their

Fig. 18. Input resistance as a function of frequency at iIN ¼ 10 mA for various high
performance CMs discussed in Section 8.
Fig. 19. Output resistance as a function of frequency at iIN ¼ 10 mA for various high
performance CMs discussed in Section 8.
respective papers and are mentioned in the figures as well.
However, various analyses parameters used for comparison like
current range, input resistance, output resistance, bandwidth etc.
are taken in accordance to the values discussed in Section 2. The
comparative simulation results of these high performance CM
topologies are summarized in Table 7. The current transfer char-
acteristic for these CMs is shown in Fig. 15 and their corresponding
curves showing PER in current mirroring accuracy are shown in
Fig. 16. In Fig. 16, wherever required the percentage error has been
calculated after subtracting the offset term from the output cur-
rent. Input current vs. input voltage curves for these CMs re-
presenting their input compliance voltages are plotted in Fig. 17. It
shows that minimum voltage headroom at input side is consumed
by high output resistance Azhari et al. CM [78]. The variations in
input and output resistances as a function of frequency (at iIN
¼10 mA) are depicted Figs. 18 and 19 respectively and the simu-
lated frequency response curves are shown in Fig. 20. This figure
shows that active input regulated cascode CM [13], high perfor-
mance Ramirez-Angulo et al. CM [73] and self-biased cascode CM
[2] show peaking in frequency response. From pole–zero analysis
carried out in Eldo Spice, it was observed that in these CMs
peaking appeared due to presence of a zero prior to (or very close
to) dominant pole.
 B. Aggarwal et al. / Microelectronics Journal 53 (2016) 134–155
Fig. 23. MC simulation results illustrating PER for worst case in current transfer
characteristic for various high performance CMs discussed in Section 8.
The performance analysis of these circuits reveals that compact
all cascode CM offers minimum error in current transfer char-
acteristics along with minimum input resistance. However, this
configuration introduces an offset term in the output current.
Wide swing triode region cascode CM requires minimum voltage
headroom and consumes least power, while maximum bandwidth
and output resistance is offered by self-biased cascode CM. How-
ever, it shows peaking in frequency response.
Noise and temperature analyses are also important in deciding
the overall efficiency of a CM. The simulations to analyze the effect
of noise at input and output sides of these CMs were carried out
and it was observed that contribution of input and output noise is
maximum in case of regulated bulk-driven CM [71]. This is because
bulk-driven transistors are very sensitive to voltage variations, a
slight deviation in their bulk voltage can increase the substrate
leakage current a lot. The curves showing effect of input referred
noise for these CMs as a function of frequency are plotted in
Fig. 21. The effect of temperature variations for a temperature
sweep of 25 °C to þ75 °C on current transfer characteristics of
high performance CMs has been studied. The variations in output
current (Iout) for  25 °C to þ75 °C, as compared to room tem-
perature (27 °C) was observed and difference of these two values
as a function of input current (Iin) for each high performance CM
has been shown in Fig. 22. From this figure it can be analyzed that
high performance compact all cascode CM [77] and wide swing
triode region cascode CM [41] are least sensitive to temperature
fluctuations while high output resistance Azhari et al. CM [78] and
FGMOS based wide range CM [72] are maximally affected by
temperature variations.
Moreover, simulation results discussed above take into account
the specified values of the device parameters of various circuits. To
include the effect of random offset mismatch in output current of
these CMs, Monte Carlo (MC) analysis has been performed for 5%
mismatch in MOSFET's aspect ratio with uniform distribution. This
analysis illustrated that, with respect to random offset mismatch
occurring due to various process variations, Ramirez et al. CM [73]
and compact all cascode CM [77] are the most robust and triode
region cascode CM [41] is the most sensitive CM configuration. It
can be analyzed that the double nested feedback loops present at
input and output sides of Ramirez et al. CM [73] and compact all
cascode CM [77] provide them the robustness shown by these
configurations. Out of 50 MC runs carried out for each high per-
formance CM, percentage error ratio (PER) has been calculated for
the worst case compared to its expected standard result (shown in
Fig. 15) and plotted in Fig. 23.
It has been observed that as device dimensions are scaled be-
low 65 nm, various physical and quanta mechanica effects like
significant leakage currents, variability of technological para-
meters (like threshold voltage, width, length, doping level etc.),
mobility degradation, carrier velocity saturation, poly-depletion
effects, bias dependent source/drain resistances and capacitances,
vertical and lateral doping etc. are encountered [79–81]. All these
153
factors severely degrade the matching (a must condition) required
in basic CM pair for all the topologies discussed in this paper.
Moreover, square law characteristic considered in voltage–current
equations become inaccurate and the true relationship can be
defined somewhere between linear and square characteristic [80].
In deep-submicron technologies, hot-carriers cause finite drain-to-
substrate impedance and also lead to dc current tunneling through
the gate and instigate static gate leakage component. In MOS de-
vices based on these technologies, off-state subthreshold leakage
current is also quite significant [79]. This makes the classical hy-
brid model inaccurate and new models (like EKV MOSFET model)
with modified voltage–current equations valid for short channel
devices have to be used [81]. Hence, the topologies discussed
above may or may not work properly for these technologies. The
validity of the circuit can be obtained only after using the models
specially defined for these technologies and has to be verified
using SPICE simulations.
9. Conclusions
Various CM topologies suggested in literature have been stu-
died in detail and their simulations carried out by Mentor Graphics
Eldo spice in TSMC 0.18 mm CMOS, BSIM3 and Level 53 technology.
Techniques reported in literature for improving various perfor-
mance characteristics of a CM like accuracy, compliance voltage,
input resistance, output resistance, bandwidth and low voltage
operation have been explored and analyzed. Simulation results
illustrating their comparative performance parameters are shown
and have been tabulated. Moreover, various very high-perfor-
mance CMs reported in literature based on these techniques have
also been explored and summarized in this paper along with their
simulated results. It has been concluded that the most optimal
current mirroring accuracy has been observed with compact all
cascode CM though with offset current component, in addition to
lowest input resistance. Triode region cascode CM consumes
minimum voltage headroom and least power. Maximum band-
width and output resistance are offered by self-biased cascode CM,
though with peaking in frequency response. Furthermore, noise,
temperature and Monte Carlo analyses of these high performance
CMs was carried out and their simulation results are shown.
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