Design and implementation of Baugh-Wooley Signed

Multiplier Using Verilog

MahakGupta NehaTiwari Anamika

Department of Electronics
and Communication
Engineering,
ABES EngineeringCollege,
Ghaziabad –U.P.
mahakgupta4100@gmail.com
hailendra Bishariya
Department ofElectronics
and Communication
Engineering,
ABESEngineering
College,Ghaziabad-U.P.
Department of Electronic and Department of Electronics
Communication Engineering, and Communication
ABES EngineeringCollege, Engineering, ABES
Ghaziabad – U.P. Engineering
nehat6249@gmail.com College,Ghaziabad-
U.PShrivastavanamikasri66
7@gmail.com
Mudit Saxena
Department of Electronics
and Communications ,ABES
Engineering CollegeGhaziabad-U.P.

Abstract—In this research paper,abrief Keywords—Baugh-

review of the design and implementation of WooleyMultiplie,Multiplier,VLSI,
Baugh-Wooley Signed Multiplieri XilinxISE.
spresented. Variouselectronicdevicesbased .INTRODUCTION-:
on VLSI technology have long
The Baugh-Wooley Signed Multiplier is a digital
beenimportantfortestsystems.TheBaugh- circuit designed to performs igned binary
Wooley multiplier design seeks tominimize multiplication efficiently.It is a fundamental
hardware complexity,increasespeed, component in digital signal processing and
decrease size, and use less power.Baugh arithmetic operations. This outlines the designand
Wooley Multiplier uses a ripple implementation of a Baugh- Wooley signed multiplier
carryadditiontechniqueto increase using the Verilog hardware description language.It
efficiencyandreducepower.The represents a compelling solution for efficiently
improvement of Baugh-Wooley and Braun handling the multiplication of signedbinarynumbers.
multiplier sfor signed and unsigned number The implementation of the Baugh-Wooley signed
multiplication is the main goal of this work. multiplierinVerilog hold sparticular significance in
Threedistinct adder logics are used in the contemporary digital circuit design. It aligns with the
design,which affect speed and power increasing demand for optimized arithmetic units in
consumption:Basic CMOS,Domino, and applications such as digitalsignal processing, where
Split Path Data Driven Dynamic efficient multiplicationofsignednumbersis paramount.
Logic(SPD3L).There designed multipliers
address three important system design
constraints: speed, area, and power The exploration aims to shed light on the
needs.They show advantages in both power intricacies of Baugh-Wooley signed multiplier
efficiency and delay reduction designed to and its Manifestation in Verilog.By delving into
expedite arithmetic operations in digital the design considerations ,inherent
signal processing ,thi advantages,and practical applications, this
smultiplie remploysbit-wise parallel lis study seeks to provide acomprehensive
mand partial product reduction to optimize understanding of how this multiplier,coupled
computational speed.By strategically with Verilog,contributes to the advancement of
minimizing the number of partial products digital circuit design methodologies.
and leve ragingbinary arithmetic
cproperties,theBaugh-Wooley multiplie
rstrikes abalance between efficiency and
hardware complexity,making it avaluable
component in applications demanding high-
speed multiplication.
II. LITERATURE REVIEW
K. Sarita Raj, et al., in 2023, designed multiple
control tofoli and multiple control Fredkin using
reversible logic gates. Ongoing efforts in employing
several multiplier types to increase hardware
capacity were however insufficient. MCTs and
MCFgetCstock with fully reversible initialization
minimize hardware complexity, redundancy, and
wasted power.
In Abhinav Rampisa, et al., 2022, Design of Low-
Power 4-Bit Bog-Volumemultiplying 1-Bitmirror
and Approximate Full Adders" Most recent data-
driven innovations, especially machine learning
(ML) and artificial intelligence (AI) and artificial
intelligence (AI) conformance.A nominal
temperature of 30°Candonoperatingvoltageof0.7v, a
16-nmCMOS process using a primary 4-bit BW
multiplier is suggested.
37.5 MW, while it uses 35.5 micro
wforacombinedMFA andAFA circuit.[2]
Vamshi Ponugoti et al., 2022 presented the design of
a Baugh-Wooley multiplier using the full swing
GDIT technique. This study uses fullswing gated
fusion input (GDI) technology using a four-bit
Baugh-Wooley multiplier for matic operations
commonly used in accumulators, microprocessors,
digital signal processing, and many other
applications. Thus, the overall system performance
is determined by the full performance of the header.
Saha and Dandpat. In 2021, "Modified Baugh
Woolley Multiplying Lowpower Compressors" is a
16-bit modified Baugh Woolley multiplier that uses
a slow-power compressor, full ladders, and a
modified ripple carry adder while achieving lower
power consumption, lower latency, and minimal
transistor count compared to conventional circuits.
ITSimulatedinCadenceVirtuosousingGPDK45nmtec
hnology.[4]
Gudiwada and Florence Sudha, "Design of a Baug-
WoolMultiplierQuantum-DotCellular
AutomatausingNovel1-BitFullLadder" in 2020.
with energy loss analysis"
This work explores the use of Quantum-
dotAutomata (QCA) for nanoscale applications
in CMOS addressing.
EmmanuelPrince Gomes, et al., In 2019,
"BaughWooley Multiplier using Carry Save
Addition for EnhancedPDP" This research
presents new methods for implementing five
depth modified BWMin digital signals. carrier
structure in abasiccarry-saveimplementation.
the ripple summing technique applied to the
basic modified BWM results in improved
performance, latency and PDP performance.[6]
Dr. P. Karuppusamy. In 2019, "Design and
Analysis of a Low-Power, High-Speed
BaughWooley Multiplier" The study analyzes
the performance of several multipliers and
develops a high-speed, low-power multiplier
based on the Baugh Wooley algorithm.
Strategies Used, Multiplier Consumption and
Properties, Properties, Properties, Applications
It is decided that a multiplier with lower latency
and power consumption must be used. By
examining the performance of the Baugh
Wooley multiplier and other existing
multipliers, research has shown that the Baugh
Wooley multiplier's performance, latency
intervals, and current consumption are
compelling when compared to others.[7]
 III. METHODOLOGY
K. Saritha Raj, et al., In 2023, Using Multiple
Control Toffoli and Multiple Control Fredkin
Reversible Logic Gates" In the current effort to
increase hardware capacity, several types of
multipliers have been used, but the results have
been insufficient. MCT-MCF) with an
originally reversible full adder using
MCT&MCF gates aims to minimize hardware
complexity, increase speed, reduce size and
waste energy.
Abhinav Rampeesa, et al., In 2022, A Baugh-Wooley
multiplier using 1-bit mirror and approximate
fulladders” by Abhinav Rampeesa, Mohammed Irfan,
and J. Ajayan. The primary focus of this design and
analysis work is a high performance, low power, 4-bit
Baugh-Wooley multiplier that is dependent. One focus
on various technology nodes from 16nm to 90nm,
especially machine learning (ML) and artificial
intelligence with significant relevance to artificial
intelligence (AI). .
Vamshi Ponugoti et al., In 2022 Using Full Swing
GDI Technique" features Vamshi Ponugoti,
SeetaramOruganti, and SahithiPoloja. This study
presents a four-bit Baugh-Woole multiplier using the
highly desired addition of full Swing Gate Diffusion
Input (GDI) technology, which is made necessary by
GDI technology Arithmetic operations are often used
in accumulators, microprocessors, digital signal
processing and several other applications.
Saha and Dandapat. In 2021, Manolina Saha and
Anup Dandapat presented a Modified Baugh Wooley
Multiplier Using Low-Power Compressors" by
Manolina Saha and Anup Dandapat. The paper
proposes a 16-bit modified BaughWooley Multiplier
that uses low-power compressors, full ladders, and a
modified Ripple obaCarryAdder. and negative
numbers in various digital systems by exhibiting
lower power consumption, lower latency and
.
minimized number of transistors compared to
conventional circuits. It is simulated in
CadenceVirtuosousingGPDK45nm technology.
GudivadaandFlorenceSudhain2020,Multiplication
in quantum dot cellular automata using a 1-bit
ladder with energy dispersive analysis”This thesis
explores the use of quantum dots (QCA) for
nanoscale applications in CMOS addressing. 2 feet.
Emmanuel Prince Gomes, et al., in 2019, “Baugh
Wooley Multiplier using Carry Save Addition for
Enhanced PDP” This research presents new
methods for implementing five-depth BWMin digital
signal processing. The proposed methodology shows
increased efficiency, which is confirmed by the
ripple addition technique. Compared to the
corrugation technique, the supporting structure is in
the basic implementation of nose preservation.
Dr. P. Karuppusamy. In 2019, "Design and
Analysis of a Low-Power, High-Speed Baugh
Wooley Multiplier" The study analyzes the
performance of several multipliers and develops a
high-speed, low-power multiplier based on the
Baugh Wooley algorithm. Multiplier properties,
including area, power consumption, and latency, are
determined by the multiplication strategies used. It is
decided that a multiplier with lower latency and
power consumption must be used. By checking the
performance of the BaughWoole multiplier and
other existing multipliers, the research demonstrated
that the performance, transient latency and power
consumption were found to be convincing compared
to other current approaches.
RESULT and Analysis

In this section we present the results of our study on Baugh-Wooley multiplier is a technique used in digital signal
processing and VLSI design for efficient multiplication of signed binary numbers. His

*Efficiency*: The Baugh-Wooley multiplier offers improved efficiency in terms of speed and area utilization
compared to traditional multiplication techniques such as array multipliers or Booth coding.

*Resource Utilization*: It requires less hardware resources compared to conventional multipliers, making it suitable
for VLSI implementations where area is a concern.

*Performance*: Baugh-Wooley multiplication results in a reduction in propagation delay, allowing faster

computation of multiplication operations.

*Algorithm Complexity*: The Baugh-Wooley multiplication algorithm simplifies the multiplication process by
exploiting the properties of two's complement arithmetic, resulting in reduced hardware complexity.

*Partial Product Reduction*: The algorithm effectively reduces the number of partial products generated during
multiplication, leading to a more efficient implementation.

*Carry Propagation*: The Baugh-Wooley multiplier efficiently handles carry bit propagation and reduces critical
path delay in the multiplying circuit.

*Overhead*: While Baugh-Wooley multiplication offers advantages in terms of speed and area, it can introduce
additional overhead in terms of control logic and routing complexity, especially for large VLSI designs.

*Power Consumption*: The reduced hardware complexity of the Baugh-Wooley multiplier can result in lower power
consumption compared to conventional multiplication techniques, making it suitable for power-sensitive
applications.

*Trade-offs*: When selecting multiplication techniques for VLSI designs, designers must carefully consider trade-
offs between speed, area, and power consumption, as the Baugh-Wooley multiplier may not always be the optimal
choice depending on specific design constraints.
PARAMETERS:-

The result in this table form from the reference paper are as table no1.

Reference Voltage(v) Current(mA) Power(W) Power Delay(ns) Freq.(Hz) Temp.(c)

cons.(W)

[1] 0.76 0.45 729.33 178.34

[2] 0.7 37.5 30

[3] 1.8v&1.2 74.3 250

[4] 4&2 5&2 0.54 100

[5] 2.44

[6] 48.76 2.73

[7] .377 4.56

[8] 4.68 10.54

[9]

[10] 0.6 0.172 7.913 25

Table1: Comparison with different existing systems The comparison table illustrates the superior performance of our
advanced multiplier compared to existing solutions. Our multiplier achieves high accuracy response, low power
consumption .
Discussion
The Baugh-Wooley multiplier is a widely used
technique for implementing fast and efficient
multiplication operations in very large scale
integration (VLSI). It is particularly beneficial in
digital signal processing (DSP) applications, where
multiplication is a fundamental operation.
The Baugh-Wooley algorithm reduces the number of
partial products that need to be generated and
computed, thereby saving computational resources
and improving efficiency. It achieves this by using the
properties of two's complement arithmetic and
breaking the multiplication process into smaller, more
manageable steps.
Instead of directly multiplying two binary numbers,
the Baugh-Wooley algorithm first performs a
modified multiplication, which involves negating
certain bits of the operands. This modified
multiplication results in a reduced number of partial
products, which can then be efficiently generated and
added together.
One of the main advantages of the BAUGH-
WOOLEY multiplier in VLSI implementations is its
ability to reduce hardware complexity while
maintaining high efficiency. By reducing the number
of partial products and optimizing the critical path,
Baugh-Wooley multipliers can achieve faster
multiplication speeds with fewer resources than other
multipliers.
From a VLSI perspective, this translates to tangible
benefits. By reducing the number of partial products,
the Baugh-Wooley multiplier minimizes hardware
complexity and length of the critical path. This not
only saves silicon real estate, but also improves
performance by streamlining the fabrication process.
In addition, the Baugh-Wooley multiplier is perfectly
compatible with parallel architectures commonly
found in modern VLSI designs. This makes it an
attractive choice for high-performance DSP
applications that can take advantage of parallel
processing capabilities to further increase throughput.
In essence, the Baugh-Wooley multiplier is like a
master conductor managing a symphony of bits,
optimizing the multiplication process to ensure
efficiency, speed and scalability in VLSI designs. A
testament to the power of intelligent algorithms in
shaping the landscape of digital arithmetic processing.
Overall, the Baugh-Wooley multiplier is a powerful
technique in VLSI design that offers a balance
between performance, efficiency, and hardware
complexity, and is a popular choice for a variety of
digital signal processing and arithmetic-intensive
applications.
 CONCLUSION
In conclusion, the design of the Baugh Wooley Multiplier increases the complexity of the device, reduces its size,
and uses less power. By using the Baugh Wooley Multiplier, the methodology improves efficiency, which is
confirmed in the second paper using the fiber-addition method. The main purpose of this work is to build and
investigate a high-performance, low-power, reliable 4-bit Baugh Wooley Multiplier. Our proposed solution aims to
create a Baugh-Wooley Signed Multiplier using Verilog, and we have succeeded in several important ways. We have
understood and implemented the Baugh-Wooley algorithm, which uses Booth coding and minimizes partial products
to efficiently multiply signed numbers.
Throughout the project, we break down the design into smaller, manageable components using Verilog. Rigorous
tests and simulations have been conducted to ensure the accuracy of our multiplier in various scenarios.
When faced with challenges such as the complexity of Booth's coding and optimizing the use of resources, we
successfully overcome these challenges to produce functional multipliers. The Baugh-Wooley Signed Multiplier
shows improved performance,

especially if the operand condition contains many zeros.

Looking ahead, potential improvements include implementing a pipelined architecture for faster throughput,
exploring power optimization techniques, and scaling designs for larger operations.
In summary, our project provides valuable insight into the complexity of signature multiplication and demonstrates
the effectiveness of the Baugh-Wooley algorithm. Future work can build on this foundation for further optimization
and wider applicability.
A Baugh-Wooley Signed Multiplier is a digital circuit used for signed binary multiplication in digital signal
processing and arithmetic operations. The implementation of this multiplier in Verilog is essential for modern digital
circuit design, especially in applications that require optimal arithmetic units. Various studies have explored the
design and methods of improving the performance and efficiency of the Baugh-Wooley multiplier, including the use
of inverse logic gates, adding savings, low-power compressors, and quantum dot cellular automata. These studies
show improvements in energy consumption, latency, footprint, and overall system performance.

The results have practical implications for VLSI designers, providing guidance on how to balance trade-offs between
these important parameters. By understanding the nuances of multiplier design presented in their research,
practitioners can make informed decisions to optimize the performance of VLSI circuits, from embedded systems to
high performance computing.

In addition, Baugh-Wolley multiplier research is used as a basis for further research and innovation in VLSI design.
This not only deepens our understanding of reproductive architecture, but also inspires new approaches

methodologies for enhancing overall circuit efficiency and performance.

Moving forward, based on the insights provided by Baugh and Wolley, it is necessary to explore new avenues for
multiplier optimization and push the boundaries of VLSI design. By leveraging the lessons learned from their
research, we can drive advances in semiconductor technology and unlock new possibilities for next-generation
electronic devices and systems.
References.

i. K. Saritha Raj, P. Rajesh Kumar, M. Satyanarayana. "Baugh-Wooley Multiplier design using Multiple
Control Toffoli and Multiple Control Fredkin reversible logic gates”, International Review of Applied
Sciences and Engineering,vol.14, pp 285-292, 2023.
ii. Abhinav Rampeesa, Ponnaboina Akhila, Mohammed Irfan, Shashank Rebelli, Laxman Raju Thoutam , J.
Ajayan. "Design of Low Power 4-Bit Baugh-Wooley Multiplier using 1- Bit Mirror and Approximate Full
Adders", 2nd Asian Conference on Innovation in Technology (ASIANCON), 2022.
iii. Vamshi Ponugoti, Seetaram Oruganti, Sahithi Poloju, Srikanth Bopidi. "Chapter 71 Design of Baugh-
Wooley Multiplier Using Full Swing GDI Technique”, Springer Science and Business Media LLC, 2022.
iv. Manolina Saha, Anup Dandapat. "Modified Baugh Wooley Multiplier using Low Power Compressors", 2nd
International Conference for Emerging Technology (INCET), 2021.
v. A. Arunkumar Gudivada, Gnanou Florence Sudha. "Design of Baugh–Wooley multiplier in quantum-dot
cellular automata using a novel 1-bit full adder with power dissipation analysis", SN Applied Sciences,
vol.2, article no. 813, 2020.
vi. Emmanuel Prince Gomes, Ankita Saha, Mandhavika Agarwal, and V S Kanchana Bhaaskaran. “Baugh
Wooley Multiplier Using Carry Save Addition for Enhanced PDP”, Proceedings of International
Conference on Sustainable Computing in Science, Technology and Management (SUSCOM), Amity
University Rajasthan, Jaipur - India, February 26-28, 2019.
vii. Dr. P. Karuppusamy, “Design and Analysis of Low-Power, High-Speed Baugh Wooley Multiplier” Journal
of Electronics and Informatics Vol.01/ No. 02 Pages: 60-70, 2019.
viii. Vinay B. Biradar, P. G. Vishwas, C. S. Chetan, B. S. Premananda. "Design and performance analysis of
modified unsigned braun and signed Baugh-Wooley multiplier”, International Conference on Electrical,
Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT), 2017.
ix. Shaik. Noorjahar Begum and M. Rambabu, “Design and Implementation of 16-Bit Baugh-Wooley
Multiplier with GDI Technology” International Journal of Advanced Scientific Technologies in Engineering
and Management Sciences (IJASTEMS-ISSN: 2454-356X) Volume.2, Issue4, April.2016.
x. Mansi Jhamb, Garima, and Himanshu Lohani, “Design, implementation, and performance comparison of
multiplier topologies in power-delay space” Engineering Science and Technology, an International Journal
Volume 19, Issue 1, March 2016, Pages 355-363.

xi. Shruti D. Kale, Prof. Gauri N. Zade, “Design of Baugh-Wooley Multiplier using Verilog
HDL”IOSR Journal of Engineering (IOSRJEN) ISSN (e): 2250-3021, ISSN (p): 2278-8719 Vol. 05,
Issue 10 (October. 2015), ||V2|| PP 25-29.

xii. Anitha R, Bagyaveereswaran V, “Low Power Baugh Wooley Multipliers with Bypassing Logic” IEEE -
International Conference on Research and Development Prospects on Engineering and Technology
(ICRDPET 2013) March 29,30 - 2013 Vol 3.