Applied Energy 138 (2015) 414–422

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Applied Energy
journal homepage: www.elsevier.com/locate/apenergy

Energy efficient hotspot-targeted embedded liquid cooling of electronics

Chander Shekhar Sharma a, Manish K. Tiwari a,1, Severin Zimmermann a, Thomas Brunschwiler b,
Gerd Schlottig b, Bruno Michel b, Dimos Poulikakos a,⇑
a
Department of Mechanical and Process Engineering, ETH Zurich, 8092 Zurich, Switzerland
b
Advanced Micro Integration, IBM Research–Zurich, 8803 Rüeschlikon, Switzerland

h i g h l i g h t s

 We present a novel concept for hotspot-targeted, energy efficient ELC for electronic chips.
 Microchannel throttling zones distribute flow optimally without any external control.
 Design is optimized for highly non-uniform multicore chip heat flux maps.
 Optimized design minimizes chip temperature non-uniformity.
 This is achieved with pumping power consumption less than 1% of total chip power.

a r t i c l e i n f o a b s t r a c t

Article history: Large data centers today already account for nearly 1.31% of total electricity consumption with cooling
Received 5 June 2014 responsible for roughly 33% of that energy consumption. This energy intensive cooling problem is exac-
Received in revised form 20 September erbated by the presence of hotspots in multicore microprocessors due to excess coolant flow requirement
2014
for thermal management. Here we present a novel liquid-cooling concept, for targeted, energy efficient
Accepted 24 October 2014
cooling of hotspots through passively optimized microchannel structures etched into the backside of a
chip (embedded liquid cooling or ELC architecture). We adopt an experimentally validated and compu-
tationally efficient modeling approach to predict the performance of our hotspot-targeted ELC design.
Keywords:
Hotspot-targeted cooling
The design is optimized for exemplar non-uniform chip power maps using Response Surface Methodol-
Microchannel cooling ogy (RSM). For industrially acceptable limits of approximately 0.4 bar (40 kPa) on pressure drop and one
Electronics cooling percent of total chip power on pumping power, the optimized designs are computationally evaluated
Hotspots against a base, standard ELC design with uniform channel widths and uniform flow distribution. For an
Energy efficient computing average steady-state heat flux of 150 W/cm2 in core areas (hotspots) and 20 W/cm2 over remaining chip
Multicore microprocessors area (background), the optimized design reduces the maximum chip temperature non-uniformity by 61%
to 3.7 °C. For a higher average, steady-state hotspot heat flux of 300 W/cm2, the maximum temperature
non-uniformity is reduced by 54% to 8.7 °C. It is shown that the base design requires a prohibitively high
level of pumping power (about 2000 fold for 150 W/cm2 case and 600 fold for 300 W/cm2 case) to match
the thermal performance of the optimized, hotspot-targeting designs. The pumping power requirement
for optimized designs is only 0.23% and 0.17% of the total chip power for 150 W/cm2 and 300 W/cm2
hotspot heat flux respectively. Moreover, the optimized designs distribute the coolant flow without
any external flow control devices and the performance is only marginally affected by the manifold
geometry used to supply the coolant to the microchannel heat transfer structure. This also attests to
the robustness of the optimized embedded microchannel structures.
Ó 2014 Elsevier Ltd. All rights reserved.

1. Introduction

Since the advent of first very large scale integrated circuits,

⇑ Corresponding author. Tel.: +41 44 632 27 38; fax: +41 44 632 11 76.
electronic chip manufacturers have endeavored to keep up with
Moore’s law [1]. Chip performance has improved due to increasing
E-mail address: dpoulikakos@ethz.ch (D. Poulikakos).
1
Present address: Department of Mechanical Engineering, University College gate density as well as fabrication of multiple cores on a single
London (UCL), Torrington Place, London WC1E 7JE, UK. chip. However, the inability to follow the Dennard scaling for

http://dx.doi.org/10.1016/j.apenergy.2014.10.068
0306-2619/Ó 2014 Elsevier Ltd. All rights reserved.
 C.S. Sharma et al. / Applied Energy 138 (2015) 414–422
Nomenclature
Afs interfacial area density ð2=ðwc þ ww ÞÞ
hf specific enthalpy of fluid (J/kg)
hc microchannel height (m)
K permeability (m2)
lth length of throttling zone (m)
n,m integral multipliers
m_ mass flow rate (kg/s)

mi relative mass flow rate
P pressure (Pa)
q00 heat flux (W/m2)
R flow resistance (Pa s/kg)
Rthermal thermal resistance (°C m2/W)
T temperature (K)
Ts,max maximum temperature of chip (at base of silicon die)
DTs,max chip wide temperature difference ð¼ T s;max  T s;min Þ
U, Us true and Superficial velocity vectors for porous domain
(m/s)
V_ volumetric flow rate (m3/s)
wc, ww microchannel and wall widths (m)
W, L overall chip dimensions (m)
Wm half width of inlet manifold
supply voltage has lead to high chip heat flux dissipation densities,
especially during the last decade [2]. As a consequence, electronic
reliability considerations are driving a shift away from air-cooling
[3] towards a number of alternative approaches including liquid
cooling [4,5], two-phase cooling [6,7], phase change materials
(PCM) [8,9] and nanofluids [10,11]. Single-phase liquid cooling
has long been identified as an effective and feasible approach for
cooling high heat flux density chips. Starting with the landmark
work of Tuckerman and Pease [12], liquid cooling of chips has been
analyzed in great detail. This includes investigations on traditional
microchannel heat sinks [13], manifold microchannel (MMC) heat
sinks [5,14], spray and jet cooling [15].
Most of the research on liquid cooling of chips has focused on
maximum temperature (Ts,max) reduction under uniform heat flux
dissipation conditions. However, it is also necessary that the chip
temperature is spatially as uniform as possible (i.e. approaching
the isothermal chip condition). Large temperature gradients in
the package increase thermal stresses in the chip to substrate or
heat sink interface, reduce electronic reliability in regions of high
temperature and create circuit imbalances in CMOS devices [4]. A
few studies have focused on reducing chip temperature non-
uniformity (DTs,max) under a uniform chip heat flux map. These
include use of flow boiling of dielectric liquid [16], single phase
liquid cooling with variable pin fin density [17], variable
microchannel width in the streamwise direction [18–20] and
double-layer microchannel structure [21].
During the last decade, computer architecture has witnessed a
trend towards multicore microprocessors due to limitations
encountered in further increasing the single-core clock frequencies
[22]. In a multicore microprocessor, each core houses the execution
units [23]. In modern high performance chips, the cores can
dissipate on an average up to 150 W/cm2 while the rest of the chip
dissipates as low as 20 W/cm2. Since the cores dissipate multiple
times higher heat flux than the rest of the chip, we refer to the
cores as the hotspots. The large difference in heat dissipation
between hotspot and background regions makes the goal of
isothermal junction temperatures even more challenging.
Several approaches have been proposed in the past aimed at
achieving an isothermal chip condition by preferential cooling of
415
_ pumping pumping power (W)
W
_ chip
W total power dissipated by the chip (W)
Greek letters
afs interfacial heat transfer coefficient (W/m2 K)
um fraction of total coolant flow flowing through HSBG
zone
c volume porosity ðwc =ðwc þ ww ÞÞ
k thermal conductivity (W/m K)
Subscripts
bg, hs, th background, hotspot and throttling zones
f, s fluid and solid
fp, sp fluid and solid phases of porous medium
intf interface
max maximum
min minimum
opt optimum value
V optimized value at total flow rate V_ T
B base case
T total
hotspots (henceforth referred to as hotspot-targeted cooling).
These include, for example, use of thermoelectric cooling [24]
and electrowetting [25]. However, these approaches are limited
by low device efficiencies, low heat flux pumping capacities and
contact parasitic resistance for the former [24] and relatively low
heat fluxes for the later [25]. Attempts using single phase liquid
cooling have also been reported with varying degree of success
[26–28]. Additionally, conventional backside attached MMC heat
sinks are thermally joined to the chip through a thermal interface
material (TIM) which, combined with the thickness of substrate
and heat sink base, results in heat spreading and high thermal
resistance. For effective hotspot-targeted cooling, the net thermal
resistance and heat spreading can be reduced by circulating the
coolant through microchannels etched into the backside of the chip
(also termed as embedded or direct chip backside microchannel
cooling) [29–32].
It is also critical that any cooling of microprocessors be energy
efficient [33]. This becomes even more relevant for large datacen-
ters employing thousands of multicore microprocessors. Direct
electricity consumption by large data centers had almost tripled
between 2000 and 2010 and reached 1.31% of the total world
electricity consumption by 2010 due to increased demands for
Information Technology (IT) related services. Although the growth
in data center energy consumption slowed down in the period
2005–2010 [34], the still increasing data center energy bill is
quickly becoming a cause of concern [35]. Cooling overhead for
these datacenters contributes roughly 33% of this electricity
consumption. Hence, efficient cooling can significantly reduce the
IT energy bill [35,36].
In this paper, we propose a novel, hotspot-targeted and, at the
same time, highly energy efficient cooling solution for typical mod-
ern day multicore microprocessors. We employ a passive, energy
saving approach to alter the heat sink design by optimizing the
microchannel geometry and flow rate distribution. The hotspot-
targeted cooling design is described in Section 2. Sections 3 and
4 focus on the modeling, validation and optimization methodolo-
gies and the final results for two exemplar chip power maps are
presented in Section 5. Section 6 presents general rules for design
of hotspot-targeted microchannel heat sink. Lastly, Section 7
416 C.S. Sharma et al. / Applied Energy 138 (2015) 414–422
Fig. 1. (a) Schematic of a MMC heat sink with embedded microchannels. Arrows
indicate fluid flow. Microchannels will be modeled as porous medium. (b) Chip
heat flux distribution and one unit cell used for computational modeling and
(c) schematic of the proposed hotspot-targeted embedded microchannel structure
in one unit cell. ‘I/2’ and ‘O/2’ indicate half inlet and outlet slot nozzles respectively.
HSBG (Hotspot and downstream Background) and BG (only Background) zones are
marked.
demonstrates how the hotspot-targeted design distributes the
coolant in the heat sink without the need for any external flow
distribution devices.
2. Hotspot-targeted heat sink concept
Our hotspot-targeted cooling concept utilizes the well known
MMC heat sink architecture [5,14,37,38], consisting of embedded
microchannels and a manifold layer above it as shown in
Fig. 1(a), as the basis for the design. While the multiple inlet and
outlet slot nozzles in the MMC heat sink reduce the overall pres-
sure drop and improve the thermal performance through impinge-
ment jet cooling and reduction in overall thermal boundary layer
thickness [5,39]; embedded microchannels enable efficient target-
ing of hotspots by reducing the overall thermal resistance and heat
spreading.
Fig. 1(b) shows the heat dissipation map of a typical multicore
chip. The red colored cores are the hotspots and the blue region
is the background. Conventional backside attached liquid cooling
solutions for such a chip are highly energy intensive and lead to
overcooling of the background region and undercooling of the
hotspot regions, thus leading to poor chip temperature uniformity.
We propose a novel microchannel structure to achieve efficient
and targeted hotspot cooling, as described in the following.
As shown in Fig. 1(b) (marked by white dashed lines), a repeat-
ing unit cell for the chip heat flux map can be identified. Similarly,
by exploiting flow symmetry, the heat sink can also be considered
to consist of repeating unit cells. Each unit cell is bounded by sym-
metry planes in inlet and outlet slot nozzles. Fig. 1(c) illustrates a
schematic of the corresponding unit cell of the proposed embed-
ded microchannel cooling structure with inlet and outlet slot
nozzles positioned over the hotspots and over the background
region respectively.
The chip area can be divided into two types of streamwise zones
in each unit cell: ‘HSBG’ zones consisting of a hotspot area with a
downstream background area; ‘BG’ zones consisting of only back-
ground area. These zones are also marked in the corresponding
unit cells in Fig. 1(b) and (c). The proposed design consists of
different microchannel structures in the two zones. While the
HSBG zones consist of fine channels over the hotspots and coarse
channels over the background, the BG zones consist of coarse
channels throughout except for flow-throttling zones, with fine
channels and wide channel walls, near the outlet slot nozzle. The
introduction of throttling zones is a key design concept introduced
here in order to passively manipulate the flow rate distribution on
hotspot and background regions. By altering the throttling zone
length, the fraction of the total flow directed to the HSBG zones
can be changed. Finer channels over the hotspots along with a
higher flow rate in the HSBG zones result in higher heat transfer
coefficient over the hotspots as compared to background.
3. Modeling approach
The hotspot-targeted design was optimized using a conjugate
heat transfer model described below.
3.1. Computational domain and boundary conditions
The computational domain included the silicon die and micro-
channels etched into the back of the die in a unit cell (refer
Fig. 2(a)). Microchannels were modeled as fluid saturated porous
medium [40]. Walls were included inside the porous medium to
separate HSBG and BG zones in order to precisely control the
flow rate distribution between these zones during optimization.
Mass-flow distribution mðyÞ
_ and fluid temperature of 20 °C at the
inlet, and pressure outlet boundary condition at the outlet were
imposed. Heat flux distribution q00 (x,y) was imposed at the base.
Free slip was assumed on all porous medium x–z walls to simulate
volumetric averaging in y-direction [40]. All other boundaries were
assumed to be adiabatic walls. The overall dimensions of the unit
cell are shown in Fig. 2(b) and listed in Table 1. These dimensions
were chosen to represent a realistic multicore microprocessor.
This work corresponds to a test chip consisting of seven unit cells
(refer Fig. 2(top)). Note that the conclusions from this work are
easily adaptable to the eight hotspot arrangement shown in
Fig. 1 by scaling up the total flow rate.
 C.S. Sharma et al. / Applied Energy 138 (2015) 414–422 417

where SM, the directional loss term, is given by [5,41]:

SM;x ¼ lf K 1 1=2

x U s;x  c loss K x qf jUs jU s;x
SM;y ¼ lf K 1 1=2
y U s;y  c loss K y qf jUs jU s;y ð3Þ
1
SM;z ¼ l f K z U s;z  closs K z1=2 qf jUs jU s;z
The permeability K was considered as anisotropic with Ky =
Kx/10 to inhibit flow in y direction (i.e. normal to channel walls).
The permeability and the loss coefficient, closs are given by [14,42]
pffiffiffiffiffiffiffiffiffiffiffi!
cw2c wc hc
Kx ¼ Kz ¼ ; closs ¼ 0:55 1  5:5 pffiffiffiffiffiffiffiffiffiffi ð4Þ
12 hc W

3.2.3. Energy
Energy transport inside the porous medium was modeled
through two separate equations for fluid and solid phase thus
allowing for finite temperature difference between the two phases
[40,41].

r  ðqf Us hf Þ ¼ r  ðckf rhf Þ þ afs Afs ðT sp  T fp Þ ð5Þ

ks r  ½ð1  cÞrT sp   afs Afs ðT sp  T fp Þ ¼ 0 ð6Þ
Heat transfer in silicon die and manifold bottom wall is gov-
erned by the Laplace equation ðr2 T s ¼ 0Þ. Conjugate heat transfer
at porous medium-solid interfaces is governed by the following
equations [43]:

 ks ððrTÞs;intf  nÞ ¼ ckf ððrTÞfp;intf  nÞ  ð1  cÞks ððrTÞsp;intf  nÞ ð7Þ

T s ¼ cT fp þ ð1  cÞT fs ð8Þ
In our model, we accounted for the temperature dependence of
intensive water properties such as density (qf), dynamic viscosity
Fig. 2. (a) Computational domain and boundary conditions, and (b) dimensions of (lf) and specific heat (cp,f) [44] while silicon properties were
the unit cell.
assumed constant ðks ¼ 149 W=mKÞ. The discretized governing
equations were solved using Ansys CFXÒ version 13.0. We imposed
1  106 as the normalized residual and 0.1% as the conservation
Table 1
target for our simulations. The computational mesh used and its
Unit cell dimensions.
grid independence test are described in SI, Section 1.
Dimension Description Value
W Chip width 2.32 cm 3.3. Interfacial heat transfer coefficient
L Test chip length 2.7 cm
H Silicon die thickness 525 lm
The 2-equation energy model in Eqs. (5) and (6) requires knowl-
hc Microchannel height 300 lm
hn Slot nozzle height 450 lm
edge of the interfacial heat transfer coefficient afs. These values
wn Slot nozzle width 500 lm were obtained through separate CFD simulations for a single
whs  lhs Chip core (hotspot) size 4181 lm  4197 lm microchannel and were compiled in the form of a look-up table
wd Distance between hotspots 9280 lm according to the following functional relationship (refer SI, Section
2 for details):

afs ¼ afs ðV_ T ; um ; wc ; xÞ ð9Þ

3.2. Governing equations

1=2
The Reynolds number (defined as qf Uðwc hc Þ =lf ) in the micro- 3.4. Validation of the model
channels stays below 350 across most of the parameter range
encountered in this work. Thus, the flow was assumed to be lami- The above-described modeling methodology was validated
nar. The governing equations for flow in porous medium follow against experimental measurements for an MMC heat sink with
[5,40,41]. embedded microchannels. The microchannels were of uniform size
with wc = 35 lm and ww = 25 lm. The chip power map consisted of
3.2.1. Continuity q00hs ¼ 150 W=cm2 and q00bg ¼ 20 W=cm2 . The chip dimensions were
the same as described in Fig. 2(b) and Table 1. The details of exper-
imental measurements are provided in SI, Section 3. Fig. 3 illus-
$  ðqf Us Þ ¼ 0 ð1Þ
trates that the model is able to successfully capture the cooling
performance of the embedded microchannel structure. The model
3.2.2. Momentum is able to capture temperature non-uniformity in the chip with an
accuracy of 0.4 °C over all flow rates. The small discrepancy
between the model and measured results can be attributed to
qf
 
lf  
r U  Us  r  ðrUs þ ðrUs ÞT Þ ¼ SM  rP ð2Þ minor deviations of actual flow distribution in the heat sink from
c2 s c the modeled distribution and multiple sources of background
418 C.S. Sharma et al. / Applied Energy 138 (2015) 414–422

Fig. 3. Comparison of measured and modeled (a) DTs,max as a function of flowrate and (b) chip temperature map (for one unit cell) at 1 l/min.

radiation that may influence IR (Infrared thermography) between upstream and downstream pitches, for the microchannel
measurements. structure in HSBG and BG zone respectively, to ensure uninter-
rupted flow.
The limits for um and V_ T were chosen such that chip tempera-
4. Optimization of microchannel structure
ture stayed below 85 °C at all operating conditions anywhere in
the heat sink ðV_ T;min ¼ 0:2 l=minÞ. Eq. (11) (h) describes the upper
Minimization of DTs,max and Ts,max can be posed as a constrained
limit on pressure drop through HSBG zone and states that DPHSBG
optimization problem. This section describes the problem formula-
cannot exceed the maximum possible pressure drop in the BG
tion and the optimization method used.
zone, which will occur when the throttling zone occupies the
entire length (L/7) of the unit cell. Eq. (11) (i) is a constraint on
4.1. Design objectives, parameters and constraints the overall pressure drop [46] and Eq. (11) (j) is a constraint
imposed to factor in our aim to achieve the cooling at minimal
The microchannel size distribution (channel lengths, widths energy input in the form of pumping power.
and wall widths) and the overall flow rate V_ T need to be optimized
in order to minimize Ts,max and DTs,max. The constrained optimiza-
tion problem can be formulated as: 4.2. Optimization methodology

Minimize T s;max and DT s;max ð10Þ Response surface method (RSM), a robust technique to reduce
the computational cost for optimization [47–50], was used to
such that achieve the optimal design. The overall optimization was per-
30 6 wc;hs ; wc;bg ; wc;th 6 300 ðaÞ formed in two steps. In the first step, optimal microchannel
structure (wc,hs,opt, wc,bg,opt), flow rate distribution (um,opt) and
ww;hs ; ww;bg ; ww;th P 30 ðbÞ
total flow rate ðV_ T;opt Þ were determined assuming no throttling
ðwc þ ww Þbg ¼ nðwc þ ww Þhs ðcÞ zone (i.e. lth = 0) and using RSM (refer SI, Section 4 for details). In
ðwc þ ww Þth ¼ mðwc þ ww Þbg ðdÞ the second step, the throttling zone configuration was determined
lth 6 L=7 ðeÞ as described below.
0:46 6 um 6 0:9 ðfÞ
V_ T P V_ T;min ðgÞ
DPHSBG 6 DPBG;max ðhÞ
where DPBG;max ¼ DPBG jlth ¼ L=7; wc;th ¼ 30; ww;th ¼ 300
DP 6 0:35 bar ðiÞ
W_ pumping ¼ DPV_ T 6 0:01W
_ chip ðjÞ
ð11Þ
In above equations the constraints for channel widths wc and
wall widths ww are in lm. Eqs. (11)(a)–(e) describe the geometrical
constraints and Eqs. (11)(f)–(j) describe the operational constraints
on the design. The height of the microchannels hc was fixed at
300 lm. In Eqs. (11) (a) and (b), the lower limits of channel and
fin widths were fixed based on aspect ratio limit of 10, which
comes from the process guidelines for deep reactive ion etching Fig. 4. Resistance analogy for flow division (a) without throttling zone and (b) with
of silicon [45]. Eqs. (11) (c) and (d) specify an integral relationship throttling zone.
 C.S. Sharma et al. / Applied Energy 138 (2015) 414–422 419

4.2.1. Throttling zone configuration

The optimized microchannel structure has fine channels over
hotspots in the HSBG zones and coarse channels in the BG zones
ðwc;hs;opt < wc;bg;opt Þ resulting in a higher resistance to coolant flow
in the HSBG zones as compared to the BG zones. As a result, the
flow rate distribution would deviate from the optimized distribu-
tion um,opt as most the fluid would flow through the coarse chan-
nels in BG. The flow division between HSBG and BG zones is
explained through electrical resistance analogy for the flow
network in Fig. 4. Flow resistances corresponding to optimized
microchannel structure in the HSBG and BG zones are represented
by RHSBG,opt and RBG,opt respectively. Fig. 4(a) illustrates the case of
no throttling zone discussed above. Since the pressure drop has
to be equal in the two branches corresponding to HSBG and BG
zone, RBG,opt < RHSBG,opt leads to m _ BG (i.e. um < um,opt).
_ HSBG < m
In order to realize the desired flow rate distribution, the flow
resistance in the BG zone has to be increased, such that pressure
drop on the two branches is equalized (i.e. DPBG = DPHSBG) under
the condition um = um,opt. This was achieved by introducing an
additional flow resistance Rth in the form of a flow throttling zone
(refer Fig. 1(c)) in the BG branch (i.e. RBG = RBG,opt + Rth > RHSBG,opt) as
shown in Fig. 4(b). This somewhat counterintuitive but important
introduction of a throttling zone is key to the success of our
approach. However, the fine channels in throttling zone can cause
undesirable overcooling in the BG zone. This effect can be limited
by (i) placing the throttling zones towards outlet slot nozzles and
(ii) minimizing their length lth. For this purpose, wc,th was fixed at
the lower limit of 30 lm and a high value for ww,th was selected
such that the constraint (11) (d) was satisfied. With all other
parameters fixed, Rth became a function of the length of the
throttling zone lth which was then determined through iterative
microchannel simulations, such that

DPBG ¼ DPHSBG ð¼ DPÞ with um ¼ um;opt ; V_ T ¼ V_ T;opt ð12Þ

5. Results and discussion
The hotspot-targeted cooling concept was first evaluated using
a strongly non-uniform, exemplar heat flux map with q00hs ¼
150 W=cm2 and q00bg ¼ 20 W=cm2 (i.e. a hotspot to back ground heat
_ chip ¼ 285 W). Optimization was
flux ratio of q00 =q00 ¼ 7:5 and W
hs bg
performed using both RSM and detailed microchannel simulations
(refer SI, Section 5 for details). The resulting optimal parameters
and design performance are enumerated in Table 2. A minimum
DTs,max of 3.7 °C and a minimum Ts,max of 29.2 °C was achieved.
5.1. Performance evaluation of the optimized design
The optimized design needs to be compared against a suitable
base case configuration to evaluate the performance. The base case
was selected to represent the limit of cooling with a uniform
microchannel structure and uniform flow distribution. It consists
of embedded microchannels with lowest allowable channel width
for best possible thermal performance and lowest allowable
wall width to minimize pressure drop for such channels (i.e.
Fig. 5. (a) Comparison of the optimized and base design performance for
q00hs ¼ 150 W=cm2 and q00bg ¼ 20 W=cm2 . First three legends indicate the flow model
used for simulating the base design. (b) x-direction velocity profiles (at micro-
channel mid-height) and temperature distribution in the base design (at point B in
(a)) and optimized design.
wc,B = ww,B = 30 lm). All other geometrical dimensions were the
same as those for the optimized design (refer Table 1).
Microchannel simulations were used to evaluate the base case
design at various flow rates. As V_ T increased, the microchannel
Reynolds number increased beyond 2800, the flow became pro-
gressively unstable and turbulence modeling was needed to model
the unstable flow. Two turbulence models, k-omega and Shear
Stress Transport (SST), were used for an estimate of the base case
performance at high flow rates [41]. Fig. 5(a) compares the
thermo-hydraulic performance of the optimized design against
base design in terms of W_ pumping vs. DTs,max. Two points on the base
design performance curve are highlighted: (A) indicates the need
for more than 1300 W of W_ pumping required by the base design to
match the thermal performance of the optimal design. This is
about 2000 times higher as compared to the optimized design
and renders the base design infeasible. Point (B) indicates that

Table 2
Optimum design parameters and performance for q_ 00hs ¼ 150 W=cm2 and q_ 00bg ¼ 20 W=cm2 .

V_ T um wc,hs wc,bg ww;hs ww,th lth DTs,max Ts,max DP _

W pumping
(%)
_
ww;bg W chip

wc;th
(l/min) (lm) (lm) (lm) (lm) (lm) (°C) (°C) (bar)

1.2 0.705 36 300 30 300 927 3.7 29.2 0.33 0.23

420 C.S. Sharma et al. / Applied Energy 138 (2015) 414–422

DTs,max for the optimized design is 61% lower than the base design
for the same W _ pumping . Fig. 5(b) compares the flow fields and the
resulting temperature distribution in the base and optimized
designs. The hotspot-targeted flow distribution in the optimized
non-uniform microchannel structure design concentrates the heat
transfer capacity on the hotspots and leads to the highly uniform
temperature distribution in the chip as compared to base design
at point (B).

5.2. Extension of design concept to higher heat fluxes

The hotspot-targeted embedded microchannel cooling concept

can also be extended to higher levels of q00hs and q00hs =q00bg . We demon-
strate the results for another heat flux map consisting of
q00hs ¼ 300 W=cm2 and q00bg ¼ 20 W=cm2 (i.e. q00hs =q00bg ¼ 15) in Table 3
and Fig. 6. The optimal design achieves an improvement of 54% in
DTs,max while consuming about 600 times lower W _ pumping as
compared to the base design.
The hotspot-targeted designs from Tables 2 and 3 are also
compared against recent literature heat sinks, designed to reduce
DTs,max (see Table 4 and Fig. 7). The optimized designs have the
lowest thermal resistance (Rthermal) values and their pumping
power fractions are comparable to the literature designs. Since
literature results for DTs,max have been reported for various levels
of chip heat flux non-uniformity, we normalize DTs,max as depicted
below for a consistent comparison of various designs.

DT s;max
DT q ¼  00  ð13Þ
qhs
q00bg

Eq. (13) implies that a design is better if it achieves lower temper-

ature non-uniformity DTs,max for higher levels of power map non-
uniformity q00hs =q00bg (i.e. DTq is lower if DTs,max is low for high q00hs =q00bg
ratio). The optimized designs achieve DTq values of 0.49 and 0.58
(nearly an order of magnitude lower than the nearest value of 4.5) Fig. 6. (a) Comparison of optimized design performance against base design for
q00hs ¼ 300 W=cm2 and q00bg ¼ 20 W=cm2 . (b) x-direction velocity profiles and tem-
and hence compare favorably against the literature designs.
perature distribution in base design (B) and optimized design.

5.3. Complete heat sink performance
The manifold layer design was considered next, to optimally
supply and drain coolant from the microchannels. Conjugate heat
transfer simulations were performed for the domain consisting of
a full heat sink unit cell. Details for the full heat sink model are
described in SI, Section 6. Fig. 8 shows simulation results for the

relative coolant mass-fraction distribution ðmi Þ in the microchannel
heat transfer structure, for q00hs ¼ 150 W=cm2 and q00bg ¼ 20 W=cm2 ,
with a conventional straight manifold profile.

mi was obtained by calculating the normalized mass flux
through the middle y–z plane of the microchannel layer [14],
equally divided into N = 50 sections, as:
qf jUs  nji dA
R
 A
mi ¼ 1 P i R
N N Ai qf jUs  nji dA
where Ai ¼ ðW  4ww Þhc =N.
It is evident that a higher proportion of coolant flows
through HSBG zone. um, calculated on the basis of this mass flow
distribution, is nearly 0.7, the optimum value according to Table 2.
Hence, the optimized microchannel structure was able to realize
the required coolant distribution without the need of any external
flow distribution devices.
Further, simulations were performed for a straight manifold
(i.e. constant cross-section) and a number of tapered manifold
profiles with converging inlet and diverging outlet manifold
for the optimized design corresponding to q00hs ¼ 150 W=cm2 and
q00bg ¼ 20 W=cm2 (refer Table 2). It was observed that, unlike in
the case of conventional MMC heat sinks [14], the mass flow
distribution was not sensitive to the shape of the inlet and outlet
manifolds. Fig. 9 shows some of the converging inlet manifold pro-
files investigated in this work. For each design, outlet manifold
shape is complementary, that is the sum of the widths of inlet
and outlet manifolds is constant for all the manifold profiles. As
ð14Þ evident, changing the manifold shape has insignificant effect on
fraction of flow flowing through HSBG zones, um. This is a very
significant result, as it points to the robustness of the optimized
microchannel structure, which is adequate for efficiently achieving
the required and targeted distribution of the flow.

Table 3
Optimum design parameters and performance for q_ 00hs ¼ 300 W=cm2 and q_ 00bg ¼ 20 W=cm2 .

V_ T um wc,hs wc,bg ww;hs ww,th lth DTs,max Ts,max DP _

W pumping
_
ww;bg W chip

wc;th (%)
(l/min) (lm) (lm) (lm) (lm) (lm) (°C) (°C) (bar)

1.6 0.92 52.5 300 30 630 1480 8.7 38.8 0.3 0.17
 C.S. Sharma et al. / Applied Energy 138 (2015) 414–422
Table 4
Comparison of optimized designs against literature heat sinks.
a
Approximate values/values back calculated from available information.
Fig. 7. Comparison of optimized designs (red colored text and symbols) against
heat sinks from literature. The numbers in square brackets refer to literature
references. (For interpretation of the references to colour in this figure legend, the
reader is referred to the web version of this article.)
Fig. 8. Relative mass flux distribution for straight manifold profile
q00hs ¼ 150 W=cm2 and q00bg ¼ 20 W=cm2 .
6. Design rules for hotspot-targeted microchannel cooling
We recommend the following general design rules for achieving
hotspot-targeted cooling of multicore microprocessors. With
421
Fig. 9. Non-dimensionalized inlet manifold profiles. Wm is half-width of inlet
manifold. Solid line is straight manifold profile while dashed lines are converging
inlet manifold profiles. Numbers next to each manifold profile indicate the
corresponding um value.
embedded manifold microchannel cooling concept as the basis and
chip power map divided into parallel HSBG and BG zones, the
design consists of:
(1) Inlet slot nozzles positioned over cores and outlet slot noz-
zles positioned over background to concentrate impinge-
ment cooling on the hotspots.
(2) Smallest feasible microchannel wall width to minimize the
overall pressure drop.
(3) Fine channels over cores, coarse channels over background
along with flow distribution between HSBG and BG zones
selected to achieve higher heat transfer coefficient over hot-
spots and thus minimize the chip temperature gradient.
(4) Highest allowable total flow rate that satisfies pressure drop
and pumping power constraints.
(5) Flow throttling channels towards outlet slot nozzles in the
BG zones to realize the flow distribution selected in (3)
above.
(6) All streamwise microchannel pitches related through inte-
gral multiples to ensure uninterrupted flow in HSBG and
BG zones.
for
7. Conclusions
A novel concept for energy efficient, hotspot-targeted embed-
ded liquid cooling of multicore microprocessors was presented.
The design consists of fine channels over the hotspots, coarse chan-
nels over the background and introduces a flow throttling zone to
regulate flow in different regions. Optimized hotspot-targeted
422 C.S. Sharma et al. / Applied Energy 138 (2015) 414–422
designs were computationally obtained, for two highly non-
uniform, exemplar heat flux maps: (a) q00hs ¼ 150 W=cm2 and
q00bg ¼ 20 W=cm2 and (b) q00hs ¼ 300 W=cm2 and q00bg ¼ 20 W=cm2 .
Minimum chip temperature non-uniformities of 3.7 and 8.7 °C,
respectively were achieved for the two cases, while adhering to
strict, industrially relevant constraints on pressure drop (<0.35 bar)
and pumping power (<1% of chip power). It was shown that the
optimized designs compare very favorably against a base design
selected to represent the limit of cooling with uniform embedded
microchannels and uniform flow distribution. Simulations for a full
heat sink highlighted the flow distribution behavior of the opti-
mized microchannel structure and insignificant effect of the man-
ifold shape on the cooling performance of the heat sink. Lastly,
general rules for design of hotspot-targeted microchannel heat
sinks were described.
Appendix A. Supplementary material
Supplementary data associated with this article can be found, in
the online version, at http://dx.doi.org/10.1016/j.apenergy.2014.
10.068.
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