Electronics & Communications

Engineering Department
3rd Year- 2nd Semester
Digital Circuit (2) Laboratory

2023/2024
Dr.Ismail Ali
Eng.Ahmed Refaat
 Laboratory Experiments

Subject name Digital Circuit (2)

Lecturer Dr. Ismail Ali
year Third Year
Lecturer Eng.Ahmed Refaat
assistant
Student Name

Experiments Name
1 Constructing Read Only Memory (ROM) with Diodes
2 Erasable Programmable Read Only Memory (EPROM)
Circuit

3 Comparing between faulty and fault free for any circuit

4 Constructing a R-S Flip-Flop with Basic Logic Gate

5 Constructing a D Flip-Flop with R-S Flip-Flop

 Experiment (1)
Constructing Read Only Memory (ROM) with Diodes

OBJECTIVE
Understanding the structure of the most simple ROM.

DISCUSSION
Fig shows the basic circuit of a simple ROM made up of diodes and a 3-8 line decoder.
AO, A1 and A2 are input terminals. Incoming data are controlled by diodes. The 3-line
address has 8 states and there are four data at the output. The output capacity is 8><4.
 If outputs DQ~D3 passes through a 3-state gate, then it can be used in conjunction with
other ROM, with an additional "Enable" terminal to control the other ROM. Fig shows how
four ROM are used in parallel. The data terminals D0-D7 and Address Select A0-A7 are
connected in series.
When ¯CS1=0 and¯ CS2~¯CS4 =1, data in ROM1 is selected. CS1-CS4 only allow one
data to be accessed at a time.

To allow selection of different ROMs, ¯CS1 ~¯CS4 passes through a 2-4 decoder. The input
is controlled by A8, A9; as shown in Fig.

If A9A8 = "00", ROM1 is selected

If A9A8 = "01", ROM2 is selected.

If A9A8 = "10", ROM3 is selected.

If A9A8 = "11", ROM4 is eselcted.

The capacity of each ROM is (2 )^8 (A7~A0=2^8 , D0~D7=8), the total CAcapacity
is (2^8 )*8x4=2^8x2^2 x8 = 1Kx8(1K=1024).
PROCEDURE

1. Insert Connection Clips according to Fig. 5-4.

2. Connect inputs D1, D2 to data switches SWO and SW1

3. Measure and record the output when D2D1=01 and when D2D1=10.
4. If the power is cutoff and turned on again, will the outputs be the same?
 Experiment (2)
Erasable Programmable Read Only Memory (EPROM) Circuit

OBJECTIVE

Understanding the theory, structure and applications of EPROM.

DISCUSSIONS

During the process of program development, data stored in ROM have to be

modified and edited quite often. Although PROMs (Programmable Read Only
Memory) allow users to write-in data by themselves, it is an one-time only device
and is a very inconvenient, uneconomical to use if several modifications are
necessary. Fig. shows the general schematic of an EPROM.

The most obviously, and easily distinguishable mark on an EPROM is the quartz window on the top surface.
On the inside, it is the Metal-Oxide semiconductor Field Effect Transistor (MOSFET) that sets EPROM apart
from other memories. In a brand new EPROM, no boas exist at any of the MOSFETs so the MOSFETs are
not conductive, outputs D0-D3 are at logic "1" initially. If logic "0" is required at a certain bit, an EPROM Writer
must be used to apply a certain voltage (depend on EPROM specifications, typically 21V or 25V) to this
particular bit, injecting electrons into the gate. Since the gates are covered with insulating materials, the
electrons are trapped inside. The gates now become negatively charged, creating a path in the MOSFET and
making it conductive, or logic "0".

Exposure to ultraviolet light, through the quartz window, will erase data stored in the EPROM.The duration of
exposure depends on the amount, or length of data stored, typically anywhere from 15 to 30 minutes. When the
MOSFETs are exposed to ultraviolet light, the trapped electrons gains enough energy to escape the insulating
material, thus making the MOSFET not conductive.
EQUIPMENTS REQUIRED

KL-31001 Digital Logic Lab, Module KL-33010 PROCEDURES

1- Connect the circuit shown in Fig.

2-The 2764 EPROM has 13 address lines and 8 data lines, so the total
Capacity approximately 64Kb (213*23=216). Connect S1-S3 to outputs D7-D0 to Logic
Indicators L8-L1 respectively.

3- The state of input S1S2 will determine the outputs. How does the output change when
S3=0and S3=1?

S1 S2=00 - BILLBOARD 1
S1 S2=01 - BILLBOARD 2 (below are for reference only)
S1S2=10 - TRAFFIC LIGHT
S1S2=11 - FLASHING YELLOW
S1S2=00 -ADDRESS A6-A0 (000000-111111) OR 128 STATES
S1S2=01 -128 STATES
S1S2=10, B2B1=11 -AUTOMATICALLY SETS A6A5A4=000,
ADDRESS A3-A0 (0000-1111), OR 16 STATES

4- The input data follows:

(1) BILLBOARD 1, see Table 5-5

(2) BILLBOARD 2, same as above (for reference only) Outputs D6-D0 is like a
counter, change in binary from 000000-111111, D7=0.
(3) Traffic Light, Flashing Yellow and Normal Operation, as shown in Table (for
reference only)

0
A3A2A1A0
NEXT 1 2 3 4 5 6 7 8 9 A B c D E F
bit

DATA
PREVIOUS
BIT
A6A5 01 02 04 08 10 20 40 00 01 03 06 OC 18 30 60 00
A4 0
1 03 OC 30 40 00 01 03 07 OF 1F 3F 7F 7E 7C 78 70
2 60 40 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF 00 FF
3 40 20 10 08 04 02 01 00 40 20 10 08 04 02 01 00
4 60 30 18 OC 06 03 41 60 30 18 OC 06 03 41 60 30
5 18 OC 06 03 00 08 14 22 41 00 08 14 22 41 00 08
6 14 22 41 00 08 14 22 41 00 41 22 14 08 14 22 41
FF
7 00 41 22 14 08 00 FF 00 00 FF 00 00 FF FF 00
 Experiment (3)
Comparing between faulty and fault free for any circuit

1-Appling the following circuit on the module:

2- Comparing the result with the table
 Experiment (4)
Constructing a R-S Flip-Flop with Basic Logic Gates

1. Connect inputs A3, A4 to Pulser Switches SWA A (TTL), SWB B (TTL) output.
Connect outputs F6 and F7 to Logic Indicators L1, L2. What is the states of F6 and
F7? Turn the power off for a few seconds and turn it back on. What is the states of
F6 and F7 now?
2. Follow the input sequences in Table 4-5. Observe and record F6, F7.

3. Determine the Q and Q output, the R and S input. (set Pulser Switch to "1" first, then "0" and "1"
again)
4. Insert connection clips according to Fig. 4-13 to construct the circuit of Fig. 4-15. Connect inputs
Al, A2 to Pulser Switches SWAA, SWB B output.
Follow the input vequences in Table 4-6. Observe and record F6, F7
 Experiment (5)
Constructing a D Flip-Flop with R-S Flip-Flop

1. Insert connection clips according to Fig. 4-16 to construct the D flip-flop circuit of
Fig. 4-17.
2. Connect Al to SW1; CK2 to SWAA output and F6 to Ll .
3. Follow the input sequences in Table 4-7. Observe and record the output states.
 Experiments Degree
Constructing Read Only Memory (ROM) with
Diodes

Erasable Programmable Read Only Memory

(EPROM) Circuit

Comparing between faulty and fault free for

any circuit

Constructing a R-S Flip-Flop with Basic

Logic Gates

Constructing a D Flip-Flop with R-S Flip-Flop

Prepared by

Eng. Ahmed Refaat

Head of Laboratories
Revision
Department supervisor

Dr. Mohamed Eng. Mohammed Eng. Abd-

Metawea Elsherief Elrahman Khattaby