VSLI Lab

Semester #08
BEE (2020-2024)

Lab 1
Implementation of 4 to 1 Multiplexer using Verilog

Submitted to: Mehwish Majeed

Submitted by: Aimen anwar
Registration no: 2020-bee-002

Objective
i. Getting familiar with Verilog HDL for digital design.
 ii. To understand 4 to 1 MUX working principle
iii. To understand ModelSim Software for Development of Verilog HDL Codes.
iv. To implement and Test 4 to 1 MUX on Verilog HDL by
 Gate Level Modeling
 Data Flow Modeling
 Behavioral Modeling
Equipment Required
Modelsim software installed PCs
Introduction
Traditionally, digital design was done by the schematic entry. This has been replaced today by the use of Hardware Description
Language (HDL). In electronics, HDL is the language used for formal description of electronic circuits. HDL offers several advantages
over traditional design techniques such as efficient and convenient way of designing, simulation and synthesis of large electronic
circuits containing larger number of electronic components and devices, efficient verification of design in initial phase of
development. An entire digital system can be described in text format using prescribed set of roles and keywords (reserved words).
Two popular HDLs are Verilog and VHDL. The HDL used in our lab will be Verilog.
(1) VHDL (VHSLC HDL):
➔ Very high speed: Integrated circuit HDL
(2) Verilog HDL:
➔ Mostly in VLSI design uses verilog HDL.
➔ It uses similar procedures and constructs C- programming language.
➔ Verilog HDL provides for description of a digital System at all of the levels in VLSI design flow.
➔ This language is case sensitive.

To create a Verilog file using Modelsim follow the steps given at the end of this lab document.
Multiplexer
A multiplexer (MUX) is a digital switch which connects data from one of “n” inputs to a single output. A number of “Select Inputs”
determine which data input is connected to the output. The Block Diagram of MUX with “n” data inputs and “s” select lines is shown
in figure below:MUX acts like a digitally controlled multi-position switch where the binary code applied to the select inputs controls
the input source that will be switched on to the output.A 4 to 1 MUX is shown in figure below. There are four input lines, I0 to I3,
and two selections lines, S0 and S1, are decoded to select a particular input to appear at output.

EXPRESSION
f = (a . 𝑠0 . 𝑠1) + (b . 𝑠0 . 𝑠1) + (c . 𝑠0 . 𝑠1) + (d . 𝑠0 . 𝑠1)
Logic Diagram

4:1 mux is built using 4 AND gates, 2 NOT gate and one OR gate.
Lab Task
Implement 4 to 1 Mux using:
1) Gate Level Modeling
2) Data Flow Modeling

3) Behavioral Modeling