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Objective

To seek a challenging position in an organization, which provides opportunities to personal

growth and organizational growth as well.

Personal Details

Date of Birth & Age :

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Education
Course Institution Month & Year % / CGPA

Areas of Interest:

● Design For Testability

● Digital Design
Technical Skills:

● Design For Testability

o Scan Insertion
o DRC Analysis during Scan Insertion
o Scan Compression (EDT)
o ATPG Pattern Generation in Compressed mode and Bypass Mode
o Coverage Analysis and Improvement
o On-Chip Clock Controller
o Scan Pattern Simulation
o JTAG and Boundary Scan
o MBIST Insertion
● Digital Design
o Combinational and Sequential Circuit Design
o Basics of Verilog HDL
● Basics of Static Timing Analysis

Software Skills:

● Automation Languages : TCL

● Operating Systems
● HDL
● Text Editor
● EDA Packages
: Linux and Windows
: Verilog
: GVIM
: Tessent (Scan, TestKompress, MBIST),
QuestaSim and DesignCompilers

Projects (DFT Related)

MBIST and Scan Insertion on 2 small designs
Design 1 (Communication Chip):
Worked on small Hierarchical designs consisting of a Parent and multiple Child cores with flop count of
~4K. Performed MBIST Insertion, Scan Stitching and DRC Cleanup, EDT and OCC Insertion. Worked
on ATPG Coverage analysis, Pattern generation and Serial & Parallel Scan pattern Simulation.

Design 2 (Navigation Chip):

Worked on small design with flop count ~42K. Performed MBIST insertion, Scan Stitching and DRC
cleanup, EDT and OCC Insertion. Worked on ATPG Coverage analysis.

Projects (University)
 Hobbies

Declaration:
I do hereby declare that the particulars of information and facts stated above are true, correct, and
complete to the best of my knowledge and belief.

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