PD - 97343

IRFS4010-7PPbF
HEXFET® Power MOSFET
Applications D
l High Efficiency Synchronous Rectification in SMPS
VDSS 100V
l Uninterruptible Power Supply RDS(on) typ. 3.3mΩ
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
G max. 4.0mΩ
S ID 190A
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
D
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability S
S
l Lead-Free S
S
S
G
D2Pak 7 Pin

G D S
Gate Drain Source

Absolute Maximum Ratings

Symbol Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 190
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 130 A
IDM Pulsed Drain Current c 740
PD @TC = 25°C Maximum Power Dissipation 380 W
Linear Derating Factor 2.5 W/°C
VGS Gate-to-Source Voltage ± 20 V
dv/dt Peak Diode Recovery e 26 V/ns
TJ Operating Junction and -55 to + 175 °C
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300
(1.6mm from case)
Mounting torque, 6-32 or M3 screw 10lbxin (1.1Nxm)
Avalanche Characteristics
EAS (Thermally limited) Single Pulse Avalanche Energy d 330 mJ
IAR Avalanche Current c See Fig. 14, 15, 22a, 22b, A
EAR Repetitive Avalanche Energy f mJ

Thermal Resistance
Symbol Parameter Typ. Max. Units
RθJC Junction-to-Case jk ––– 0.40 °C/W
RθJA Junction-to-Ambient (PCB Mount) ij ––– 40

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IRFS4010-7PPbF

Static @ TJ = 25°C (unless otherwise specified)

Symbol Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 100 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.11 ––– V/°C Reference to 25°C, ID = 5mAc
RDS(on) Static Drain-to-Source On-Resistance ––– 3.3 4.0 mΩ VGS = 10V, ID = 110A f
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
IDSS Drain-to-Source Leakage Current ––– ––– 20 µA VDS = 100V, VGS = 0V
––– ––– 250 VDS = 100V, VGS = 0V, TJ = 125°C
IGSS Gate-to-Source Forward Leakage ––– ––– 100 nA VGS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 VGS = -20V
RG(int) Internal Gate Resistance ––– 2.1 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units Conditions
gfs Forward Transconductance 210 ––– ––– S VDS = 25V, ID = 110A
Qg Total Gate Charge ––– 150 230 nC ID = 110A
Qgs Gate-to-Source Charge ––– 36 ––– VDS = 50V
Qgd Gate-to-Drain ("Miller") Charge ––– 48 ––– VGS = 10V f
Qsync Total Gate Charge Sync. (Qg - Qgd) ––– 102 ––– ID = 110A, VDS =0V, VGS = 10V
td(on) Turn-On Delay Time ––– 19 ––– ns VDD = 65V
tr Rise Time ––– 56 ––– ID = 110A
td(off) Turn-Off Delay Time ––– 100 ––– RG = 2.7Ω
tf Fall Time ––– 48 ––– VGS = 10V f
Ciss Input Capacitance ––– 9830 ––– VGS = 0V
Coss Output Capacitance ––– 650 ––– VDS = 50V
Crss Reverse Transfer Capacitance ––– 260 ––– pF ƒ = 1.0MHz
Coss eff. (ER) Effective Output Capacitance (Energy Related)h ––– 730 ––– VGS = 0V, VDS = 0V to 80V h
Coss eff. (TR) Effective Output Capacitance (Time Related)g ––– 740 ––– VGS = 0V, VDS = 0V to 80V g

Diode Characteristics
Symbol Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current ––– ––– 186 A MOSFET symbol D

(Body Diode) showing the

ISM Pulsed Source Current ––– ––– 740 integral reverse G

(Body Diode)c p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.3 V TJ = 25°C, IS = 110A, VGS = 0V f
trr Reverse Recovery Time ––– 60 ––– ns TJ = 25°C VR = 85V,
––– 67 ––– TJ = 125°C IF = 110A
Qrr Reverse Recovery Charge ––– 150 ––– nC TJ = 25°C di/dt = 100A/µs f
––– 180 ––– TJ = 125°C
IRRM Reverse Recovery Current ––– 4.7 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)

Notes:
 Repetitive rating; pulse width limited by max. junction
temperature.
‚ Limited by TJmax, starting TJ = 25°C, L = 0.052mH
RG = 25Ω, IAS = 110A, VGS =10V. Part not recommended for use
above this value .
ƒ ISD ≤ 110A, di/dt ≤ 1310A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
„ Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
† Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
‡ When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
ˆ Rθ is measured at TJ approximately 90°C.
‰ RθJC value shown is at time zero.

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 IRFS4010-7PPbF
1000 1000
VGS VGS
TOP 15V TOP 15V
10V 10V
8.0V 8.0V
ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

7.0V 7.0V
100 5.0V 5.0V
4.5V 4.5V
4.3V 4.3V
BOTTOM 4.0V BOTTOM 4.0V

10 100

1 ≤60µs PULSE WIDTH

Tj = 25°C
4.0V 4.0V ≤60µs PULSE WIDTH
Tj = 175°C
0.1 10
0.1 1 10 100 0.1 1 10 100
V DS, Drain-to-Source Voltage (V) V DS, Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5
ID = 110A

RDS(on) , Drain-to-Source On Resistance

VGS = 10V
ID, Drain-to-Source Current (A)

100 2.0
T J = 175°C
(Normalized)

10 T J = 25°C
1.5

1 1.0

VDS = 50V
≤60µs PULSE WIDTH
0.1 0.5
2 3 4 5 6 7 -60 -40 -20 0 20 40 60 80 100120140160180

VGS , Gate-to-Source Voltage (V) T J , Junction Temperature (°C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature

100000 14.0
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, C ds SHORTED
ID= 110A
Crss = Cgd 12.0 VDS= 80V
VGS, Gate-to-Source Voltage (V)

Coss = Cds + Cgd VDS= 50V

10.0
C, Capacitance (pF)

10000 Ciss

8.0

6.0
Coss
1000
4.0
Crss
2.0

100 0.0
1 10 100 1000 0 25 50 75 100 125 150 175 200 225
VDS, Drain-to-Source Voltage (V) QG, Total Gate Charge (nC)

Fig 5. Typical Capacitance vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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 IRFS4010-7PPbF
1000 10000
OPERATION IN THIS AREA
LIMITED BY R DS(on)

ID, Drain-to-Source Current (A)

1000
ISD, Reverse Drain Current (A)

100
T J = 175°C 100µsec

100
10 10msec
T J = 25°C 1msec
10

DC
1
1
Tc = 25°C
VGS = 0V Tj = 175°C
Single Pulse
0.1 0.1
0.0 0.5 1.0 1.5 1 10 100 1000
VSD, Source-to-Drain Voltage (V) VDS, Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area
Forward Voltage

V(BR)DSS , Drain-to-Source Breakdown Voltage (V)

200 125
Id = 5mA
180
120
160

140
ID, Drain Current (A)

115
120

100 110

80
105
60

40
100
20

0 95
25 50 75 100 125 150 175 -60 -40 -20 0 20 40 60 80 100120140160180
T C , Case Temperature (°C) T J , Temperature ( °C )
Fig 9. Maximum Drain Current vs. Fig 10. Drain-to-Source Breakdown Voltage
Case Temperature
6.0 1400
ID
EAS , Single Pulse Avalanche Energy (mJ)

5.0 1200 TOP 21A

38A
1000 BOTTOM 110A
4.0
Energy (µJ)

800
3.0
600
2.0
400

1.0
200

0.0 0
0 10 20 30 40 50 60 70 80 90 100 110 25 50 75 100 125 150 175

VDS, Drain-to-Source Voltage (V) Starting T J , Junction Temperature (°C)

Fig 11. Typical COSS Stored Energy Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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 IRFS4010-7PPbF
1

Thermal Response ( Z thJC ) °C/W

D = 0.50
0.1 0.20
0.10
0.05
R1
R1
R2
R2
R3
R3
R4
R4
Ri (°C/W) τi (sec)
0.01 0.02 0.02001 0.000025
τJ τC
0.01 τJ τ
τ1 τ2
0.05145 0.000094
τ3 τ4
τ1 τ2 τ3 τ4 0.19436 0.002047

0.001
Ci= τi/Ri 0.13433 0.012818
Ci i/Ri
SINGLE PULSE Notes:
( THERMAL RESPONSE ) 1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case

1000
Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
100
0.01
Avalanche Current (A)

0.05
10 0.10

1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
400 Notes on Repetitive Avalanche Curves , Figures 14, 15:
TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
350 BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:
ID = 110A Purely a thermal phenomenon and failure occurs at a temperature far in
EAR , Avalanche Energy (mJ)

300 excess of Tjmax. This is validated for every part type.

2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
250 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
200 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
150
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
100
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
50
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
0
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
25 50 75 100 125 150 175
Iav = 2DT/ [1.3·BV·Zth]
Starting T J , Junction Temperature (°C) EAS (AR) = PD (ave)·tav

Fig 15. Maximum Avalanche Energy vs. Temperature

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IRFS4010-7PPbF
4.5 30
IF = 74A
4.0
VGS(th) , Gate threshold Voltage (V)

25 V R = 85V
TJ = 25°C
3.5
20 TJ = 125°C

3.0

IRR (A)
ID = 250µA 15
2.5 ID = 1.0mA
ID = 1.0A 10
2.0

1.5 5

1.0 0
-75 -50 -25 0 25 50 75 100 125 150 175 0 200 400 600 800 1000
T J , Temperature ( °C ) diF /dt (A/µs)

Fig 16. Threshold Voltage vs. Temperature Fig. 17 - Typical Recovery Current vs. dif/dt

30 1000
IF = 110A IF = 74A
900
25 V R = 85V V R = 85V
TJ = 25°C 800 TJ = 25°C

20 TJ = 125°C Q RR (A)
700 TJ = 125°C

600
IRR (A)

15
500

10 400

300
5
200

0 100
0 200 400 600 800 1000 0 200 400 600 800 1000
diF /dt (A/µs) diF /dt (A/µs)
Fig. 18 - Typical Recovery Current vs. dif/dt Fig. 19 - Typical Stored Charge vs. dif/dt

1000
IF = 110A
900 V R = 85V

800 TJ = 25°C
TJ = 125°C
700
Q RR (A)

600

500

400

300

200
0 200 400 600 800 1000
diF /dt (A/µs)

Fig. 20 - Typical Stored Charge vs. dif/dt

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 IRFS4010-7PPbF
Driver Gate Drive
P.W.
D.U.T P.W.
Period D=
Period
+

ƒ VGS=10V *
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
- • Low Leakage Inductance D.U.T. ISD Waveform
Current Transformer
+
Reverse
‚ Recovery Body Diode Forward
-
„ + Current Current
- di/dt
D.U.T. VDS Waveform
Diode Recovery
 dv/dt
VDD

RG • dv/dt controlled by RG VDD Re-Applied

• Driver same type as D.U.T. + Voltage Body Diode Forward Drop
• ISD controlled by Duty Factor "D" - Inductor Current
Inductor Curent
• D.U.T. - Device Under Test

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs

V(BR)DSS
15V
tp

L DRIVER
VDS

RG D.U.T +
V
- DD
IAS A
VGS
20V
tp 0.01Ω
I AS

Fig 22a. Unclamped Inductive Test Circuit Fig 22b. Unclamped Inductive Waveforms
RD
VDS VDS

VGS
90%
D.U.T.
RG
+
- VDD

V10V
GS 10%
Pulse Width ≤ 1 µs VGS
Duty Factor ≤ 0.1 %
td(on) tr t d(off) tf

Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Current Regulator Id
Same Type as D.U.T. Vds

Vgs
50KΩ

12V .2µF
.3µF

+
V
D.U.T. - DS
Vgs(th)
VGS

3mA

IG ID
Current Sampling Resistors Qgs1 Qgs2 Qgd Qgodr

Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
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IRFS4010-7PPbF

D2Pak - 7 Pin Package Outline

Dimensions are shown in millimeters (inches)

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/

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 IRFS4010-7PPbF

D2Pak - 7 Pin Part Marking Information

14

D2Pak - 7 Pin Tape and Reel

Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/08
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