DRAFT SCHEME

0200CST202122301

Total Pages: 5
Scheme of Valuation/Answer Key
(Scheme of evaluation (marks in brackets) and answers of problems/key)
APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
B.Tech Degree S4 (S, FE) / S2 (PT) (S) Examination January 2024 (2019 Scheme)
Course Code: CST202
Course Name: Computer Organization and Architecture
Max. Marks: 100 Duration: 3 Hours

PART A
(Answer all questions; each question carries 3 marks) Marks

1 Explain how addressing modes contribute to the efficiency and flexibility of (3)
computer architecture.
Definition of addressing modes – 1 Mark
Explanation of how addressing modes enhance efficiency by providing various
ways to specify operands – 1 Mark
How addressing modes contribute to flexibility in programming – 1 Mark
2 What are the steps involved in the execution of an instruction in computer (3)
architecture? Provide a brief overview of these steps.
Steps in instruction execution (Fetch, Execute) – 1 Mark
Explanation of the steps - 2 Marks
3 Differentiate between arithmetic and logic micro operations in the context of (3)
register transfer logic. Provide examples for each type of operation.
Definition of arithmetic micro operations. – 1 Mark
Definition of logic micro operations. - 1 Mark
Examples of both arithmetic and logic micro operations. - 1 Mark
4 What is the role of accumulator in a processor unit? How does it contribute (3)
to arithmetic and logic operations within the system?
Definition of the accumulator. – 1 Mark
How the accumulator is used in arithmetic operations. – 1 Mark
How the accumulator is used in logic operations. – 1 Mark
5 Highlight the key steps involved in the restoring method for binary division. (3)
Key steps (Algorithm) in the restoring method – 3 Marks

Page 1 of 5
 DRAFT SCHEME
0200CST202122301

6 Differentiate between instruction and arithmetic pipelines. (3)

Definition and explanation of instruction pipelines. – 1.5 Mark
Definition and explanation of arithmetic pipelines. – 1.5 Mark
7 Give the key characteristics of PLA-based control organization and its (3)
advantages.
Explanation of PLA-based control organization. – 1 Mark
Characteristics (programmability, flexibility). – 1 Mark
Advantages of using PLA-based control. – 1 Mark

8 Enumerate the differences between hardwired control and microprogram (3)

control.
Enumerating differences between the two approaches. – 3 Marks

9 What is the role of interrupts in I/O organization? List the steps that follow (3)
an interrupt request.
Role of interrupts in I/O organization. – 1 Mark
Steps of the process following an interrupt request. – 2 Marks

10 List the key features of semiconductor RAMs. How do these features (3)
contribute to their widespread use in modern computer systems?
Listing of key features of semiconductor RAMs
(volatility, speed, density). – 1 Mark
How these features contribute to widespread use – 2 Marks

PART B
(Answer one full question from each module, each question carries 14 marks)

Module -1
11 a) Three-bus structure, SUB R3, (R4) (8)
Control Sequence – 5 marks
Fetch instruction: PC → Memory → MAR → MDR → IR.
Decode: IR → Control Unit.

Page 2 of 5
 DRAFT SCHEME
0200CST202122301

Execute: ALU (subtract) → R3 ← R4 - [R4].

Update PC: PC + 1.
Explanation of each step in the control sequence – 3 Marks
b) Execution in straight-line and branching (6)
Distinction between straight-line sequencing and branching and relevant example
for each (e.g. ADD R1, R2; Branching - BEQ R3, R4, 10. ) - 3 Marks
Explanation of the impact on the instruction cycle (Branching may cause pipeline
flush, affecting cycle time) - 2 Marks
Comparison of the two execution scenarios. - 1 Marks
12 a) Single-bus organization, SUB (R2), R3 (8)
Single-bus organization – block diagram - 3 marks
Control sequence - 3 marks
Explanation of steps in the control sequence - 2 marks
b) Indirect addressing in addressing modes (6)
Concept of indirect addressing with relevant examples (e.g. MOV R1, (R2); JMP
(address) ) - 4 marks
How indirect addressing contributes to flexibility. - 2 marks

Module -2
13 a) Hardware implementation for executing the statement xT1: A ← B (7)
Design – 7 marks
b) 4-bit combinational logic shifter (7)
Design of logic shifter with control variables. – 2 marks
Definition of operations for each control variable (Input data shifted based on
control variables H1, H0), (H1 - Arithmetic shift, H0 - Logical shift) – 2 marks
Impact of control variables on shifting – 2 marks
14 a) 4-bit arithmetic circuit within ALU (7)
Design of a 4-bit arithmetic circuit (Full-adder for each bit; carry propagated)
– 3 marks
Describing addition and subtraction processes (Addition: Bit-wise addition;
carry-in from previous bit. Subtraction: Two's complement addition.) – 2 marks
Step-by-step breakdown of the processes involved and overall functioning of the
circuit – 2 marks

Page 3 of 5
 DRAFT SCHEME
0200CST202122301

b) I/O mapped I/O vs. memory mapped I/O (7)

Explanation of principles and applications (I/O ports as memory addresses vs.
dedicated I/O address space) – 4 marks
Advantages and disadvantages of the two mapping techniques – 3 marks
Module -3
15 a) Booth’s multiplication algorithm flow chart (8)
Flow chart with steps – 4 Marks
Booth's algorithm Step-by-step multiplication of (+24) and (-21) – 4 Marks
b) Principles of pipelining (6)
Pipelining principles (Divide instruction execution into stages) – 2 Marks
Overlapping of instructions. – 1 Marks
Fetch, Decode, Execute stages – 3 Marks
16 a) Hazards in pipeline processors (8)
Explanation of hazards – 4 Marks
Differentiation between structural, data, and control hazards – 2 Marks
Solutions for overcoming data hazards (Forwarding, Stalling, Branch Prediction)
– 2 Marks
b) 4x4 array multiplier design (6)
Design of the 4x4 array multiplier – Figure – 4 Marks
Step-by-step explanation of multiplying two binary numbers (Partial product
generation, addition) – 2 Marks
Module -4
17 a) Design of Hardwired control circuit (10)
Explanation of different steps in designing hardwired control unit – 10 marks

b) Differentiate between vertical and horizontal microinstructions. (4)

Differences – 4 marks
18 a) Microprogrammed CPU organization (7)
Well-structured design of microinstructions. – 3 Marks
Organization for executing arithmetic, logic, and data transfer instructions – 2
Marks
Explanation of how the microprogrammed CPU executes instructions – 2 Marks

Page 4 of 5
 DRAFT SCHEME
0200CST202122301

b) Illustration of microprogram sequencer functioning – figure - 3 Marks (7)

Explanation of the sequence of microinstructions and how it supports arithmetic
and logical operations – 2 Marks
Importance of microprogram sequencing – 2 Marks
Module -5
19 a) Mechanisms in accessing I/O devices (10)
Explanation of mechanisms like polling and interrupt-driven I/O – 3 Marks
Role of I/O organization – 3 Marks
Description of the steps taken by a processor to interact with different I/O
devices – 4 Marks
b) DMA in I/O organization (4)
Explanation of how DMA enhances data transfer between peripheral devices
and memory – 2 Marks
Description of the steps involved in DMA-based data transfer – 1 Marks
Advantages and challenges of using DMA in I/O organization – 1 Marks
20 a) Mapping functions in cache memory (10)
Role of mapping functions in cache memory – 3 Marks
Explanation of direct mapping, associative mapping, and set-associative
mapping – 4 Marks
Examples for each mapping technique – 3 Marks
b) Cycle stealing DMA vs. burst mode DMA (4)
Differentiation between cycle stealing DMA and burst mode DMA – 2 Marks
Explanation of scenarios where each type is preferred – 2 Marks
*********

Page 5 of 5