INTEGRATION, the VLSI journal 88 (2023) 278–285

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Integration, the VLSI Journal

journal homepage: www.elsevier.com/locate/vlsi

A highly-linear, sub-mW LNA at 2.4 GHz in 40 nm CMOS process✩

Didem Erol As 1 , Mustafa Berke Yelten ∗,1
Istanbul Technical University Electronics and Communications Engineering, Maslak, Sariyer, Istanbul, 34467, Turkey

ARTICLE INFO ABSTRACT

Keywords: This paper focuses on designing low-power, low-noise amplifiers (LNA) performances. Different LNA topologies
Ultra-low-power operating with sub-mW power consumption at 2.4 GHz have been implemented in a commercial 40 nm CMOS
Linearity improvement process. The LNA1 (cascode common source LNA) has a voltage gain of 12.22 dB, a noise figure (NF) of
LNA
4.35 dB, and a third-order input intercept point (IIP3) of −12.68 dBm at 995.6 μW while the proposed LNA2
Complementary metal-oxide–semiconductor
with improved linearity has a 5.68 dB gain, 5.13 dB NF, and a −0.12 dBm IIP3. The difference between both
(CMOS)
Intermodulation distortion (IMD)
final designs, which consist of improved linearity and gain, stems from the location of the gate inductance
Linearization (𝐿𝑔 ) in the chip. The proposed LNA3 with an on-chip 𝐿𝑔 has a voltage gain of 11.1 dB, an NF of 4.27 dB, and
RF circuit an IIP3 of -0.82 dBm. Moreover, the proposed LNA4 with an off-chip 𝐿𝑔 has 10.31 dB voltage gain, 3.68 dB
NF, and 0.89 dBm IIP3 at 989.6 μW in post-layout simulations. Comparing the LNAs, the proposed LNA4 with
an off-chip 𝐿𝑔 has the best figure-of-merit (FOM). This work aims to achieve improved linearity figures at
sub-mW power.

1. Introduction performance. In addition, voltage gain and linearity are important

In recent years, wireless technology has become more crucial as
health applications, the internet of things (IoT), and Bluetooth low-
energy (BLE) applications develop rapidly in variety. For instance,
using Bluetooth low energy technology, monitoring the instant body
signals through portable and wireless devices can be performed. Also,
body temperature and heart rate sensors are good examples of biomedi-
cal applications [1]. These medical devices, such as wireless
transceivers and implantable antennas, should be small and need to
operate at ultra-low power. Therefore, biomedical wireless transceivers
have been remarkably enhanced due to immense research on
transceiver topologies and RF circuit design using the standard CMOS
technology [2].
The low noise amplifier (LNA) is the first stage of receivers to am-
plify the filtered radio-frequency (RF) signal with noise and distortion
as little as possible. A superheterodyne receiver consists of 5 main
blocks: an antenna, an RF filter, a low-noise amplifier, a mixer, and
a voltage-controlled oscillator. The filtered RF signal received from
the antenna is mixed with a local oscillator in an RF receiver chain
and amplified by the LNA before being converted by the mixer [3].
After the down-converted signal is demodulated, it is digitized by an
analog-to-digital converter. LNAs, typically the first and one of the
most important receiver stages, greatly influence the overall receiver
performance metrics of LNAs. The LNA must have a large voltage gain
to suppress the noise of the subsequent stages [4]. However, power
consumption limits these performance criteria. Therefore, the main
goal is to minimize the tradeoff between power consumption and high
performance.
Low power operation is a design problem for the voltage gain and
noise due to the low current level. Also, linearity, characterized by the
third-order input intercept point (IIP3), is in tradeoff with the noise fig-
ure and voltage gain [5]. Therefore, linearity improvement techniques
must be employed to develop linear, low-power LNA designs. In this
paper, four low-power LNA topologies operating at 2.4 GHz with sub-
mW (below 1 mW) power consumption have been implemented in a
commercial 40 nm CMOS technology.
The first design, LNA1, has a high voltage gain and low IIP3
figure, whereas, through linearity-improving techniques, the second
design, LNA2, yields better IIP3 performance. However, the voltage
gain is significantly decreased when IIP3 goes up. A third topology,
LNA3, has been developed without degrading the IIP3 performance
to increase the voltage gain. The difference between the third and
last LNA (LNA4) circuits resides in whether 𝐿𝑔 is included on the
chip or not. Hence, the paper focuses on the design challenge of
achieving high linearity even though the current levels are quite low
due to the power consumption constraint of 1 mW. It is a difficult

✩ This work was sponsored by the Scientific and Technological Research Council of Turkey under the project TÜBİTAK 1001 118E253.
∗ Corresponding author.
E-mail addresses: erold@itu.edu.tr (D. Erol As), yeltenm@itu.edu.tr (M.B. Yelten).
1
The article was written jointly by Didem Erol and Mustafa Berke Yelten. Both authors have contributed equally to this research.

https://doi.org/10.1016/j.vlsi.2022.09.010
Received 30 April 2022; Received in revised form 17 September 2022; Accepted 26 September 2022
Available online 20 October 2022
0167-9260/© 2022 Elsevier B.V. All rights reserved.
D. Erol As and M.B. Yelten Integration 88 (2023) 278–285

Fig. 1. The schematic of (a) LNA1 (Cascode LNA) (b) LNA2 with improved linearity and degraded voltage gain (c) LNA3 having both better linearity and voltage gain performance
(d) LNA4 that matches LNA3 except the off-chip 𝐿𝑔 .

design problem as many biomedical instruments should operate with a Table 1

The performance specifications of the designed LNAs.
restricted power budget, yet they have to deliver high performance. In
particular, a very linear response is expected. This article demonstrates 𝑆11 < −10 dB
𝑆22 < −10 dB
that considering LNA4, it is possible to yield an IIP3 of above 0 dBm by 𝑆21 > 10 dB
leveraging linearity improvement techniques and combining them with NF < 4 dB
design approaches that ensure the voltage gain and the noise figure are IIP3 > −1 dBm
impacted the least, remaining within their specified ranges. In short, 𝑃𝐷𝐶 < 1 mW
𝑓𝐶 2.4 GHz
the contribution of this work lies in providing design solutions for low-
power, high-performance receivers, especially sought by biomedical
applications.
This paper has the following structure: Designs of the proposed consumption. In that regard, similar to a wide-band LNA operation
LNAs have been described in Section 2. Section 3 discusses the sim- case, the noise figure cannot be lowered as much as it should since the
ulation outcomes. Finally, conclusions have been drawn in Section 4. current necessary for that performance exceeds the limitation imposed
by the power consumption. Moreover, the voltage gain and linearity
2. Circuit description could not be freely optimized for the same reason.
In Fig. 2(a), 𝑀1 is the main transistor and the diode-connected 𝑀𝑎 is
The four LNA designs in Fig. 1 aim to operate with sub-mW power used to cancel the third-order intermodulation distortion (IMD3). Also,
consumption at 2.4 GHz. LNA1 in Fig. 1(a) is the classical cascode LNA. 𝑖2 can be expressed as
LNA2 in Fig. 1(b) is designed to improve IIP3 performance by adding
𝑀𝑎 as the IMD sinker. In LNA3, shown in Fig. 1(c), 𝑀𝑏 is added to 𝑖2 = 𝑖1 − 𝑖𝑎 , (1)
increase the voltage gain without degrading the IIP3 figure. Also, LNA4 where 𝑖1 , 𝑖2 , and 𝑖𝑎 are the drain currents of 𝑀1 , 𝑀2 , and 𝑀𝑎 , respec-
performs similarly to LNA3. 𝐿𝑔 is included as an on-chip component tively. A major source of IMD3 comes from the third-order nonlinearity
in LNA3 while it is left off-chip in LNA4, as in Fig. 1(d). The biasing of 𝑀1 since the nonlinear current generated in 𝑀1 is fully transferred to
conditions of all LNAs are slightly different, yet they all have a total 𝑀2 , which acts as a current buffer. If the drain of 𝑀1 has an additional
power consumption of less than 1 mW. Hence, each LNA has been current path, which selectively cancels the IMD3 current component, a
optimized for the noise figure, voltage gain, and linearity performance smaller IMD3 current component is transferred to 𝑀2 . Therefore, the
metrics by obeying this limitation. diode-connected transistor 𝑀𝑎 , which acts as the IMD3 sinker, has been
The operating frequency of the low-noise amplifier signal should added to LNA1, as in Fig. 2(a).
be in the 2.4 GHz Industrial Scientific Medicine (ISM) band. As seen The drain current of an n-MOSFET can be provided using the
in Table 1, required LNA characteristics are determined as a voltage power-series expansion as,
gain of at least 10 dB and a noise value of less than 4 dB. Input and
output reflection coefficients should be less than −10 dB. A low noise 𝑖𝑑 = 𝑔𝑚1 𝑉𝑔𝑠 + 𝑔𝑚2 (𝑉𝑔𝑠 )2 + 𝑔𝑚3 (𝑉𝑔𝑠 )3 , (2)
amplifier consuming less than 1 mW of total power while having an
where 𝑔𝑚𝑖 is 𝑛th order transconductance. Also, 𝑖1 and 𝑖𝑎 can be ex-
IIP3 higher than −1 dBm is aimed. Although the listed performance
pressed as,
specifications are rather modest for a narrow-band LNA, it should be
emphasized that these metrics aim for operation below 1 mW of power 𝑖1 = 𝑔𝑚1,𝑀1 𝑉𝑔𝑠1 + 𝑔𝑚2,𝑀1 (𝑉𝑔𝑠1 )2 + 𝑔𝑚3,𝑀1 (𝑉𝑔𝑠1 )3 , (3)

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D. Erol As and M.B. Yelten
Fig. 2. (a) The LNA with an NMOS IMD sinker (adopted in LNA2). (b) The third-order
transconductances of 𝑀1 , 𝑀2 , and 𝑀𝑎 .
𝑖𝑎 = 𝑔𝑚1,𝑀𝑎 𝑉𝑔𝑠𝑎 + 𝑔𝑚2,𝑀𝑎 (𝑉𝑔𝑠𝑎 )2 + 𝑔𝑚3,𝑀𝑎 (𝑉𝑔𝑠𝑎 )3 ,
where 𝑉𝑔𝑠1 and 𝑉𝑔𝑠𝑎 stand for the gate-source voltage of 𝑀1 and 𝑀𝑎 ,
respectively. 𝑉𝑔𝑠𝑎 is a function of 𝑉𝑔𝑠1 , so 𝑉𝑔𝑠𝑎 can be given using the
power-series expansion,
𝑉𝑔𝑠𝑎 = 𝑐1 𝑉𝑔𝑠1 + 𝑐2 (𝑉𝑔𝑠1 )2 + 𝑐3 (𝑉𝑔𝑠1 )3 ,
where 𝑐𝑖 is the frequency-dependent coefficient. A first-order approxi-
mation is enough to prove the cancellation, so the second- and third-
order components are neglected. Thus, 𝑖𝑎 can be found in terms of 𝑉𝑔𝑠1 :
𝑖𝑎 = 𝑔𝑚1,𝑀𝑎 𝑐1 𝑉𝑔𝑠1 + 𝑔𝑚2,𝑀𝑎 𝑐2 (𝑉𝑔𝑠1 )2 + 𝑔𝑚3,𝑀𝑎 𝑐3 (𝑉𝑔𝑠1 )3 .
Taking (2)–(6) into (1), 𝑖2 will be equal to:
𝑖2 = (𝑔𝑚1,𝑀1 − 𝑐1 𝑔1,𝑀𝑎 )𝑉𝑔𝑠1 + (𝑔𝑚2,𝑀1 − 𝑐12 𝑔𝑚2,𝑀𝑎 )(𝑉𝑔𝑠1 )2
+ (𝑔𝑚3,𝑀1 − 𝑐13 𝑔3,𝑀𝑎 )(𝑉𝑔𝑠1 )3 .
The coefficients 𝑐1 , 𝑐2 , and 𝑐3 depend on frequency, and 𝑐1 has a
positive sign since 𝑀1 pulls the current from 𝑀𝑎 commensurately [6].
Besides, it is aimed to cancel (𝑔𝑚3,𝑀1 − 𝑐13 𝑔𝑚3,𝑀𝑎 ) by adjusting the gate
biasing. However, IMD3 is not fully canceled due to the limited amount
of allocated power, so the circuit is designed to minimize the IMD3
component.
In Fig. 2(b), the graphs of the third-order transconductances (𝑔𝑚3 s)
for 𝑀1 , 𝑀2 , and 𝑀𝑎 were obtained by taking the third order derivative
of the related transistor drain currents with respect to 𝑉𝑔𝑠1 . The value
of 𝑔𝑚3,𝑀2 decreases from 400 mA/V3 to 160 mA/V3 at 𝑉𝑔𝑠1 = 531 mV
and 𝑃 = 986.6 μW. However, the voltage gain is also reduced due to
lowering in the (𝑔𝑚1,𝑀1 − 𝑐1 𝑔𝑚1,𝑀𝑎 ) expression. Therefore, 𝑀𝑏 is added
to increase the voltage gain, as shown in Fig. 1(d).
LNA4 with high linearity is designed in Fig. 1(d), including the
versions of 𝐿𝑔 being on and off-chip. The aim of the off-chip 𝐿𝑔 is to
obtain a high-quality factor, thereby reducing the occupied chip estate.
𝑔𝑚 in the LNA without the voltage gain improvement technique is
equal to the transconductance of 𝑀1 , 𝑔𝑚,𝑀1 = 11.24 mS, while 𝑔𝑚 in the
LNA with the voltage gain improvement technique is the sum of 𝑔𝑚,𝑀1
Integration 88 (2023) 278–285
Fig. 3. The small signal equivalent circuit of proposed LNA designs.
Fig. 4. 𝐾 and |𝛥| values depicting the stability of the designed LNA.
and 𝑔𝑚,𝑀𝑏 , thereby bringing the total to 13.31 mS. Sizing of 𝑀𝑏 should
be done not to disturb the IMD current balance so that the linearity
performance can be preserved.
The output resistance of LNA2, 𝑅𝑂𝑈 𝑇 drops by the addition of 𝑀𝑎 .
(4) In Fig. 3, 𝑅𝑂𝑈 𝑇 ,𝑎 which equals to (1∕𝑔𝑚𝑎 ) ∥ 𝑟𝑜𝑎 appears in parallel
with 𝑟𝑜1 . While 𝑅𝑂𝑈 𝑇 roughly equals to 𝑔𝑚2 𝑟𝑜2 𝑟𝑜1 for LNA1, it becomes
𝑔𝑚2 𝑟𝑜2 (𝑟𝑜1 ‖1∕𝑔𝑚𝑎 ‖𝑟𝑜𝑎 ) in LNA2. 𝑅𝑂𝑈 𝑇 of LNA2 is smaller than that of
LNA1 since 1∕𝑔𝑚𝑎 ≪ 𝑟𝑜1 , 𝑟𝑜𝑎 . When 𝑀𝑏 is introduced, the operating
current of the cascode stage slightly decreases due to the maximum
(5) power requirement of 1 mW. Reduction of the cascode stage current
provides an increase in 𝑅𝑂𝑈 𝑇 even though 𝑟𝑜𝑏 comes in shunt with
the output resistance of the cascode. Also, 𝑔𝑚 of 𝑀𝑏 boosts 𝐺𝑚 of the
LNA since it provides a voltage gain path in shunt with the cascode
amplifier. An increase in both 𝑅𝑂𝑈 𝑇 and 𝐺𝑚 improves the voltage gain
of LNA3.
(6) A spiral inductor has not been employed at the source since bond-
wires already cause an inductive effect there. Typically, bondwires
have a higher quality factor than spiral inductors, which helps reduce
the parasitic resistance and contribution to noise. By eliminating the
(7)
spiral inductors, the total chip area is reduced as well. The bondwire
inductance value here is chosen to be 500 pH which may be obtained
by using two parallel bond wires, each having a typical inductance of
1 nH.
𝑀𝑏 is directly connected to the input; hence, the stability must
be checked. The conditions for unconditional stability in terms of
S-parameters are shown in (8) and (9) [7].
|𝛥| = |𝑆11 𝑆22 − 𝑆12 𝑆21 | < 1. (8)
1 − |𝑆11 |2 − |𝑆22 |2 + |𝑆11 𝑆22 − 𝑆12 𝑆21 |2
𝐾= >1 (9)
2|𝑆12 𝑆21 |
In Fig. 4, 𝐾𝑓 and 𝐵1𝑓 , which refer to 𝐾 and |𝛥|, equal to 3.24 and
0.162 at 2.4 GHz, respectively. Thus, 𝑀𝑏 does not degrade the stability
of LNA.
3. Simulation results and discussion
The proposed LNA with high linearity has been designed in a
commercial CMOS 40 nm process technology with a supply voltage of
𝑉𝐷𝐷 = 1 V. The current consumption is 989.6 μA. All LNAs have been
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Table 2
Device sizes 𝑊 ∕𝐿 and circuit component values.
𝑀1 32 μm | 40 nm 𝐶1 200 pF
𝑀2 16 μm | 150 nm 𝐿𝑏 750 pH
𝑀𝑎 8 μm | 40 nm 𝐶𝑒𝑥 712 fF
𝑀𝑏 44 μm | 40 nm 𝐿𝑑 8.5 nH
𝐿𝑔 2.2 nH 𝐶2 483 fF

Fig. 6. (a) Voltage gain & NF (b) IIP3 of LNA1.

Fig. 5. The layout of the designed LNA4.

constructed and optimized to operate at 2.4 GHz. The simulations were

performed in Cadence Virtuoso and R+C+CC was chosen as the extrac-
tion type, which includes all parasitic resistances, parasitic capacitors,
and coupling capacitors in the post-layout simulations. Table 2 provides
the channel geometries (μm|nm) of the transistors and the component
values. The channel length of 𝑀2 has been chosen to be longer than
that of other transistors for a larger cascode output resistance. The
quality factors of both 𝐿𝑔 and 𝐿𝑏 are 80, which are designated to be
off-chip inductors. Also, the quality factor of the on-chip inductor 𝐿𝑑
is evaluated as 7.12. Fig. 5 shows the layout of the final LNA design,
whose area occupies 0.085 mm2 .
Figs. 6(a), and 6(b) show the performance of LNA1 when tuned
to operate at 2.4 GHz. It has a matched input and output impedance
(𝑆11 = −27 dB and 𝑆22 = −17 dB, respectively). In Fig. 6(a), it is shown
that the designed LNA1 achieves a voltage gain of 12.22 dB. Also, the
noise figure equals 4.35 dB. Finally, Fig. 6(b) presents an IIP3 of −12.68
dBm.
Figs. 7(a) and 7(b) demonstrate the performance of the LNA2 with
improved linearity at 2.4 GHz. Input and output reflection coefficients
satisfy the design specifications (𝑆11 = −17.97 dB and 𝑆22 = −23 dB,
respectively). In Fig. 7(a), the voltage gain reduces from 12.2 dB to
5.68 dB, while IIP3 is raised from −12.68 dBm to −0.12 dBm in
Fig. 7(b). Moreover, NF has jumped to 5.13 dB.
In Fig. 2(b), 𝑀𝑎 added to LNA1 to improve IIP3 performance. 𝑀𝑎
is also used to decrease IMD3 of 𝑀2 with the injected current. 𝑔3,𝑀2 is Fig. 7. (a) Voltage gain & NF (b) IIP3 of LNA2 with improved linearity.
decreased with subtraction of 𝑔3,𝑀𝑎 from 𝑔3,𝑀1 , which have the same
sign. The gate biasing and the sizing of 𝑀𝑎 are adjusted to eliminate
𝑔3,𝑀2 . Considering the power consumption constraint, 𝑔3,𝑀2 could not −0.82 dBm. Also, 𝑆11 and 𝑆22 have their values below −11 dB. Finally,
be fully eliminated. However, it can be reduced enough to increase the 𝐿𝑔 is kept on-chip in this LNA.
IIP3 value by approximately 12.5 dBm.
While IIP3 is improved by decreasing 𝑔3,𝑀2 , the voltage gain is
In Figs. 8(a), and 8(b), the performance of the LNA3 with improved
linearity and voltage gain is depicted. It demonstrates that the voltage degraded through the drop in 𝑔𝑚,𝑀2 , as shown in (7). 𝑀𝑏 is added to
gain is boosted by approximately 6 dB without degrading the IIP3 per- LNA2 to increase the voltage gain, as illustrated in Fig. 3. However,
formance. Fig. 8(a) reveals that the voltage gain and NF are improved 𝑀𝑏 reduces the isolation between the input and output ports of the
to 11.1 dB and 4.27 dB, respectively. In Fig. 8(b), IIP3 is found to be cascode LNA, characterized by the parameter 𝑆12 . Thus, 𝑀𝑏 should be

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D. Erol As and M.B. Yelten Integration 88 (2023) 278–285

Fig. 8. (a) Voltage gain & NF (b) IIP3 of LNA3 with improved linearity and voltage
gain.

Fig. 10. (a) 𝑆11 and (b) 𝑆22 of LNA4 with improved linearity and voltage gain (off-chip
𝐿𝑔 ).

Fig. 9. 𝑆12 of LNA1 and LNA3.

sized to increase the voltage gain without being so dominant that it

degrades the isolation. This issue has been investigated in Fig. 9, and
it is observed that 𝑆12 increased by 13 dB, but this change is deemed
tolerable within design specifications.
Figs. 10, 11, and 12 demonstrate the pre-layout and post-layout
performances of the LNA with improved linearity and voltage gain
(off-chip 𝐿𝑔 ). According to Figs. 10(a) and 10(b), input and output
reflection coefficients at 2.4 GHz are acceptable, with (𝑆11 = −19.36 dB
(pre-layout) and 𝑆11 = −13.35 dB (post-layout)) (𝑆22 = −21.21 dB (pre-
layout) and 𝑆22 = −15.42 dB (post-layout)). 𝑆22 is critical since the
designed LNA is aimed to be modular; hence, it can be employed in
different receiver structures. The DC lines that cross the input RF path
are critical in the LNA performance in the layout. Thus, these paths,
along with the input and output paths, are drawn wider to decrease
the parasitic resistance. Thus, no significant changes in 𝑆11 and 𝑆22 are Fig. 11. (a) Voltage gain and (b) NF of LNA4 with improved linearity and voltage
observed in post-layout simulations. gain (off-chip 𝐿𝑔 ).

As observed in Fig. 11(a), the designed LNA achieves a voltage gain

of 10.31 dB in post-layout simulations. The gain reduction in the post-
layout simulation results stems from the parasitic resistance. It is seen
in Fig. 11(b) that NF increases with a decrease in voltage gain.
Finally, IIP3 is enhanced in post-layout simulations compared to
pre-layout results, as demonstrated in Figs. 12(a) and 12(b). The induc-
tive effect between the source and the ground increases the linearity
while decreasing the gain. The increase in the linearity outcomes of
post-layout simulations stems from the source degeneration caused by
parasitic resistances.
The performance parameters of LNA4 have been simulated at four
different process corners (SS, FF, FS, and SF) and three different tem-
peratures (0 ◦ C, 25 ◦ C, and 75 ◦ C). The results are presented in Table 3.
As the temperature decreases, the voltage gain increases while NF

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Table 3
The performance of the LNA4 at different process corners and temperatures.
Temperature SS FF FS SF
0 ◦C 25 ◦ C 75 ◦ C 0 ◦C 25 ◦ C 75 ◦ C 0 ◦C 25 ◦ C 75 ◦ C 0 ◦C 25 ◦ C 75 ◦ C
𝑆11 (dB) −9 −9 −9 −8.75 −9.33 −10.6 −12 −13.0 −14.6 −12.7 −13.6 −15.4
𝑆22 (dB) −22.6 −21.1 −19 −13.4 −12.9 −12.3 −15.6 −15.0 −14 −16.9 −16.5 −15.8
𝑆21 (dB) 7 6.57 5.65 13.5 13.22 12.7 11 10.64 9.88 10.4 9.99 9.2
NF (dB) 4.5 4.99 5.97 2.36 2.64 3.2 3.22 3.6 4.35 3.33 3.72 4.5
IIP3 (dBm) 7.73 8.18 7 −2.56 −2.69 −2.43 −0.20 −0.32 −0.07 4.38 3.69 3.74

Fig. 12. IIP3 (a) (pre-layout) and (b) (post-layout) of LNA4 with improved linearity
and voltage gain (off-chip 𝐿𝑔 ).

Table 4
The MC analysis for LNA4.
Best value Worst value Mean
𝑆11 (dB) −27.2 −8.53 −14.01
𝑆22 (dB) −24.52 −12.09 −16.91
𝑆21 (dB) 12.19 7.99 10.24
NF (dB) 2.95 4.66 3.73
IIP3 (dBm) 9.44 −5.27 2.2

Table 5
Performances of the proposed LNAs.
LNA1 LNA2 LNA3 LNA4 (pre-layout) LNA4 (post-layout)
𝑆21 (dB) 12.22 5.68 11.1 11.49 10.31
NF (dB) 4.35 5.13 4.27 3.38 3.68
𝑆11 (dB) −27 −17.97 −21 −19.36 −13.35
𝑆22 (dB) −16 −23 −14.78 −21.21 −15.42
IIP3 (dBm) −12.68 −0.12 −0.82 −0.7 0.89
P1dB (dBm) −23.74 −12.13 −13.57 −11.54 −11.16
𝑃𝐷𝐶 (μW) 995.6 986.6 997.2 1079 989.6
FOM 0.198 1.36 2.82 6.10 7.05

decreases. 𝑆11 degrades for the SS and FF process corners. Except for Fig. 13. Histograms of different performance parameters in Monte Carlo simulations:
these issues, other performance parameters are acceptable. (a) 𝑆11 (b) 𝑆22 (c) 𝑆21 (d) NF (e) IIP3.

The performance of LNA4 is also investigated under process vari-

ations and mismatch using the Monte Carlo (MC) analysis over 200
samples (100 samples for IIP3) in Fig. 13. Table 4 lists the worst,

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Table 6
Performance of the proposed LNA regarding its counterparts.
Gain (dB) NF (dB) IIP3 (dBm) 𝑃𝑑𝑐 (μW) 𝐹𝑐 (GHz) Tech. (nm) FOM
This Work (post-layout) 10.31 3.68 0.89 989.6 2.4 40 7.05
[12] (measurement) 11 6.8 −2.2 174 2.4 65 6.56
[13] (post-layout) 18.2 3.38 −4.32 967 2.4 180 2.93
[14] (post-layout) 14 3.45 −8 980 2.4 180 0.92
[8] (pre-layout) 14 5.2 −8.6 30 2.4 40 15.2
[15] (measurement) 12.6 5.5 ∼6.5 −9 750 0.1∼7 90 0.47
[16] (measurement) 12.3 4.9∼16 −9.5 400 0.1∼2.2 130 0.87
[17] (measurement) 14 4∼6 −10 250 0.6∼4.2 130 1.87
[18] (measurement) 17.4 2.8 −10.7 480 2.4 65 1.71
[9] (measurement) 13.9 8.9 −13 69 2.4 65 1.27
[19] (measurement) 12.2 1.9∼2.2 −16 350 3∼5 130 0.97
[10] (measurement) 21.5 6.3 −16 900 2.4 28 0.11
[11] (measurement) 6.9 3 −18 44 2.4 16 1.25
[20] (post-layout) 13.64∼15.64 4.5∼6 −5∼ -6 600 0.03∼3 180 1.30
[21] (measurement) 16.8 6.6 −16.4 350 4 28 0.20

best, and mean values of the performance parameters achieved in MC
simulations.
Table 5 summarizes the performances of four different LNAs. While
LNA1 is not suitable to satisfy the linearity specification, the IIP3 per-
formance has been dramatically improved by approximately 12.5 dBm
in LNA2, thereby meeting the requirements. However, the voltage gain
and NF of LNA2 are well below the specifications. Although the voltage
gain and IIP3 performances are enhanced in LNA3, this topology may
occupy a huge chip area due to the on-chip input matching circuit. By
taking 𝐿𝑔 off-chip, all performance metrics of LNA4 are made compliant
with the initial design specifications. Since 𝐿𝑔 is off-ship, a high-quality
factor can be assumed, further improving overall performance. When
the figure of merits (FOMs), calculated per the expression provided in
(10), of four LNAs are compared topologies, LNA4 is the most successful
of all in terms of achieved performance metrics.
Gain (dB) × IIP3 (μW)
𝐹 𝑂𝑀 = . (10)
(NF (dB) − 1) × Power (μW)
In Table 6, performance metrics of LNA4 are compared with the
results of various low-power LNAs reported in the literature with an
operating frequency in the range of 0.1 GHz to 7 GHz. Although the
FOM value of [8] is higher than that of LNA4, its IIP3 is almost equal
to that of LNA1. Except for [8], LNA4 is the best of all compared studies
in terms of the FOM value. Moreover, the power consumption of [9] is
remarkably low; however, its NF is extremely high, and the reported
IIP3 value is excessively lower than the LNA4 design described in this
work. Also, [10,11] are remarkable in terms of using deep nanoscale
CMOS technologies. However, the NF of [10] is very high, while the
voltage gain of [11] is significantly low.
4. Conclusion
In this paper, four LNAs using two different techniques to improve
linearity and voltage gain are designed at sub-mW power in a com-
mercial 40 nm CMOS process at 2.4 GHz. The proposed LNA, LNA4,
powered by a 1 V supply, achieves an IIP3 figure of 0.89 dBm and
dissipates 989.6 μW at 2.4 GHz. It has a voltage gain of 10.31 dB
and a noise figure of 3.68 dB. Based on its design metrics, LNA4
can be employed in ultra-low-power, high-performance receivers, as
frequently encountered in biomedical applications.
Declaration of competing interest
The authors declare that they have no known competing finan-
cial interests or personal relationships that could have appeared to
influence the work reported in this paper.
Data availability
Data will be made available on request.
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