FEE 402 Section2

FEE 402: Electronics B
2. Introduction to Microcomputers and Microprocessors

2.1 Microcomputers
A microcomputer is defined as a stand-alone system based on a microprocessor. A stand-alone
system is one that is able to operate without additional equipment. Fig.2.1 shows a block diagram
of a simple microcomputer. The four major parts are the:
 microprocessor aka central processing unit or CPU
 memory
 input and output circuitry or I/O
 bus system which connect the above three parts together.
Fig. 2.1
There are two types of microcomputers: the general purpose digital microcomputer and the
embedded microcomputer. The general purpose digital microcomputer is what most people
understand by the word computer. It is what is commonly referred to as a personal computer
(PC) and it has all the necessary memory and input/output devices required by the user to
execute a wide range of application programs.
An embedded computer on the other hand is one dedicated to a specific application. A good
example of an embedded microcomputer lies at the heart of an Automated Teller Machine
(ATM). When a customer inserts his/her card in a slot, the microcomputer reads the relevant
details from the magnetic strip on the card. The customer keys in an identity code (PIN), and the
microcomputer validates the code and then invites the customer to perform a transaction. Once
the transaction is completed, the microcomputer updates the data on the magnetic strip and
operates a mechanical subsystem that returns the card to the user.
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A system incorporating an embedded microcomputer is referred to as an embedded system.

Examples of embedded systems include:
o Photocopiers and printers
o Engine controllers, anti-lock braking systems, traction control systems and navigational
systems for modern automobiles.
o Home automation systems like thermostats, air conditioners and security monitoring
systems.
o Household appliances including microwave ovens, washing machines, television
sets, DVD players. etc.
o Flight control systems and missile guidance systems.
o Medical equipment
o Measuring equipment such as digital storage oscilloscopes and logic analyzers.
o Mobile phones with additional capabilities, e.g. mobile phone with PDA.
o Video game consoles.
o Programmable Logic Controllers (PLCs) for industrial automation.
o Traffic light controllers.
The fundamental difference between an embedded microcomputer and a general purpose

microcomputer is the optimization of the former to suit a single function. Typically, an
embedded microcomputer contains only the functions strictly necessary for it to execute the
allocated task. A general purpose microcomputer has the memory and input/output devices to
perform a broad range of functions. In particular, a general purpose microcomputer almost
always has facilities for expansion, thereby enabling the user to add more memory or
input/output devices at a later date.
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2.1.1 Microprocessor
A microprocessor is the central processing unit (CPU) of a microcomputer constructed within a
single chip, and it is entirely useless on its own. To make it into a viable microcomputer, it needs
to be connected to the memory, I/O and the bus system.
The microprocessor performs a large number of functions, including:

 directing the operation of all other units in the microcomputer by providing
timing and control signals for all elements.
 fetching instructions and data from memory, and carries out the instructions.
 transferring data to and from input/output devices.
 performing arithmetic and logic operations on data
 responding to input/output generated control signals such as RESET and INTERRUPT.
The above functions are performed by CPU‘s three components; an arithmetic and logic unit
(ALU) which can perform arithmetical and logical calculations like add, subtract, AND, OR, etc.,
registers which are temporary binary data storage locations and the control unit which generates
and control bus signals. A special register in the CPU is the address counter or program counter
(or instruction pointer) which is used to hold the address of the next instruction to be fetched
from the memory.
2.1.2 Memory
The memory section usually consists of RAM and ROM. External memory may consist of flash
memory, magnetic floppy disks, magnetic hard disks, DVDs or compact disks. Memory has
three purposes:
 to store instructions that the computer is going to perform
 to store the data to be operated on by the computer
 to store intermediate and final results of operations performed during program execution.
The operation of the memory is controlled by information carried in the control bus.
2.1.3 Input/Output
The input/output or I/O section allows the computer to take in data from the outside world or
send data to the outside world. Examples of input devices include: keyboards, mouse, joystick
and ADCs. Output devices include: video display terminals or CRT, printers, LED readouts and
DACs. Modems are both input and output devices. The I/O devices allow the user and the
computer to communicate with each other. The actual physical devices used to interface the
computer buses to external systems are called ports.
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For some devices, data transfer with the microcomputer is in serial form (one bit at a time) e.g.
the CRT, while for others, data transfer is in parallel form e.g. the microcomputer transfers
information to a printer one byte at a time.
2.1.4 Bus System

A bus is defined as a bundle of wires (parallel lines). The bus system consists of the data bus, the
control bus and the address bus. These buses connect the microprocessor to each of the memory
and I/O elements so that information can be exchanged between the microprocessor and these
devices.
Address Bus
This is a unidirectional bus, because information flows over it only in one direction - from the
CPU to the memory or I/O elements. It is used to specify the address of a memory location or an
I/O device involved in a data transfer.
The number of memory locations that the CPU can address is determined by the number of
address lines. If the CPU has N address lines then it can directly address 2N memory locations.
For example, a CPU with 16 address lines can address 216 or 65, 536 memory locations.
The address bus consists of 16, 20, 24, 32, 64 or more parallel signal lines.
Data Bus
This is a bidirectional bus, since data can flow to or from the CPU. It is used to carry data
associated with a memory or I/O transfer. During a READ operation, the CPU's data pins act as
inputs and receive data that has been placed on the data bus by the memory or I/O element
selected by the address on the address bus. During a WRITE operation, the CPU's data pins act
as outputs and place data on the data bus, which is then sent to the selected memory or I/O
device.
The data bus consists of 8, 16, 32, 64 or more parallel signal lines.
Control Bus
This is a set of signals that are used to synchronize the activities of the separate microcomputer
elements. Some control signals are from the CPU to other elements to tell them what kind of
operation is in progress, e.g. READ/WRITE signal. The CPU sends out signals on the control
bus to enable the outputs of addressed memory devices or port devices. Typical control bus
signals are memory read, memory write, I/O read, and I/O write. To read a byte of data from a
memory location, for example, the CPU sends out the address of the desired byte on the address
bus and then sends out a memory read signal on the control bus. The memory read signal enables
the addressed memory device to output the byte of data on the data bus where it is read by the
CPU.
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The I/O elements can also send control signals to the CPU e.g. RESET signal which causes the
CPU to reset to a particular starting state, INTERRUPT REQUEST signal used by I/O devices to
get attention of the CPU when it is performing other tasks.
The control bus consists of 4 - 10 parallel signal lines.
2.1.5 Hardware, Software, and Firmware

Hardware is the name given to the physical devices and circuitry of the computer. Software
refers to the programs written for the computer. Firmware is the term given to the programs
stored in ROMs or in other devices which keep their stored information when the power is turned
off.
2.2 Microprocessor Evolution

A common way of categorizing microprocessors is by the number of bits that their ALU can
work with at a time. A Microprocessor with a 4 - bit ALU will be referred to as a 4-bit
microprocessor, regardless of the number of address lines or the number of data bus lines that it
has.
The first microprocessor was the Intel 4004 produced in 1971. This 4004 was a 4-bit device
intended to be used with some other devices in making a calculator. Some logic designers,
however, saw that this device could be used to replace PC boards full of combinational and
sequential logic devices. Also, the ability to change the function of a system by just
reprogramming, rather than redesigning the hardware, is very appealing. It was these factors that
pushed the evolution of microprocessors.
In 1972 Intel came out with the 8008 which was capable of working with 8-bit words. In 1974
Intel announced the 8080 which had a much larger instruction set than 8008. The 8080 is
referred to as a second-generation microprocessor.
Soon after Intel produced 8080, Motorola came out with MC 6800, another 8-bit general purpose
CPU. Some of the other competitors were the MOS technology 6502 and the Zilog Z80. The 16-
bit microprocessors entered the marketplace in the late 1970s and early 1980s. Then came the
32-bit processors.
Modern microprocessors are 32-bit or 64-bit. Generally, a microprocessor with a large number of
bits can process instructions more quickly than one with a small word size when both
microprocessors are running at the same clock speed. Microprocessors are also designed such
that the ones with a larger word size can process more instructions than their predecessors [the
computer made with the Intel 4004 was a calculator-like device, while modern 32 and 64-bit
microprocessors are used to make full multimedia computers (those that can process data, video
and sounds)].
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Some people classify microprocessors into two groups based on their origin. These are the 6‘s
group and the 8‘s group. Family trees for these groups are presented Figure 2.2.
Fig. 2.2
We observe that as we progress upward on the family tree the trend is towards greater
complexity. Complexity is noted in the figure, in terms of the bit size of the internal registers.
The 6‘s group traces its origin back to the original 6800 Microprocessor designed by Motorola.
The 8‘s group traces its origin back to Intel‘s 8080 Microprocessor. Each branch in Fig.2.2 is
labeled near the top with the manufacturer responsible for its development.
For many years, manufacturers identified the microprocessors with number codes such as 4004,
8086, 68000, Z8000, etc., but of late, the microprocessors have brand names e.g. PowerPC,
Pentium, Itanium, Xeon, etc.
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Microprocessors are made for different applications. The most powerful microprocessors are
used in servers and workstations. Then there are microprocessors for PCs (microcomputers). At
the lower end are the microprocessors used in embedded systems - these are low-cost
microprocessors, and they make over well over 50% of all the microprocessors that are sold.
Microprocessors have provided a cost-effective solution for control and many modern appliances
have a number of microprocessors in their control circuitry. A modern luxury car, such as a
Mercedes Benz S-class or a BMW 7-series has over 100 microprocessors for functions such as
engine management, dashboard control, braking system, traction control, climate control, cruise
control, navigational system, etc. A Boeing 777 jet has over 1200 microprocessors.
In this course, we concentrate on the microprocessors used in microcomputers (PCs). The PC

market is dominated by Intel Corporation (with over 50% market share). Other manufacturers of
microprocessors for microcomputers include Motorola, Advanced Micro Devices (AMD),
Apple, IBM and National Semiconductors. The Motorola range of microprocessors features the
8-bit 6800, and the 32-bit 68000, 68020, 68030, 68040 and the 68060. Motorola microprocessors
are used in Apple computers. Motorola have since abandoned the 68XXX series microprocessors
and have teamed up with IBM and Apple to produce the PowerPC range of microprocessors.
The most recent microprocessors are 64-bit and these include Intel's Xeon and Itanium 2, AMD's
Opteron and Athlon 64, and IBM's Power PC G5. These processors were initially mostly used in
servers, but they are now in the PC market.
The Pentium microprocessors have millions of transistors packed within a small area e.g. the
Pentium IV processor has over 40 million transistors. The millions of transistors switching in
such close proximity collectively generate a lot of heat energy which could potentially damage
the IC. For this reason, Pentium microprocessors have fans mounted on the IC for cooling
purposes.
Table 2.1 shows the evolution of Intel microprocessors starting with 8086. From the year 2001 to
the present the design of microprocessors has emphasized on multi-threaded and multi-core
microprocessors.
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Microprocessor Year Data/Address Internal Clock Speed

Bus Width (bits) (MHz)
8086 1978 16/20 4.77-8
80286 1982 16/24 6-20
80386 1985 32/32 16-33
80486 (DX – DX4) 1989-1993 32/32 25-120
Pentium I 1993 64/32 60-200
Pentium II 1997 64/32 233-450
Pentium III 1999 64/32 450-1200
Pentium IV 2000 64/32 1400-3600
Itanium 2001 64/64 1400-3600
Table 2.1
2.3 The INTEL 8086 Microprocessor

In this course, we will deal mainly with the Intel 8086 microprocessor. This is because the
modern microprocessors are extensions of 8086. Further, an 8086 microprocessor kit is available
in the department.
The 8086 was the first 16-bit Microprocessor to be introduced by Intel Corporation, as illustrated
in Table 2.1. It is designed to be upwardly compatible with the older 8080/8085 series of 8-bit
microprocessors. The upward compatibility allows programs written for the 8080/8085 to be
easily converted to run on the 8086.
The word 16-bit means that its arithmetic logical unit, internal registers, and most of its
instructions are designed to work with 16-bit binary words. The 8086 has a 16-bit data bus, so it
can read data form or write data to memory and ports either 16-bits or 8-bits at a time. The 8086
has a 20-bit address bus, so it can address any one of 220 or 1,048,576 memory locations (1
Mbyte of memory). Each of the 1,048,576 memory addresses of the 8086 represents a byte-wide
location. Words will be stored in two consecutive memory locations. If the first byte of a word is
at an even address, the 8086 can read the entire word in one operation. If the first byte of the
word is at an odd address, the 8086 will read the first byte of the word in one operation, and the
second byte in another operation.
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3. Microprocessor Architecture
The term architecture, as used in microprocessor circuits, describes the functional components
that make up the microprocessor and the interaction between them as seen by the programmer.
As illustrated by the block diagram in Fig.3.1, the 8086 microprocessor architecture can be
broadly divided into two independent functional parts known as the Execution Unit (EU) and the
Bus Interface Unit (BIU).
Fig. 3.1
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The EU is where the actual processing of data takes place inside the 8086 µP. It is here that
instructions are received, decoded, and executed from the instruction queue portion of BIU. The
instructions are taken from the top of the instruction queue on the first-in, first-out, or FIFO,
basis. Data processed by the EU can be transmitted to the memory or peripheral devices through
the BIU. EU has no direct connection with the outside world and relies solely on the BIU to feed
it with instructions and data.
The BIU on the other hand sends out addresses, fetches instructions from memory, reads data
from ports and memory, and writes data to ports and memory. In other words the BIU handles all
transfers of data and addresses on the buses for the execution unit. The BIU has the task of
making sure that the bus is used to its fullest capacity in order to speed up operations. This
function is carried out in two ways:
 by fetching the instructions before they are needed by the execution unit and storing them
in the instruction queue, the 8086 µP is able to increase computing speed.
 by taking care of all bus control functions, the EU is free to concentrate on processing
data and carrying out the instructions.
3.1 Execution Unit (EU)

The execution unit consists of:
o Arithmetic Logic Unit
o Control Unit
o Flag Registers
o General Registers
3.1.1 Arithmetic Logic Unit (ALU)

ALU is 16-bits wide in 8086 µP. The ALU is the calculator part of the execution unit. It consists
of electronic circuitry that performs arithmetic operations or logic operations on the binary
represented electrical signals. It can do the following 16-bits arithmetic operations
(i) Addition
(ii) Subtraction
(iii) Multiplication
(iv) Division
The ALU can also perform logical operations such as NOT, AND, OR, and EXCLUSIVE OR.
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3.1.2 Control Unit

The control system provides a path for the flow of instructions into the ALU, the general
registers, and the flag register. It also fetches and transmits instructions, data and control bus
signals between µP and the other devices of the system.
3.1.3 Flag Register

A flag is a flip-flop which indicates some condition produced by the execution of an instruction
or controls certain operations of the EU. The Flag Register is a special register associated with
the ALU. A 16-bit flag register in the EU contains nine active flags. Fig.3.2 shows the location
of the nine flags in the flag register.
Fig. 3.2
Six flags are status flags: AF, CF, OF, SF, PF and ZF. The remaining three flags are control
flags: DF, IF, and TF.
 AF (auxiliary flag). If this flag is set, there has been a carry out or borrow out of bit 3
into bit 4. This flag is used during decimal arithmetic instructions.
 CF(carry flag). If this flag is set, there has been a carry out or borrow of the most
significant bit. It is used by instructions that add and subtract multi byte numbers.
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 OF (overflow flag). If this flag is set, an arithmetic overflow has occurred; that is, a
significant digit has been lost because the size of the result exceeded the capacity of its
destination location.
 SF (sign flag). Since negative binary numbers are represented in the 8086/8088 in
standard 2s complement notation, SF indicates the sign of the result ( 0 = positive, 1 =
negative).
 PF (parity flag). If this flag is set, the result has even parity, an even number of 1s. This
flag can be used to check for transmission errors.
 ZF (zero flag). If this flag is set, the result of the operation is 0.
 DF(direction flag). Setting DF causes string instructions to auto-decrement (count

down); that is, to process strings from the high address to the low address, or from right
to left. Clearing DF causes string instructions to auto-increment (count up), or process
strings from left to right.
 IF ( interrupt-enable flag) Setting IF allows the µP to recognize external (maskable)

interrupt requests. Clearing IF disables these interrupts. IF has no effect on either
nonmaskable external or internally generated interrupts.
 TF (trap flag) . Setting TF puts the processor into single-step mode for debugging. In
this mode the µP automatically generates an internal interrupt after each instruction,
allowing a program to be inspected as it executes instruction by instruction.
3.1.4 General Registers

The CPU has eight 16-bit general registers. They are divided into two files of four registers
each. They are:
(a) The data register file and
(b) The pointer and index register file
(a) Data Registers

EU has eight general purpose registers set as data registers, labeled AH, AL, BH, BL, CH, CL,
DH and DL. These are used to hold intermediate results. The H represents the high- order or
most- significant byte and the L represents the low- order or least-significant byte.
Each of these registers may be used separately as 8-bit storage areas or combined to form one
16-bit (one word) storage area. The acceptable register pairs are AH and AL, BH and BL, CH
and CL and DH and DL. The AH-AL pair is referred to as the AX register, the BH-BL pair is
referred to as the BX register, the CH-CL pair is referred to as the CX register, and the DH-DL
pair is referred to as the DX register.
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The AL register is also called the Accumulator. For 16-bit operations, AX is called the
accumulator.
The 8086 register set is very similar to those of earlier generation 8080 and 8085
microprocessors. Many programs written for the 8080 and 8085 could easily be translated to run
on the 8086.
(b) The pointer and index registers
Stack Pointer
A Stack is a section of memory set aside to store addresses and data while a subprogram is being
executed. An entire 64 K bytes segment is set aside as Stack in 8086 µP. The upper 16 bits of the
starting address for this segment is kept in the stack segment register. The Stack Pointer (SP)
register contain the 16-bit offset from the start of the segment to the memory location where a
word was most recently stored on the Stack. The memory location where a word was most
recently stored is called the top of Stack. Fig.3.2 illustrates the details.
Fig. 3.3
The physical address for a stack read or for a stack write is produced by adding the contents of
the stack pointer register to the segment base address in SS. To do this the contents of the Stack
segment register are shifted four bit positions left and the contents of SP are added to the shifted
result. In the figure 5000 H in SS is shifted left four bit positions to give 50000H. When FFEOH
in the SP is added to this, the resultant physical address for the top of the stack will be 5FFEOH.
The physical address can be represented either as a single number 5FFEOH, or it can be
represented in SS:SP form as 5000:FFEOH.
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Other pointer and Index Registers

In addition to the Stack Pointer register, SP, the EU contains a 16-bit base pointer (BP) register.
It also contains a 16-bit Source index (SI) register and a 16-bit destination index (DI) register.
These three registers can be used for temporary storage of data just as the data registers.
However, their main use is to hold the 16-bit offset of a data word in one of the segments. That
is, the pointer and index registers are usually used to point to or index to an address in memory.
When used in this manner, these registers are address registers that designate a specific location
in the memory that may be frequently used by the program. The addresses contained in these
registers can be combined with information from the BIU to physically locate the data in the
memory.
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3.2 Bus Interface Unit (BIU)

The BIU is made up of
 An instruction queue
 Address Control
3.2.1 Instruction Queue

The instruction queue is used as a temporary memory storage area for data instructions that are
to be executed by the µP. The BIU, through the control unit, prefetches instructions and stores
them in the instruction queue. This allows the execution unit to perform its calculations at
maximum efficiency. Because the BIU and EU essentially operate independently, the BIU
concentrates on loading instructions into the instruction queue. This usually takes more time to
do than the calculations performed by the execution unit. In effect, the BIU and the EU work in
parallel. The instruction queue is a first-in, first-out (FIFO) memory. This means that the first
instruction loaded into the instruction queue by the bus control unit will be the first instruction to
be used by the ALU.
3.2.2 Address control

The address-control unit is used to generate the 20-bit memory address that gives the physical or
actual location of the data or instruction in memory. This unit consists of the instruction pointer,
the segment registers and the address generator as shown in Fig. 3.4.
Instruction Pointer
The Instruction Pointer (IP) is a 16- bit register that is used to point to, or tell the µP, the
instruction to execute next. Therefore, the instruction pointer is used to control the sequence in
which the program is executed. Each time the execution unit accepts an instruction, the
instruction pointer, is incremented to point to the next instruction in the program.
Segment Registers
There are four segment registers. They are the code segment (CS), the data segment (DS), the
stack segment (SS), and the extra segment (ES). These registers are used to define a logical
memory space or memory segment that is set aside for a particular function:
 The CS register points to the current code segment. Instructions are fetched from this
segment.
 The DS register points to the current data segment. Program variables and data are held in
this area.
 The SS register points to the current stack segment. Stack operations are performed on
locations in the SS segment.
 The ES register points to the current extra segment, which is also used for data storage.
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Each of the segment registers can be up to 64 kilobytes long. A particular segment is made up of
an uninterrupted section of memory locations. A segment can be addressed separately using the
base address that is contained in its segment register. The base address is the starting address for
that segment.
Address Generator
The address-generator unit is used with the segment registers to generate the 20-bit physical
address required to identify all the possible memory addresses. The 20 address lines give a
maximum physical memory size of 220 address locations, or 1,048,576 bytes of memory. But all
the registers in the µP are only 16 bits wide. The physical address is obtained by shifting the
segment base value four bit positions (one hexadecimal position) and adding the offset or logical
address of the segment.
Fig. 3.4
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3.3 Clock, Bus and Instruction Cycles

An 8086 requires a clock signal from some external, crystal- controlled clock generator to
synchronize internal operations in the processor. Different versions of the 8086 have maximum
clock frequencies ranging from 5 MHz to 10 MHz. The period of one clock cycle then ranges
between 100 and 200 nanoseconds.
The 8086 operates in time periods called bus cycles. Each bus cycle requires 4 clock cycles to
complete. Therefore, the bus cycle for 5 MHz µp is completed after a minimum time of 800 ns.
A typical bus cycle is shown in fig. 3.5.
(a)
(b)
Fig. 3.5
One cycle of a clock is referred to as a state. A state is measured from the 50 percent point on the
falling edge of one clock pulse to 50 percent point on the falling edge of the next clock pulse- T1
in the figure is a state. Each basic bus operation such as reading a byte from memory or writing a
word to a port requires some number of states. The group of states required for a basic bus
operation is called a machine cycle. The total time it takes the 8086 to fetch and execute an
instruction is called an instruction cycle. An instruction cycle consists of one or more machine
cycles.
Two major bus cycles are the read bus cycle and the write bus cycle. The read bus cycle is
activated when the microprocessor is reading information from the memory or an I/O device.
During the read bus cycle, there are normally four clock cycles T1 ,T2, T3 and T4. However, if the
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device outputting data to the µP needs more time to send the data, a wait state (Tw) is initiated
by placing extra clock cycles (Tw's) between cycles T3 and T4.
Once a microprocessor has fetched the necessary program instructions and data through the BIU,
its next step is to execute the instructions. The EU receives the instruction from the instruction
queue and executes it. Some instructions may take 2 clock cycles to execute, where as others
may take as many as 100 clock cycles to execute. In older microprocessors this left the bus idle
while the µP was executing a long instruction, as shown in the fig. 3.6. However, since the 8086
µP is broken up into two functional units, the BIU and EU, it avoids much of the idle time
required by older microprocessors. It does this by having the BIU pre fetch instructions and place
them into the instruction queue and data registers while the EU is executing the program
instructions. Therefore, while the bus is busy during a read cycle, the EU can be executing the
previous instructions. When the bus is busy during a write cycle, the EU can be executing
another instruction. This greatly increases the effective speed of the entire system.
Fig. 3.6
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3.4 8086 Pin Diagram

Fig 8 shows the 8086 pin diagram. Vcc is on pin 40 and ground on pins 1 and 20. 8086 requires
+5v supply.
Fig 3.7
3.4.1 Microprocessor modes of operation

8086 µp can operate in two modes: minimum or maximum mode.
For the minimum mode, MN/ MX (pin 33) is asserted HIGH. This is the mode for typically
smaller systems with a single µp. Functions shown on the parenthesis (pins 24-31) apply.
The µp operates in maximum mode when MN/ MX is asserted LOW. This is the mode for larger
systems with more than one µp.
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3.4.2 Common Pin Descriptions

AD0 - AD15 (I/O): Address/Data Bus
These lines constitute the time multiplexed memory/IO address during the first clock cycle (T1)
and data during T2, T3 and T4 clock cycles. Fig. 3.8 shows the timing of AD0 – AD15 lines to
access data and address.
T4 T1 T2 T3 T4
AD0 - AD15 Address Data
Fig. .2
A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status

During T1 state these lines are the four most significant address lines for memory operations.
During I/O operations these lines are low. During memory and I/O operations, status information
is available on these lines during T2, T3, and T4 states.
S5: The status of the interrupt enable flag bit is updated at the beginning of each cycle.
The status of the flag is indicated through this bus.
S6: When Low, it indicates that 8086 is in control of the bus. During a "Hold
acknowledge" clock period, the 8086 tri-states the S6 pin and thus allows another bus master to
take control of the status bus.
S3 & S4: Lines are decoded as follows:
A17/S4 A16/S3 Function
0 0 Extra segment access
0 1 Stack segment access
1 0 Code segment access
1 1 Data segment access
Table 3.1
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After the first clock cycle of an instruction execution, the A17/S4 and A16/S3 pins specify which
segment register generates the segment portion of the 8086 address. Thus by decoding these lines
and using the decoder outputs as chip selects for memory chips, up to 4 Megabytes (one Mega
per segment) of memory can be accessed. This feature also provides a degree of protection by
preventing write operations to one segment from erroneously overlapping into another segment
and destroying information in that segment.
BHE /S7 (O): Bus High Enable/Status
During T1 state the BHE should be used to enable data onto the most significant half of the data
bus, pins D15 - D8. Eight-bit oriented devices tied to the upper half of the bus would normally
use BHE to control chip select functions. BHE is Low during T1 state of read, write and
interrupt acknowledge cycles when a byte is to be transferred on the high portion of the bus.
The S7 status information is available during T2, T3 and T4 states. The signal is active
Low and floats to 3-state during "hold" state. This pin is Low during T1 state for the first
interrupt acknowledge cycle.
RD (O): READ
The Read strobe indicates that the processor is performing a memory or I/O read cycle. This
signal is active low during T2 and T3 states and the Tw states of any read cycle.
This signal floats to tri-state in "hold acknowledge cycle".
TEST (I)
TEST pin is examined by the "WAIT" instruction. If the TEST pin is Low, execution continues.
Otherwise the processor waits in an "idle" state. This input is synchronized internally
during each clock cycle on the leading edge of CLK.
INTR (I): Interrupt Request
It is a level triggered input which is sampled during the last clock cycle of each instruction to
determine if the processor should enter into an interrupt acknowledge operation. A subroutine is
vectored via an interrupt vector look up table located in system memory. It can be internally
masked by software resetting the interrupt enable bit.
INTR is internally synchronized. This signal is active HIGH.
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NMI (I): Non-Maskable Interrupt

An edge triggered input, causes a type-2 interrupt. A subroutine is vectored via the interrupt
vector look up table located in system memory. NMI is not maskable internally by software. A
transition from a LOW to HIGH on this pin initiates the interrupt at the end of the current
instruction. This input is internally synchronized.
Reset (I)
Reset causes the processor to immediately terminate its present activity. To be recognised, the
signal must be active high for at least four clock cycles, except after power-on which requires a
50 Micro Sec. pulse. It causes the 8086 to initialize registers DS, SS, ES, IP and flags to all
zeros. It also initializes CS to FFFF H. Upon removal of the RESET signal from the RESET
pin, the 8086 will fetch its next instruction from the 20 bit physical address FFFF0H. The reset
signal to 8086 can be generated by the 8284. (Clock generation chip). To guarantee reset from
power-up, the reset input must remain below 1.5 volts for 50 Micro sec. after Vcc has reached
the minimum supply voltage of 4.5V. The RES input of the 8284 can be driven by a simple RC
circuit.
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8086 RESET line provide an orderly way to start an executing system. When the processor
detects the positive-going edge of a pulse on RESET, it terminates all activities until the signal
goes low, at which time it initializes the system as shown in table 3.2.
CPU component Contents
Flags Cleared
Instruction Pointer 0000H
CS register FFFFH
DS register 0000H
SS register 0000H
ES register 0000H
Queue Empty
Table – 3.2 System Registers after Reset
Ready (I)
Ready is the acknowledgement from the addressed memory or I/O device that it will
complete the data transfer. The READY signal from memory or I/O is synchronized by the
8284 clock generator to form READY. This signal is active HIGH. The 8086 READY input is
not synchronized. Correct operation is not guaranteed if the setup and hold times are not met.
CLK (I): Clock

Clock provides the basic timing for the processor and bus controller. It is asymmetric
with 33% duty cycle to provide optimized internal timing.
Since the 8086 does not have on-chip clock generation circuitry, an 8284 clock generator chip
must be connected to the 8086 clock pin. The crystal connected to 8284 must have a frequency 3
times the 8086 internal frequency. The 8284 clock generation chip is used to generate READY,
RESET and CLK.
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MN/ MX (I): Maximum / Minimum

This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself
generates all bus control signals. In maximum mode the three status signals are to be
decoded to generate all the bus control signals.
3.4.3 Minimum Mode Pins

The following 8 pins function descriptions are for the 8086 in minimum mode; MN/ MX = 1.
M/ IO (O): Status line

This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it
accesses I/O and when high it access memory. M / IO becomes valid in the T4 state preceding a
bus cycle and remains valid until the final T4 of the cycle. M/ IO floats to 3 - state OFF during
local bus "hold acknowledge".
WR (O): Write
Indicates that the processor is performing a write memory or write IO cycle, depending on the
state of the M / IO signal. WR is active for T2, T3 and Tw of any write cycle. It is active
LOW, and floats to 3-state OFF during local bus "hold
acknowledge ".
INTA (O): Interrupt Acknowledge

It is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2,
T3, and T4 of each interrupt acknowledge cycle.
ALE (O): Address Latch Enable

ALE is provided by the processor to latch the address into the 8282/8283 address
latch. It is an active high pulse during T1 of any bus cycle. ALE signal is never floated.
DT/ R (O): DATA Transmit/Receive

In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the
direction of data flow through the transceiver. This signal floats to tri-state off during local bus
"hold acknowledge".
DEN (O): Data Enable

It is provided as an output enable for the 8286/8287 in a minimum system which uses the
transceiver. DEN is active LOW during each memory and IO access. It will be low beginning
39
with T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until
the middle of T4. It floats to tri-state off during local bus "hold acknowledge".
HOLD & HLDA (I/O): Hold and Hold Acknowledge

Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged,
HOLD must be active HIGH. The processor receiving the "HOLD " request will issue HLDA
(HIGH) as an acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue
of HLDA, the processor will float the local bus and control lines. After "HOLD" is detected as
being Low, the processor will lower the HLDA and when the processor needs to run another
cycle, it will again drive the local bus and control lines.
3.4.4 Maximum Mode Pins
The following pins function descriptions are for the 8086 systems in maximum mode (i.e.. MN/
MX = 0). Only the pins which are unique to maximum mode are described below.
S2, S1, S0 (O): Status Pins

These pins are active during T4, T1 and T2 states and is returned to passive state (1,1,1 during
T3 or Tw (when ready is inactive). These are used by the 8288 bus controller to generate all
memory and I/O operation) access control signals. Any change by S2, S1, S0 during T4 is used
to indicate the beginning of a bus cycle. These status lines are encoded as shown in table 3.3.
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S2 S1 S0 Characteristics
0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code access
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive State
Table 3.3
QS0, QS1 (O): Queue – Status

Queue Status is valid during the clock cycle after which the queue operation is performed. QS0,
QS1 provide status to allow external tracking of the internal 8086 instruction queue. The
condition of queue status is shown in table 3.4.
Queue status allows external devices like In-circuit Emulators or special instruction set extension
co-processors to track the CPU instruction execution. Since instructions are executed from the
8086 internal queue, the queue status is presented each
CPU clock cycle and is not related to the bus cycle activity. This mechanism allows
(1) A processor to detect execution of a ESCAPE instruction which directs the co-
processor to perform a specific task and
(2) An in-circuit Emulator to trap execution of a specific memory location.
QS1 QS1 Characteristics
0 0 No operation
0 1 First byte of opcode from queue
1 0 Empty the queue
1 1 Subsequent byte from queue
Table 3.4
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LOCK (O)
It indicates to another system bus master, not to gain control of the system bus while LOCK is
active Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active
until the completion of the instruction. This signal is active Low and floats to tri-state OFF
during 'hold acknowledge".
RQ / GT0 and RQ / GT1 (I/O): Request/Grant

These pins are used by other processors in a multi processor organization. Local bus masters of
other processors force the processor to release the local bus at the end of the processors current
bus cycle. Each pin is bi-directional and has an internal pull up resistors. Hence they may be
left un-connected.
3.5 Timing Diagrams

The Write and Read cycle timing diagrams will be illustrated in class.
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4 Interrupts in µP 8086
An interrupt is the method of accessing the µP by a peripheral device. An interrupt is used to

cause a temporary halt in the execution of a program. The µP responds to the interrupt with an
interrupt service routine, which is a short program or subroutine that instructs the µP on how to
handle the interrupt.
When the 8086 is executing a program, it can get interrupted because of one of the following:
a) Due to an interrupt getting activated. This is called hardware interrupt.
b) Due to an exceptional happening during an instruction execution, such as division of a
number by zero. This is generally termed as exceptions or Traps.
c) Due to the execution of an Interrupt instruction like "INT 21H". This is called a Software
interrupt.
The action taken by the 8086 is similar for all the three cases, except for minor differences.
There are two basic types of interrupts, maskable and non-maskable. A nonmaskable interrupt
requires an immediate response by the µP. It is usually used for serious circumstances like power
failure. A maskable interrupt is an interrupt that the µP can ignore depending upon some
predetermined condition defined by the status register. Interrupts are also prioritized to allow for
the case when more than one interrupt needs to be serviced at the same time.
4.1 Hardware interrupts

In a microcomputer system, whenever an I/O port wants to communicate with the
microprocessor urgently, it interrupts the microprocessor. In such a case, the microprocessor
completes the instruction it is presently executing. Then, it saves the address of the next
instruction on the stack top. Then it branches to an Interrupt Service Subroutine (ISS), to service
the interrupting I/O port. An ISS is also commonly called as an Interrupt Handler. After
completing the ISS, the processor returns to the original program, making use of the return
address that was saved on the stack top.
In 8086 there are two interrupt pins. They are NMI and INTR. NMI stands for non maskable
interrupt. Whenever an external device activates this pin, the microprocessor will be interrupted.
This signal cannot be masked. NMI is a vectored interrupt. This means, the 8086 knows where to
branch to service the NMI request. If both NMI and INTR are activated at the same time, NMI
will be serviced first.
In an 8086 system the first 1 K bytes memory from 00000H to 003FFH is set aside as a table for
storing the starting addresses of interrupt service procedures. Since 4 bytes are required to store
the CS and IP values for each interrupt service procedure, the table can store starting addresses
for up to 256 interrupt procedures. The starting address of an Interrupt Service procedure stored
in this table is often called as Interrupt Vector Table or the Interrupt Pointer Table.
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Fig. 4.1 shows how the 256 interrupt pointers are arranged in the memory table. The lowest five
types are dedicated to specific interrupts such as the divide by zero interrupt and the non
maskable interrupt. The next 27 interrupt types, from 5 to 31 are reserved by Intel for use in
future microprocessors. The upper 224 interrupt types, from 32 to 255, are available to use for
hardware and software interrupts.
Fig. 4.1
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4.1.1 Action taken by 8086 when NMI is activated

When NMI pin interrupts the 8086, a branch takes place to the ISS, whose interrupt type number
is 2. The action taken is as follows:
i. Completes the current instruction that is in progress.
ii. Push the Flag register values on to the stack.
iii. Push the CS value and IP value of the return address on to the stack.
iv. IP is loaded from contents of the word location 00008H.
v. CS is loaded from contents of next word location 0000AH.
vi. Interrupt flag and trap Flag are reset to O.
Return from Interrupt Handler (IRET)

The execution of the IRET instruction results in POP from the stack top, the IP, CS and Flag
registers. Thus return back to the interrupted program takes place. When the control is
transferred back to the interrupted program, the register values are not the same it was before the
occurrence of interrupt. To solve this problem, an ISS starts with saving register values on the
stack. Finally, the register values are restored from the stack and a return to the interrupted
program takes place using the IRET instruction.
4.1.2 Action taken by 8086 when INTR line is activated

Whenever an external signal activates the INTR pin, the microprocessor will be interrupted only
if interrupts are enabled using set interrupt Flag instruction. If the interrupts are disabled using
clear interrupt Flag instruction, the microprocessor will not get interrupted even if INTR is
activated. That is, INTR can be masked.
INTR is a non vectored interrupt, which means, the 8086 does not know where to branch to
service the interrupt. The 8086 has to be told by an external device like a Programmable
Interrupt controller regarding the branch.
Whenever the INTR pin is activated by an I/O port, if Interrupts are enabled and NMI is not
active at that time, the microprocessor finishes the current instruction that is being executed and
gives out a ‗0‘ on INTA pin twice. When INTA pin goes low for the first time, it asks the
external device to get ready. In response to the second INTA the microprocessor receives the 8
bit, say N, from a Programmable Interrupt Controller. The action taken is as follows:
i. Complete the current instruction.
ii. Activates INTA output, and receives type Number, say N.
iii. Flag register value, CS value of the return address & IP value of the return address are
pushed on to the stack.
iv. IP value is loaded from contents of word location N x 4.
v. CS is loaded from contents of the next word location.
vi. Interrupt Flag and trap Flag are reset to 0.
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At the end of the ISS, there will be an IRET instruction. This performs popping off from the
stack top to IP, CS and Flag registers. Finally, the register values which are also saved on the
stack at the start of ISS, are restored from the stack and a return to the interrupted program takes
place using the IRET instruction.
4.2 Exceptions or Traps
4.2.1 Divide-by-zero interrupt - Type 0

The 8086 will automatically do a Type 0 interrupt if the result of a division operation is too large
to fit in the destination register. For example, if we execute DIV BL, then AX will be divided by
BL. The quotient will be stored in AL and the remainder in AH. If AX content is 4060H and BL
is 02H, then the quotient is 2030H. But the 8-bit AL register cannot hold this data. This results in
automatic branching to an ISS. It is an internal interrupt, and the 8086 branches to an ISS whose
interrupt Type number is 0.
Action taken by the 8086 when divide by zero error occurs is as follows:
i. Flag register value is pushed on to the stack.
ii. CS value of the Return address and IP value of the Return address are pushed on to the
stack.
iii. IP is loaded from contents of word location 0x4 = 00000H.
iv. CS loaded from contents of next word location, 00002H.
v. Interrupt Flag and trap Flag are reset to 0.
The action taken by the ISS could be to display a suitable error message on the CRT and then
halt the proceedings. Or, it could be to set a bit in a memory location to indicate an error, and
then return to the interrupted program using the IRET instruction.
4.2.2 Single-Step Interrupt - Type 1

When we tell a System to single- Step , it will execute one instruction and stop. We can then
examine the contents of the registers and memory locations. If they are correct, we can tell the
system to go on and execute the next instruction. In other words, when in single-Step mode, a
system will stop after it executes each instruction and wait for further directions from the user.
The 8086 trap flag and type 1 interrupt make it quite easy to implement a single-Step feature.
If the 8086 trap flag is set, the 8086 will automatically do a type 1 interrupt after executing each
instruction. It is an internal interrupt caused by the completion of an instruction execution. It is
useful for debugging a program.
The action taken by the 8086 when T flag is set to 1, and an instruction execution is completed is
as follows:
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i. Flag register values is pushed on to the stack.

ii. CS value of the return address and IP value of the return address are pushed on to the
stack.
iii. IP is loaded from the contents of the word location, 1x4 = 00004H.
iv. CS is loaded from contents of the next word location, 00006H.
v. Interrupt Flag and trap Flag are reset to 0.
The action taken by the ISS could be to display the contents of the various registers on the CRT
and then return to the interrupted program using the IRET program.
4.3 Software interrupt Instructions

These are instructions that can be inserted at the desired places in a program to cause an
interrupt. They are:
a) INT instructions with type number specified.
b) INT 3, Break Point Interrupt instruction.
c) INTO, Interrupt on overflow instruction.
When one of these instructions is executed a branch to an ISS takes place. Because their
execution results in a branch to an ISS, they are called interrupts. Software Interrupt instructions
can be used to test the working of the various Interrupt handlers. For example, we can execute
INTO instruction to execute type 0 ISS, without really having to divide a number by 0. Similarly,
we can execute INT 2 instruction to test NMI ISS.
4.3.1 INT-Interrupt Instruction with Type number Specified

The mnemonic for this is INT. It is a 2 byte instruction. The first byte provides the op-code and
the second byte the Interrupt type number. Op-code for this instruction is CDH. The execution of
an INT instruction, say INT N, when N is the value in the range 00H to FFH, results in the
following:
i. Flag register value is pushed on to the stack.
ii. CS value of the Return address and IP value of the Return address are pushed on to the
stack.
iii. IP is loaded from the contents of the word location N x 4.
iv. CS is loaded from the contents of the next word location.
v. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS take place. During the ISS, interrupts are disabled because the Interrupt
flag is reset to 0. At the end of the ISS, there will be an IRET instruction. Thus a return back to
the interrupted program takes place with Flag registers unchanged.
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4.3.2 INT3-Break Point Interrupt Instruction

When a break point is inserted, the system executes the instructions up to the breakpoint, and
then goes to the break point procedure. Unlike the single-Step feature which stops execution
after each instruction, the breakpoint feature executes all the instructions up to the inserted
breakpoint and then stops execution.
The mnemonic for the instruction is INT3. It is a 1 byte instruction. Op-code for this is CCH.
The execution of INT3 instruction results in the following:
i. Flag register value is pushed on to the Stack.
ii. CS value of the return address and IP value of the return address are pushed on to the
Stack.
iii. IP is loaded from the contents of the word location 3x4 = 0000CH.
iv. CS is loaded from the contents of the next word location.
v. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS takes place. During the ISS, interrupts are disabled because Interrupt
flag is reset to 0. At the end of the ISS, there will be an IRET instruction to return back to the
interrupted program.
A break point interrupt service procedure usually saves all the register contents on the Stack.
Depending upon the system, it may then send the register contents to the CRT display and wait
for the next command from the user.
4.3.3 INTO - Interrupt on overflow instruction

The 8086 overflow flag, OF, will be set if the signed result of an arithmetic operation on two
signed numbers is too large to be represented in the destination register or memory location. For
example, if we add the 8-bit signed number 01101100 and the 8-bit signed number 01010001,
the signed result will be 10111101. This is correct if we add unsigned binary numbers, but it is
not the correct signed result.
There are two ways to detect and respond to an overflow error in a program. One way is to put
the jump if overflow instruction, JO, immediately after the arithmetic instruction. If the overflow
flag is Set, execution will jump to the address specified in the JO instruction. At this address an
error routine may be put which respond to the overflow.
The second way is to put the INTO instruction immediately after the arithmetic instruction in the
program. The mnemonic for the instruction is INTO. It is a 1 byte instruction. The op-code for
this is CEH. It is a conditional interrupt instruction. Only if the overflow flag is Set, a branch
takes place to an interrupt handler whose interrupt type number is 4. If the overflow flag is reset,
the execution continues with the next instruction.
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The execution of INTO results in the following:

i. Flag register values are pushed on to the Stack.
ii. CS value of the return address and IP value of the return address and
iii. IP value of the return address are pushed on to the stack.
iv. IP is loaded from the contents of word location 4x4 = 00010H.
v. CS is loaded from the contents of next word location.
vi. Interrupt flag and Trap flag are reset to 0.
Thus a branch to ISS takes place. During the ISS, interrupts are disabled. At the end of ISS, there
will be an IRET instruction, returning back to the interrupted program. Instructions in the ISS
procedure perform the desired response to the error condition.
4.4 Priority of Interrupts

NMI is always serviced on top most priority. Then follows internal interrupts which result in an
error, like Divide by Zero error, as well as software interrupt instructions. The next lower priority
is assigned to INTR. And the lowest priority is assigned to single Step interrupt.
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5.0 Addressing Modes in 8086

The different ways that a processor can access data are referred to as its addressing modes. It is
the way by which the location of the operand is determined. How an operand is addressed in a
program depends on the types and location of the data. There are three general types of
addressing modes:
a) Immediate addressing modes.
b) Register addressing modes.
c) Memory addressing modes.
5.1 Immediate Addressing mode

Suppose that in a program we need to put the number 526AH in the CX register. The
MOV CX,526AH instruction can be used to do this. This instruction will put the immediate
hexadecimal number 526AH in the 16- bit CX register. This is referred to as immediate
addressing mode because the number to be loaded into the CX register will be put in two
memory locations immediately following the code for the MOV instruction. A similar
instruction, MOV CL,48H could be used to load the 8-bit immediate number 48H into the 8-bit
CL register.
It is thus possible to write instructions to load an 8-bit immediate number into an 8-bit memory
location or to load a 16-bit number into two consecutive memory locations.
5.2 Register Addressing mode

Register is the source of an operand for an instruction in Register Addressing mode. For
example, the instruction MOV CX,AX copies the contents of the 16-bit AX register into the 16-
bit CX register. Destination register is specified in the instruction before the source. When it
executes, the contents of AX are just copied to CX, not actually moved. In other words, the
previous contents of CX are written over, but the contents of AX are not changed. For example,
if CX contains 2A84H and AX contains 4971H before the execution, then after the execution of
the instruction, CX will contain 4971H and AX will still contain 4971H.
The contents of any 16-bit register can be moved into any 16-bit register, or the contents of any
8-bit register can be moved into any 8-bit register. However, an instruction of the type MOV
CX,AL cannot be used because this is an attempt to copy a byte- type operand (AL) into a word
type destination (CX). A byte in AL would fit in CX, but the 8086 would not know which half of
CX to put it in. But if the byte from AL is to be copied into the high byte of CX, the instruction
MOV CH,AL could execute it. The instruction MOV CL,AL will copy the byte from AL to CL,
the low byte of CX.
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5.3 Memory Addressing Modes

To access data in memory the 8086 must produce a 20-bit physical address. It is done by adding
a 16-bit value called the effective address to one of the four segment bases. This effective
address (EA) represents the displacement or offset of the desired operand from the segment base.
Any of the segment bases can be specified, but the data segment is the one most often used. Fig
5(a) shows a graphic form of how EA is added to the data segment base to point an operand in
the memory. Fig 5(b) shows how the 20-bit physical address is generated by the BIU. The
starting address for the data segment in fig 5(b) is 2000H so that the data segment (DS) register
will contain 2000 H. The BIU shifts the 2000H four bit positions left and adds the effective
address, 437AH, to the result. The 20-bit physical address sent out to memory by the BIU will
then be 2437AH. The physical address can be represented either as a single number, 2437AH, or
in the segment base : offset form as 2000 : 437AH.
Fig. 5
51
There are two modes of memory addressing: Direct and indirect modes.
5.3.1 Direct Addressing Mode

For the simplest memory addressing mode the effective address is just an 16-bit number written
directly in the instruction. The instruction MOV CL,[437AH] is an example. The brackets
around the 437AH are shorthand for "the contents of the memory location at a displacement from
the segment base of". Thus 437AH is the effective address or displacement/offset. When
executed, this instruction will copy the contents of the memory location, at a displacement of
437AH from the data segment base into the CL register. The actual 20-bit physical memory
address will be produced by shifting the data segment base in DS four bits left and adding the
effective address 437AH to the result, as illustrated in Fig 5(b). This addressing mode is called
direct because the displacement of the operand from the segment base is specified directly in the
instruction.
Another example of this addressing mode is the instruction MOV BX,[437AH]. When executed,
this instruction copies a word from memory into BX register. Since each memory address of the
8086 represents a byte of storage, the word must come from two memory locations. The byte at a
displacement of 437AH from the data segment base will be copied into BL. The contents of the
next higher address, displacement 437BH will be copied into BH register. The 8086 will
automatically access the required number of bytes in memory for a given instruction.
The above two examples show how direct addressing mode can be used to specify the source of
an operand. It can also be used to specify the destination of an operand. For example the
instruction MOV [437AH],BX will copy the contents of the BX register to two memory
locations in the data segment. The contents of BL will be copied to the memory location as a
displacement of 437AH and the contents of BH will be copied to the memory location at a
displacement of 437BH.
5.3.2 Indirect Addressing Mode

In the direct addressing mode, either the source or the destination operand is a specific memory
location defined by the address number or a label. For example, in the instruction MOV
BX,MEM1 the contents of the memory address labeled MEM1 is copied or moved into BX
register.
In the indirect addressing mode, the memory address is not directly given. A register is used to
indicate the address where the data can be found. Therefore, the register acts as an indirect
address to locate the data. For example, in the instruction MOV (BX),CX the source of data is
the CX register. The destination where the data are to be placed or copied to, is the address
pointed to by the BX register. The brackets ( ) around BX indicate that the BX register contains
the effective address and not a numeric value.
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6. Input/Output Concepts
6.1 The Input/Output Subsystem

The I/O Sub System is responsible for the movement of data between the basic microcomputer
system and the peripheral or external devices connected to it. It performs the same functions as a
seaport or airport for a city. Data bits are moved in and out of the I/O Sub System in the same
way as people and goods are moved in and out of the seaport or airport. The I/O sub system
exchanges data with peripheral devices through interface circuitry known as ports. The
peripheral device is physically connected to the port. The port is also physically connected to the
control circuitry as shown in fig 6.1.
Fig. 6.1
The port is the path way for data as it is transferred between the microprocessor and its
peripherals.
When the CPU performs an output instruction (I/O write cycle) the data on the bus must be
stored by the port. When an input instruction (I/O read cycle) is executed, the I/O port must gate
its data on to the data bus lines. Just as each memory location has its own (memory) address,
each I/O port has its own (port) address.
53
Peripheral devices (I/O port) may be connected to the µP using Port mapped or memory mapped
techniques.
6.1.1 Port Mapped I/O

In Port Mapped I/O, the I/O devices have a separate address space from general memory. The
separation of the I/O address space is accomplished either by an extra "I/O" pin on the CPU's
physical interface, or an entire bus dedicated to I/O. Port-mapped I/O uses a special class of CPU
instructions specifically for performing I/O. This is generally found on Intel microprocessors,
specifically the IN and OUT instructions which can read and write to an I/O device. Because the
address space for I/O is isolated from that for main memory, this is sometimes referred to as
isolated I/O. This technique is also referred to as I/O mapped I/O.
The 8086 has two I/O instructions: IN AL (or AX),port and OUT port, AL (or AX). There are
two forms of each instruction. In the direct form, IN AL (or AX), port or OUT port, AL (or AX),
the I/O port address is supplied within the instruction and restricts the access to ports with
addresses between 0 and 255. The indirect Form, IN AL ( or AX), DX and OUT DX, AL ( or
AX) uses register DX to hold the port address. This allows access to the full range of I/O ports
from 0 to 65,535.
The advantage of the indirect form is that an I/O procedure can be setup and shared between
several peripherals by passing the port address (in register DX) to the procedure.
6.1.2 Memory Mapped I/O

Memory mapped I/O uses the same address bus to address both memory and I/O devices, and
the CPU instructions used to access the memory are also used for accessing devices. In order to
accommodate the I/O devices, areas of the CPU's addressable space must be reserved for I/O.
Since I/O port is mapped to a memory address, it is accessible in software using any of the
memory read or write instructions. For example, the instruction MOV BH, MEM1 becomes an
input instruction (input the data at "port" MEM1 to register BH). Indirect I/O is also possible.
The instruction sequence can be as follows:
LEA SI,MEM1 ; Point SI at the port
MOV (SI),CX ; output CX to port
The above instructions allow CX to be output to the 16-bit port at address DS:MEM1.
54
6.1.3 Relative Merits of the Two Input Systems

The main advantage of using port-mapped I/O is on CPUs with a limited addressing capability.
Because port-mapped I/O separates I/O access from memory access, the full address space can
be used for memory. The main disadvantage is that I/O operations can slow the memory access,
if the address and data buses are shared. This is because the peripheral device is usually much
slower than main memory. In some architectures, port-mapped I/O operates via a dedicated I/O
bus, alleviating the problem.
There are two major advantages of using memory-mapped I/O. One of them is that, by
discarding the extra complexity that port I/O brings, a CPU requires less internal logic and is
thus cheaper, faster, easier to build, consumes less power and can be physically smaller. The
other advantage is that, because regular memory instructions are used to address devices, all of
the CPU's instructions and addressing modes are available for the I/O. This is compared to the
single input and output commands available with an I/O mapped port.
6.1.4 Types of Input Ports

There are two types of I/O ports; parallel and serial. Parallel port is the easiest to implement as
the microprocessor works with data in 8- or 16- bit groups. All bits comprising the data word are
input and output together in parallel.
In a serial I/O port, the data bits are lined up and transmitted in single file fashion one bit at a
time. This technique is slower than parallel port design.
55
6.2 Data Transfer Techniques

Data transfer in µP can be classified as:
 Microprocessor controlled
 Device Controlled like DMA
Microprocessor controlled data transfer can further be divided into two categories:
o Programmed I/O
o Interrupt Driven I/O
6.2.1 Programmed I/O

In programmed I/O data transfer, the program instructions control the transfer of data during the
input and output operations. The software therefore initiates, as well as controls the process of
data transfer. The hardware‘s responsibilities are confined to merely performing the necessary
operations. The appropriate device is first checked in the device interface to determine whether it
is ready. Device readiness must be tested because the CPU is much faster than peripheral
devices. The test is followed by a conditional skip instruction. If the ready flag is '1' (device
ready), the program proceeds to the next step. If the Ready Flag is '0', the program loops back to
the test instruction. The CPU, therefore, waits for a slow device by continually testing the
readiness of the device, until it reports ready. When the I/O device is ready, the data transfer
operation takes place. Immediately after the transfer of one character, the CPU reset the ready
Flag to 0. The device then sets the Flag back to 1, when it is again ready to receive the data.
Programmed data transfer has the advantage that it allows simple hardware interfaces, because
most of the management of the I/O operations is performed by software. The disadvantage of this
technique is that valuable CPU time is wasted while the CPU waits for the peripheral device to
get ready.
6.2.2 Interrupt Driven I/O

When interfacing a peripheral to a microprocessor, the microprocessor is not knowing when the
peripheral is ready. That is, the peripheral operates asynchronously with respect to the
microprocessor. One solution is to programme the CPU to repeatedly check the peripheral's
READY flag. However, this has a built-in disadvantage in that all the resources of the processor
are devoted to waiting for this flag. No other task can be performed. If the peripheral is READY
once in every 10,000 µsec, the CPU will spend most of its time idling. A more logical approach
would be to have the peripheral "tell the CPU" when it is ready. This is the purpose of the
microprocessor's interrupt input. An interrupt is used to cause a temporary halt in the execution
of a program. The microprocessor responds to the interrupt with an Interrupt Service Sub-routine
(ISS) which is a short programme or a subroutine that instructs the microprocessor on how to
handle the interrupt.
56
If we assume that 100µs is required to respond to the interrupt and supply the peripheral with
data, then in the case of a 10,000 µs per character printer, 9900 µs will be available to the
processor for its main task.
The 8086 has two interrupt pins labeled INTR and NM1. NM1 is a nonmaskable interrupt, which
means that it requires an immediate response from the processor and it cannot be blocked. INTR
is maskable via the IF flag. Only when this flag is set will interrupts on this input be accepted.
Interrupts can be generated by both hardware and software. Interrupts are also prioritized to
allow for the case when more than one are applied.
Since NMI input is nonmaskable, care must be taken when using this interrupt. This is because
there may be some programs which we do not want to interrupt- reading or writing data to a disk
drive, for example. For this reason, NMI input is normally reserved for catastrophic events like
memory error or impending power failure.
6.2.3 Direct Memory Access

DMA is a type of I/O technique in which data can be transferred between the micro computer
memory and an external device without utilizing the microprocessor. The DMA is typically used
to transfer blocks of data between the memory Subsystem and an external device. A DMA write
operation transfers data from an external device to memory.
Since the main purpose of DMA operation is to transfer data between external devices and
memory without involving the µP, another device is required. This device is called a DMA
controller. The DMA controller must be capable of performing read and write operations in the
same manner as the µP. Therefore, the DMA controller is actually a special- purpose
microprocessor whose only task is to perform high-speed data transfer between memory and an
external device. The major difference between an I/O program controlled transfer and DMA is
that data transfer does not employ the registers of the CPU.
The primary advantage of the DMA data transfer technique is that it provides an efficient
transfer of large amount of data between storage devices and the main memory without involving
the CPU.
Several DMA transfer combinations are possible.

1. Memory to peripheral.
2. Peripheral to memory.
3. Memory to memory.
4. Peripheral to peripheral
DMA request takes precedence over all other bus activities, including interrupts. In fact, no
interrupt, maskable or non-maskable, will be recognized during a DMA operation.
57
7 Intel 8086 Assembly Language Instructions

7.1 Real and Protected Modes
While the original Intel 16-bit CPUs, the 8086/8088 are no longer widely used, all later Intel
processors such as the 80386, 80486 and Pentium processors can still execute 8086 software.
The more recent CPUs can be switched by software into either the 8086-compatible ―real‖ mode
or to the ―protected‖ mode. Protected mode extends the data and address registers from 16 to 32
bits (and to 64 or 128) and includes support for memory protection and virtual memory.
Unfortunately, the details of interrupt handling in protected mode are too complex to cover in a
reasonable amount of time so we will restrict ourselves to 80x86 real-mode programming.
7.2 Overview of Registers in 8086

The 8086 includes four 16-bit data registers (AX, BX, CX and DX). These register can be used
in arithmetic or logic operations and as temporary storage. The most/least significant byte of
each register can also be addressed directly (e.g. AL is the LS byte of AX, CH is MS byte of
CX). Each register also has a special purpose:
Register Special Purpose
AX Arithmetic/Logic/IN and OUT operations
BX index register for MOVE
CX count register for string operations
DX port address for IN and OUT
There is a 16-bit program flags register. Three of the bits indicate whether the result of the most
recent arithmetic/logical instruction was zero (ZF), has a negative sign (SF), or generated a carry
or borrow (CF) from the most-significant bit. The overflow bit (OF) indicates overflow for
signed operations (a carry/borrow from the second most-significant bit). A fourth bit, the
interrupt enable bit (IF) controls whether maskable interrupt requests (on the IRQ pin) are
recognized.
The address of the next instruction to be executed is held in a 16-bit instruction pointer (IP)
register (the ―program counter‖). A 16-bit stack pointer (SP) implements a stack to support
subroutine calls and interrupts/exceptions.
There are also four segment registers (CS, DS, ES, SS) which have the base address of the code,
data and stack to be placed in any four 64 kByte ―segments‖ within the CPU‘s 1 megabyte (20-
bit) address space.
58
7.3 Instruction Set

A summary of the 8086 real-mode instruction set is attached to this document. The instructions can be
grouped into four main categories:
a) Data Transfer instructions

b) Data Manipulation instructions
c) Program Execution Transfer instructions
d) Process Control Instructions.
7.3.1 Data Transfer

Data transfer instructions include: MOV, IN, OUT, LEA, LDS, LES, PUSH, POP, XCHG,
XLAT.
The MOV instruction is used to transfer 8 and 16-bit data to and from registers. Either the source or
destination has to be a register. The other operand can come from another register, from memory, from
immediate data (a value included in the instruction) or from a memory location ―pointed at‖ by register
BX. For example, if COUNT is the label of a memory location the following are possible assembly-
language instructions:
; immediate addressing: load CX with the value 240
MOV CX,0F0H
; register addressing: move contents of BX to AX
MOV AX,BX
; direct memory addrssing: move contents of AX to memory
MOV COUNT,AX
; direct memory addressing: load CX with the value at
; address 240
MOV CX,[0F0H]
; indirect memory addressing: move contents of AL
; to memory location in BX
MOV (BX),AL
16-bit registers can be pushed (the SP is first decremented by two and then the value stored at
SP) or popped (the value is restored from the memory at SP and then SP is incremented by 2).
For example:
PUSH AX ; push contents of AX

POP BX ; restore into BX
There are some things to note about Intel assemblylanguage syntax:
 the order of the operands is destination, source — the reverse of that used on the 68000!
 semicolons begin a comment
 the suffix ‘H‘ is used to indicate a hexadecimal constant, if the constant begins with a
letter it must be prefixed with a zero to distinguish it from a label
 the suffix ‘B‘ indicates a binary constant
 square brackets indicate accesses to memory
 the size of the transfer (byte or word) is determined by the size of the destination
59
The 8086 has separate I/O and memory address spaces. Values in the I/O space are accessed with
IN and OUT instructions. The port address is loaded into DX and the data is read/written to/from
AL or AX, for example:
MOV DX,372H ; load DX with port address
OUT DX,AL ; output byte in AL to port
; 372 (hex)
IN AX,DX ; input word to AX
Load effective address instruction used to load an address pointer offset from memory into a 16-
bit register. General format:
LEA Reg16,EA
The full address in 8086 is 20-bits and thus can‘t be stored in one register (16-bits). However it
can be fetched and stored in two registers. The instruction Load register and DS (LDS) {also
referred to as Load full pointer} is used to load a full address pointer from memory into a 16-bit
register (mostly SI) and DS register. General format and operation for LDS:
LDS Reg16,EA
Meaning: (EA) → (Reg16) //word pointer offset

(EA+2) → (DS) //word pointer segment base address
The instruction Load register and ES (LES) operates the same, except it initializes ES.
Summary of operation of LEA, LDS and LES:
Exchange instruction XCHG is Used to exchange the data between two data registers or a data
register and memory. General format:
XCHG D,S
The operation swaps the content of the source and destination. Direct memory addressing is also
applicable, e.g
XCHG [SUM],BX
60
7.3.2 Data Manipulation

These include Arithmetic/Logic, shift and rotate, and string instructions (see the attached detailed
instruction set).
Arithmetic and logic instructions can be performed on byte and 16-bit values. Format examples
are:
; Add immediate operand to a value in a register or memory

ADD BX,4
; Add contents of BX to those of AX, results in AX
ADD AX,BX
;Add two registers with carry, (AX) + (BX) + (CF) → (AX)
ADC AX,BX
;Add register and memory with carry, (DS:DI) + (AX)+ (CF)→(DS:DI)
ADC [DI],AX
; Subtract an immediate operand from value in a register or memory
SUB AL,100H
;Subtract values in two registers, (AX) - (BX) → (AX)
SUB AX,BX
;Subtract value in register from value in memory,(DS:DI)-(AX) →(DS:DI)
SUB [DI],AX
; increment BX
INC BX
; compare (subtract and set flags
; but without storing result)
CMP AX,[MAX]
; mask in LS 4 bits of AL
AND AL,0FH
; set MS bit of CX
OR CX,8000H
; clear AX
XOR AX,AX
For arithmetic operations, Flags updated based on result : CF, OF, SF, ZF, AF, PF. In case of
Logic operations, Flags updated based on result are CF, OF, SF, ZF, PF while AF is undefined
Integer multiplication instructions are MUL (Multiply two unsigned byte or word operands) and
and IMUL (Multiply two signed byte or word operands). Formats:
; Multiply unsigned integer S with the value in AX, results in AX

MUL S
; Multiply signed integer S with the value in AX, results in AX
IMUL S
Operations of the multiplying instructions:

(AL) X (S8)→ (AX) // 8-bit product gives 16 bit result
(AX) X (S16) →(DX), (AX) //16-bit product gives 32 bit result
Note that:
61
 Source operand (S) can be an 8-bit or 16-bit value in a register or memory

 AX assumed to be destination for 16 bit result
 DX,AX assumed destination for 32 bit result
 Only CF and OF flags updated; others undefined
7.3.3 Program Execution Transfer instructions

Conditional jumps transfer control to another address depending on the values of the flags in the
flag register. Conditional jumps are restricted to a range of -128 to +127 bytes from the next
instruction while unconditional jumps can be to any point.
; jump if last result was zero (two values equal)

JZ skip
; jump if carry set (below)
JC neg
; jump on carry not set
JNC smaller
; unconditional jump:
JMP Label
The assembly-language equivalent of an if statement in a high-level language is a CoMPare

operation followed by a conditional jump.
The CALL and RET instructions call and return from subroutines. The processor pushes IP on
the stack during a CALL instruction and the contents of IP are popped by the RET instructions.
For example:
CALL readchar
...
readchar:
...
RET
Other Examples
1. Using JMP, Unconditional Jump. Transfers control to another part of the program. 4-byte
address may be entered in this form: 1234h:5678h, first value is a segment second value
is an offset.
Algorithm:
always jump
Example:
ORG 100h ;The code begins at offset 100h within the code segment
MOV AL, 5h
JMP label1 ; jump over 2 lines!
PRINT 'Not Jumped!'
MOV AL, 0
62
label1:
PRINT 'Got Here!'
RET
2. Using JA, Short Jump if first operand is Above second operand (as set by CMP
instruction). Unsigned.
Algorithm:
if (CF = 0) and (ZF = 0) then jump
Example:
MOV AL, 250h
CMP AL, 5h
JA label1
PRINT 'AL is not above 5'
JMP exit
label1:
PRINT 'AL is above 5'
exit:
RET
3. Using JC, Short Jump if Carry flag is set to 1.

Algorithm:
if CF = 1 then jump
Example:
MOV AL, 255h
ADD AL, 1h
JC label1
PRINT 'no carry.'
JMP exit
label1:
PRINT 'has carry.'
exit:
RET
4. In the following program, 32 8-bit numbers are stored in consecutive address with the
first number at offest address 8100H. The program counts how many of these 32 numbers
are equal to zero, and stores this count in the offset address 8200H.
Obviously this program will have to do a loop 32 times, and

each time will have to examine a number from the 32-number
array starting at address 8100H.
Two indices are set: SI to count through the number of loops, and DI to count
through the array:
63
ORG 100H
MOV CH,0
MOV SI,0
MOV DI,8100H
Label1: MOV AH,[DI]
CMP AH,0
JNE Label2
INC CH
Label2: INC SI
INC DI
CMP SI,20H
JNE Label1
MOV [8200H],CH
INT 20H
The loop is terminated when SI reaches 20H i.e. decimal 32.
7.3.4 Process Control Instructions

In addition to interrupts caused by external events (such as an IRQ signal), certain instructions
such as a dividing by zero or the INT instruction generate exceptions.
The 8086 reserves the lower 1024 bytes of memory for an interrupt vector table. There is one
4-byte vector for each of the 256 possible interrupt/ exception numbers. When an interrupt or
exception occurs, the processor: (1) clears the interrupt flag in the flags register, (2) pushes the
flags register, CS, and IP (in that order), (3) loads IP and CS (in that order) from the appropriate
interrupt vector location, and (4) transfers control to that location.
For external interrupts (IRQ or NMI) the interrupt number is read from the data bus during an
interrupt acknowledge bus cycle. For internal interrupts (e.g. INT instruction) the interrupt
number is determined from the instruction.
The INT instruction allows a program to generate any of the 256 interrupts. This ―software
interrupt‖ is typically used to access operating system services.
The CLI and STI instructions clear/set the interrupt-enable bit in the flags register to disable/
enable external interrupts.
The IRET instruction pops the IP, CS and flags register values from the stack and thus returns
control to the instruction following the one where interrupt or exception occurred.
7.4 Sample Problems

Write the following short programs based on 8086:
(a) Two 8-bit numbers which are stored in the offset addresses 1000H and 1001H are
added together. Then an OR operation is performed between the 8-bit result and an 8-
64
bit number stored in address 1002H, with the final 8-bit result being stored in the
address 1100H.
(b) Eight 16-bit numbers which are stored in successive offset addresses starting at
1200H are added together. Then an AND operation with the number 8888H is
performed on the 16-bit result and with the resulting number being stored in the offset
addresses 1400H and 1401H.
(c) A 16-bit number stored in the addresses 1200H and 1201H is subtracted from the 16-
bit number in the addresses 1300H and 1301H. Also, another 16-bit number stored in
the addresses 1400H and 1401H is subtracted from the 16-bit number in the addresses
1500H and 1501H. The results of both subtractions are added together and the final
result stored in the addresses 1600H and 1601H.
(d) The characters of the keyboard are read as they are typed and their ASCII values are
stored into the offset addresses beginning with 2000H, until a carriage return (ASCII
value ODH) is hit.
65
Intel 8086 Microprocessor Instruction Set

------------------------------------------------------
|Mnemonic |Description |
|------------------+----------------------------------
|AAA |ASCII Adjust for Add in AX |
|AAD |ASCII Adjust for Divide in AX |
|AAM |ASCII Adjust for Multiply in AX |
|AAS |ASCII Adjust for Subtract in AX |
|ADC d,s |Add with Carry |
|ADD d,s |Add |
|AND d,s |Logical AND |
|CALL a |Call |
|CBW |Convert Byte to Word in AX |
|CLC |Clear Carry |
|CLD |Clear Direction |
|CLI |Clear Interrupt |
|CMC |Complement Carry |
|CMP d,s |Compare |
|CMPS |Compare memory at SI and DI |
|CWD |Convert Word to Double in AX,DX |
|DAA |Decimal Adjust for Add in AX |
|DAS |Decimal Adjust for Subtract in AX|
|DEC d |Decrement |
|DIV s |Divide (unsigned) in AX(,DX) |
|ESC s |Escape (to external device) |
|HLT |Halt |
|IDIV s |Divide (signed) in AX(,DX) |
|IMUL s |Multiply (signed) in AX(,DX) |
|IN d,p |Input |
|INC d |Increment |
|INT |Interrupt |
|INTO |Interrupt on Overflow |
|IRET |Interrupt Return |
|JB/JNAE a |Jump on Below/Not Above or Equal |
|JBE/JNA a |Jump on Below or Equal/Not Above |
|JC/JNC a |Jump if Carry/No Carry |
|JCXZ a |Jump on CX Zero |
|JE/JZ a |Jump on Equal/Zero |
|JL/JNGE a |Jump on Less/Not Greater or Equal|
|JLE/JNG a |Jump on Less or Equal/Not Greater|
|JMP a |Unconditional Jump |
|JNB/JAE a |Jump on Not Below/Above or Equal |
|JNBE/JA a |Jump on Not Below or Equal/Above |
|JNE/JNZ a |Jump on Not Equal/Not Zero |
|JNL/JGE a |Jump on Not Less/Greater or Equal|
|JNLE/JG a |Jump on Not Less or Equal/Greater|
|JNO a |Jump on Not Overflow |
|JNP/JPO a |Jump on Not Parity/Parity Odd |
|JNS a |Jump on Not Sign |
|JO a |Jump on Overflow |
|JP/JPE a |Jump on Parity/Parity Even |
|JS a |Jump on Sign |
|LAHF |Load AH with 8080 Flags |
|LDS r,s |Load pointer to DS |
66
------------------------------------------------------
|Mnemonic |Description |
|------------------+----------------------------------
|LEA r,s |Load EA to register |
|LES r,s |Load pointer to ES |
|LOCK |Bus Lock prefix |
|LODS |Load memory at SI into AX |
|LOOP a |Loop CX times |
|LOOPNZ/LOOPNE a |Loop while Not Zero/Not Equal |
|LOOPZ/LOOPE a |Loop while Zero/Equal |
|MOV d,s |Move |
|MOVS |Move memory at SI to DI |
|MUL s |Multiply (unsigned) in AX(,DX) |
|NEG d |Negate |
|NOP |No Operation (= XCHG AX,AX) |
|NOT d |Logical NOT |
|OR d,s |Logical inclusive OR |
|OUT p,s |Output |
|POP d |Pop |
|POPF |Pop Flags |
|PUSH s |Push |
|PUSHF |Push Flags |
|RCL d,c |Rotate through Carry Left |
|RCR d,c |Rotate through Carry Right |
|REP/REPNE/REPNZ |Repeat/Repeat Not Equal/Not Zero |
|REPE/REPZ |Repeat Equal/Zero |
|RET (s) |Return from call |
|ROL d,c |Rotate Left |
|ROR d,c |Rotate Right |
|SAHF |Store AH into 8080 Flags |
|SAL/SAR d,c |Shift Arithmetic Left/Right |
|SBB d,s |Subtract with Borrow |
|SCAS |Scan memory at DI compared to AX |
|SEG r |Segment register |
|SHL d,c |Logical Shift Left |
|SHR d,c |Shift logical Right |
|STC |Set Carry |
|STD |Set Direction |
|STI |Set Interrupt |
|STOS |Store AX into memory at DI |
|SUB d,s |Subtract |
|TEST d,s |AND function to flags |
|WAIT |Wait |
|XCHG r(,d) |Exchange |
|XLAT |Translate byte to AL |
|XOR d,s |Logical Exclusive OR |
|------------------+---------+------------------------
Flags:OF - Overflow, DF - Direction, IF – Interrupt Enable, TF – Trap,

SF – Sign, ZF – Zero, AF – Auxiliary, PF – Parity, CF - Carry
Key: a – Address/Label, c – Count, d –Destination, p – Input/Output port,

r – Register, s – Source
67
Appendix
Actions in the Timing Diagrams for 8086 Microprocessor

T1 – Start of bus cycle. Actions include setting control signals to give the required values for,
M/ ALE, DT/ and putting a valid address onto the address bus. M/ goes LOW if the
Write or Read is to or from a port. The microprocessor asserts M/ HIGH if the Write or
Read is to or from memory. ALE goes HIGH to enable the address latches. The
microprocessor then sends the address it will be writing to or reading from. It then brings
ALE LOW to latch the address on the outputs of the latches. After the address information
is latched, the 8086 remove the address information from AD0-AD15, which are then used
for data. Address information is also removed from A16-A19. DT/ will be LOW when
8086 is receiving data (Reading) and HIGH when transmitting data (Writing).
T2 – The or control signals are issued, is asserted and in the case of a Write, data
is put onto the data bus. The turns on the data bus buffers to connect the CPU to the
external data bus. The READY input to the CPU is sampled at the end of T2 and if
READY is LOW, a wait state TW (one or more) is inserted before T3 begins.
T3 – This clock period is provided to allow memory/IO devices to access data for a Write cycle.
If the bus cycle is a Read cycle, the data bus is sampled at the end of T3.
T4 – All bus signals are deactivated in preparation for the next cycle. For the Write cycle, the
trailing edge of the signal transfers data to the memory or IO device which activates
the system and cause a Write when returns to logic 1 level.
68

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FEE 402: Electronics B

2. Introduction to Microcomputers and Microprocessors

A system incorporating an embedded microcomputer is referred to as an embedded system.

The fundamental difference between an embedded microcomputer and a general purpose

The microprocessor performs a large number of functions, including:

2.1.4 Bus System

The control bus consists of 4 - 10 parallel signal lines.

2.1.5 Hardware, Software, and Firmware

2.2 Microprocessor Evolution

In this course, we concentrate on the microprocessors used in microcomputers (PCs). The PC

Microprocessor Year Data/Address Internal Clock Speed

2.3 The INTEL 8086 Microprocessor

3.1 Execution Unit (EU)

3.1.1 Arithmetic Logic Unit (ALU)

3.1.2 Control Unit

3.1.3 Flag Register

 DF(direction flag). Setting DF causes string instructions to auto-decrement (count

 IF ( interrupt-enable flag) Setting IF allows the µP to recognize external (maskable)

3.1.4 General Registers

(a) Data Registers

(b) The pointer and index registers

Other pointer and Index Registers

3.2 Bus Interface Unit (BIU)

3.2.1 Instruction Queue

3.2.2 Address control

3.3 Clock, Bus and Instruction Cycles

3.4 8086 Pin Diagram

3.4.1 Microprocessor modes of operation

3.4.2 Common Pin Descriptions

AD0 - AD15 Address Data

A19/S6, A18/S5, A17/S4, A16/S3 (0): Address/Status

S3 & S4: Lines are decoded as follows:

A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

BHE /S7 (O): Bus High Enable/Status

INTR (I): Interrupt Request

NMI (I): Non-Maskable Interrupt

CPU component Contents

Instruction Pointer 0000H

Table – 3.2 System Registers after Reset

CLK (I): Clock

MN/ MX (I): Maximum / Minimum

3.4.3 Minimum Mode Pins

M/ IO (O): Status line

INTA (O): Interrupt Acknowledge

ALE (O): Address Latch Enable

DT/ R (O): DATA Transmit/Receive

DEN (O): Data Enable

HOLD & HLDA (I/O): Hold and Hold Acknowledge

3.4.4 Maximum Mode Pins

S2, S1, S0 (O): Status Pins

0 0 1 Read I/O port

0 1 0 Write I/O port

QS0, QS1 (O): Queue – Status

0 1 First byte of opcode from queue

1 0 Empty the queue