Total No. of Questions : 8] SEAT No.

8
23
P9134 [Total No. of Pages : 2

ic-
[6179]-260

tat
S.E. (Information Technology Engg.)

4s
LDCO : LOGIC DESIGN & COMPUTER ORGANIZATION

0:2
02 91
9:4
(2019 Pattern) (Semester - III) (214442)

0
30
9/1 13
Time : 2½ Hours] [Max. Marks : 70
0
2/2
Instructions to the candidates:
.23 GP

1) Answer Q1 or Q2, Q3 or Q4, Q5 or Q6, Q7 or Q8.

E

2) Neat diagrams must be drawn wherever necessary.

82

8
C

23
3) Figures to the right indicate full marks.

ic-
16

tat
8.2

4s
Q1) a) Differentiate between Combinational circuit & Sequential circuits? [6]
.24

0:2
91
49

9:4
b) Design flip flop conversion logic to convert J-K flip flop to T flip-flop?[6]
30
30

c) Design and draw MOD 96 Counter using IC 7490 & explain its operations?[6]
01
02
2/2
GP

OR
9/1
CE

Q2) a) Compare Asynchronous counters with Synchronous counters? [6]

82

8
23
.23

b) Design flip flop conversion logic to convert S-R Flip Flop to a J-K Flip-
ic-
16

Flop? [6]
tat
8.2

4s

c) Explain the working of 3-bit synchronous counter using J-K flip flop
.24

0:2
91

with suitable circuit diagram and state table? [6]

49

9:4
30
30
01
02

Q3) a) Describe with neat diagram Von Neumann Architecture of computer? [6]
2/2
GP
9/1

b) Write a note on multiple bus hierarchies? [5]

CE
82

c) Explain how system bus organization is used for communication between

.23

the major components of a computer with neat diagram? [6]

16
8.2

OR
.24

P.T.O.
49
Q4) a) Describe with neat diagram Harvard Architecture of computer? [6]

8
23
b) Which are the types of ALU? Explain the operations of ALU by using

ic-
various control signal? [5]

tat
4s
c) Explain the Control unit Implementation using Micro-programmed

0:2
Implementation? [6]

02 91
9:4
0
30
Q5) a) 9/1 13
Describe instructions with 0, 1, 2 or 3 addresses using suitable example.[6]
0
2/2
b) Differentiate between RISC & CISC Architecture. [6]
.23 GP

c) Define and explain with suitable diagram and example Instruction Pipelining
E
82

8
Architecture of processor. [6]
C

23
ic-
OR
16

tat
Q6) a) Describe cluster computer architecture with neat diagram. [6]
8.2

4s
.24

0:2
b) What is SMP? Draw suitable diagram of SMP & explain briefly. [6]
91
49

9:4
c) Explain interrupt handling process using IVT and ISR. [6]
30
30
01
02
2/2

Q7) a) Write short note on : [8]

GP
9/1

i) EPROM
CE
82

8
23
ii) EEPROM
.23

ic-
16

b) What is cache coherency problem? Explain four different approaches to

tat
8.2

4s

prevent cache coherence problem. [9]

.24

0:2

OR
91
49

9:4

Q8) a) Explain cache memory operation using multilevel cache organization.[8]

30
30
01

b) Explain with neat diagram Signals used to Connect Memory to Processor.[9]

02
2/2
GP
9/1


CE
82
.23
16
8.2
.24

[6179]-260
49