Proceedings of the IEEE 2017 International Conference on Computing Methodologies and Communication

(ICCMC)

Scan Methodology and ATPG DFT Techniques at

Lower Technology Node
Ms. Janki Chauhan, Project Trainee, DFT, ASIC Department,VLSI,India
Parul University,P.O.Limda,Ta.Waghodia,Vadodara,India
Mr. Chintan Panchal, Technical Manager eInfochips pvt.ltd.,Ahmedabad,India
Prof. Haresh Suthar,(HOD)E.C. Department, Parul Institute of Technology,Vadodara,India
Email: jankinchauhan@gmail.com*

Abstract—As VLSI Technology is continuously shrinking to Yield (Y)= Number of good Chips fabricated/Number of
lower technology nodes, we need efficient techniques for testing total Chips fabricated.
on lower nodes because as Design Complexity grows, there are
numbers of challenges including higher test cost, higher power
consumption, test time, area, pin count and new defects at Let’s start with the ASIC flow which is shown in below
small geometries(variation in transistor’s channel length, W/L figure 1.In Which First of all we should have the specifica-
ratio, threshold voltage).Reliability and testability both are the tions of our design after that RTL code is written and then
important parameters in today’s VLSI design. We use design for the synthesis process is there .In this process the RTL code is
testability for this purpose. Scan is the first step for inserting converted into the gate level netlist. On this netlist functional
DFT(design for testability) architecture in any chip. Thus scan verification is done.
insertion improves the controllability and observability of the
sequentially flops. After that pattern generation step is there
which is generated by ATPG (Automatic test pattern generation)
Tool and finally pattern simulation will give results in terms of
pass/fail patterns. The purpose of this paper is to implement
scan insertion flow architecture on lower technology nodes and
detect the targeted faults through the pattern generation by
ATPG which will improve the yield on SOC by fault detection
using some EDA tools. It also includes the optimization of the
most important test parameters related to testability.

Keywords—Design for testability, Scan insertion, DRC, ATPG,

Lower technology node

I. I NTRODUCTION

As per the Moore’s low, transistor’s count is doubled at

every 18th month and due to this we are basically moving
toward the lower technology nodes.
At the lower technology nodes, advantage is the speed
improvement but on other side the disadvantage is that the
cost increases as well as the run time increases and yield
decreases. So basically defect density is sharply added at
lower technology nodes with respect to the transistor density
(performance) and it is a big concern for DFT in our ASIC
flow [6]. Due to these factors, new fault models and scan
techniques have to be introduced to ensure high quality design
[11].
Due to the down scaling of future size ,it is very important Figure 1: DFT in ASIC Flow
to detect the timing related defects causes delay faults like
transition fault and path delay fault.They can only be detected
when testing frequency is same as functional frequency. This
type of testing of design is called At-Speed testing [3].
In scan design we convert the normal flip-flops of design Finally DFT is there which includes scan insertion ,ATPG
into scanable flip-flops. The scan insertion should not result & pattern simulation steps. After that Physical design flow is
in a very large area, power or performance overhead [14].It there for placement and routing which is performed by the
should result in higher yield. physical design engineer team.

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 Proceedings of the IEEE 2017 International Conference on Computing Methodologies and Communication
(ICCMC)

A. Why DFT is necessary? 1) Stuck at fault models

• Single stuck at faults
DFT includes the techniques to add extra logic with • Multiple stuck at faults
awareness of power, area and performance of the circuit
2) Transition faults
to detect the manufacturing faults which arrived due to the
3) Path delay faults
manufacturing defects. The main aim of DFT (Design for
4) IDDQ faults
Testability) is to add controllability and Observability in the
5) Transistor faults
design to make design testable.
• Stuck at short fault
Currently, IC manufacturing process is inherently defective, • Stuck at open fault
but must still provide high quality ICs which are Testable,
Reliable and provide high Performance. With increasing the
number of transistors in a chip and decreasing the chip size, II. P ROBLEM D EFINITION
Reliability is main concern in today’s design [18].
A. DFT Challenges on lower technology nodes
Devices are mainly failed due the manufacturing problems
[10] like Insufficient doping, process variations including As shown in the figure 3, with continuous decrease in the
Gate oxide breakdown, material defects, missing contact win- technology node number of challenges increases that is the
dows, Contact degradation etc. These manufacturing defects reason, efficient techniques [15] needs to be used to achieve
are express in the following three terms which are correlated desired range of the test parameters.
to each other.
• Test time : Nowadays, defect density has rapidly in-
Defect: It can result in shorts to power/ground, slow creased on a lower nodes. To target the detectable
transistors etc. due to the process variations. faults from the design in a least amount of time, makes
task critical for DFT engineer because, there are some
Fault: A representation/modeling of that defect.
limitations of the tester [9].
Error: A wrong output signal produced by a defective
system.

Figure 2: Defect and Fault representation

Here, as shown in Figure 2, during manufacturing due to

some process defects, A in permanently shorted to VDD, this
is modeled to stuck-at 1 fault model. Here, Defect is short
with VDD, Fault is stuck-at 1 and Error is when A = 0 and
B = 1 output =1.
Hence we must test these chips before they go on some
board. Because if chip is malfunctioned then it will result in
to the malfunctioning of whole board. DFT fulfills this aim
by adding extra logic. The logic added makes manufacturing
test process faster. Hence time to market of the chip is
reduced. DFT process with care makes manufacturing test
cost effective.
B. Fault models
Fault modeling is nothing but translation of physical
defect into a mathematical construct that can be operated by
specific algorithm [4].
Most commonly supported fault model in to the modern
VLSI are shown below:
Figure 3: Silicon complexity on lower nodes [8]
• Pattern count : Mostly Pattern count is increases with
respect to the no. of targeted faults in the design. Re-
duction in pattern count [13] is very important because
memory size and pin count is limited on tester. It also
affects the test time.
• Test coverage : Test coverage is nothing but the ratio
of detected faults to the total no. of detectable faults in
our design.
• Power consumption : Power consumption during the
test is one of the major factors affecting yield and
introduces failures [12]. For reducing test time,there
is a tedency to test maximum part of the chip in the
least amount of time.Thus the switching during test is

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generally more than the functional [17] [16]. Hence

during the testing maximum heat dissipated because of
the switching which may burn the chip [19].
• Pin count : Due to continuous reduction in transistor
geometries [6], the available pin count for testing
keeps on reducing(Due to small package size) which
places serious problems on semiconductor companies
to perform DFT. Figure 4: Scan Operation [2]
• Area : Basically we add some extra logic and define
the DFT architecture to test our design. So ,area (Gate
count)is also increases which is a big concern for ASIC. When the SE is low data at the D input will be selected and
DFT area should not be more than the 5% of the actual thus fed to the flip flop. On the contrary for SE=1, data at
area. the SI input is selected and fed to the flip flop. Thus we can
achieve controllability through the SI data.

III. EDA TOOLS AVAILABLE FOR SCAN & ATPG

B. Pre-requisite
There are different tools available for DFT(Design for test)
techniques in the semiconductor market which is shown in Here is the case study on scan insertion using Incen-
below table I. tia’s Testcraft tool. Inputs and Outputs of Testcraft tool are
mentioned in Figure 6. Basically Incentia product offering
Logic, Low power, DFT synthesis solution by offering De-
Table I: Diffèrent tools for the scan insertion and ATPG
signcraft,Testcraft and Powercraft features [7].
Semiconductor
Scan Insertion ATPG a) Design Database: Design on which scan insertion,
Vendor
Synopsys DFT Compiler Tetramax ATPG and pattern simulation are performed, is one CPU
Mentor graphics Tessent Scan Fastscan
Cadence RC compiler Encounter test
design.
Incentia Designcraft - Table II describes the specifications of the design.

IV. S CAN I NSERTION Table II: Design database

Project,ID : ABCDE**
In scan based design ,all the cells are converted to scan Sr.No. Specifications Value Information
Functional Provided
cells. These scan cell designs are mainly divided in to the 1
Frequency
1GHz
by semiconductor vendor
three types as shown below: Test Decided
2 10MHz
Frequency as per the tester requirement
1) Muxed-D scan cell Technology
3 28nm -
(nm)
2) Clocked scan cell Standard cell library which is
4 Library(.db) -
3) LSSD (Level Sensitive Scan Design) provided by semiconductor vendor

b) Design Diagram: Figure 5 shows the overview of the

A. Scan Operation scan inserted design and there are total 6 memory modules.
As memories are tested using the MBIST logic,memory
Scan test is a well-known and often-used design-for testa- modules are taken as black-box.
bility technique.Basically Scan cell is composed of a D f/f
and multiplexer. In this scan operation, basically sequential
flip-flop’s are converted in to the scan flip-flop’s which is
shown in figure 4. It has two modes

1) Normal mode
2) Test mode

Pins required for scan operation are listed below :

1) SE (Scan Enable)
2) SI (Scan Input)
3) TM (Test Mode) -This pin is used when extra test-
points are added Figure 5: Block diagram of ABCDE** design
4) SO (Scan out) - This pin is shared with Q of DFF

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c) Incentia Scan Insertion Flow: Basically Incentia tool
imports the required gate level netlist and appropriate libraries
from the vendor side. After giving the proper inputs, design
related constraints(timing, power, delay time) need to be
provided. Before defining the scan architecture, DRCs(design
rule check) need to be solved [20]. After the preview of
the Scan Design, Scan chain will be stitched. Finally the
tool gives major two outputs: scan inserted netlist and spf
file(procedure file).
Figure 6: Incentia Scan Insertion flow
d) Violations Observed: Here is the list of some basic
DRCs which are faced during scan insertion.
1) violation: uncontrolled clock violation
Enable pin of clock gater is controlled by functional
logic.
Solution :
Basically one AND gate need to be added before the
clock gater for controlling purpose. One input of the
AND gate is Scan Enable pin and another pin will be
SCANTEST pin which is shown below.
Figure 7: Uncontrolled Clock Violation
2) violation: uncontrolled Set/Reset violation
Solution :
These rule can be solved by the same method as above
rule was solved.Instead of AND gate, Multiplexer can
also be used for controlling purpose
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(ICCMC)
V. PATTERN G ENERATION
ATPG is the abbreviation for Automatic Test Pattern
Generation. This is EDA technique, which enables ATE
to distinguish between correct and faulty circuit behavior.
Generated patterns are then used to test semiconductor device
after manufacturing. ATPG reduces test pattern generation
time.There are so many EDA tools available for ATPG.
A. Why we perform ATPG
Let’s take one example, here input A is stuck at 1 in
AND gate. To detect this fault we must test the gate with
appropriate test vector.
Figure 8: Stuck at 1 fault
Table III shows faulty operation of this AND gate. Here
in 2nd row, expected output was 0 but due to stuck-at 1 fault
it generated 1. Hence to detect stuck at 1 fault at node ‘A’
we must apply A=0 and B=1. (A, B) = (0,1) is test vector
for stuck at 1 fault at A. Same way stuck at 0 and stuck at
1 fault can occur at all the nodes possible. Hence total 6
faults are there, but in practical circuit so many nodes are
there and all are assumed to be fault sensitive. We must
generate test vector for all the nodes. That is why we need
ATPG. Depending upon some algorithm EDA tool generates
all the patterns. Manual test vector/test pattern generation is
not possible for higher number of nodes; hence we need to
do this with ATPG process.
A B OUT
0 0 0
0 1 1
1 0 0
1 1 1
Table III: Test vectors for stuck at 1 fault in AND gate
B. ATPG Pre Requisite
Here is the example of the ATPG pattern generation using
the Mentor Graphics’ FastScan Tool. As for the Scan inser-
tion, Incentia TestCraft tool is used, some steps are required
to do before starting the ATPG process with FastScan figure
19.
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 Proceedings of the IEEE 2017 International Conference on Computing Methodologies and Communication
Figure 9: Scan to ATPG Flow
Fastscan have the most important feature to reduces run
time with no effect on coverage or pattern count using
distributed ATPG [5].In Fastscan, there are two mode for
pattern generation where in tetramax there are total 3 modes
for pattern generation.This two modes are expressed as setup
mode & system mode in which we have to perform some
necessary steps through scripting which is shown in figure
20.
Figure 10: Fastscan ATPG flow
C. Violations Observed
1) Issue 1
As shown in figure 21, if source and sink are clocked
by the same clock and the sink captures data from the
source, a potential exists for the captured data to pass
through both the source and sink in the same clock
cycle. That is, the sink might capture the source’s
new data instead of the source’s old data.
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Figure 11: Clock Rule -1
Solution:
The preferred method is to enable the
set_split_capture_cycle command which enables
the simulation of level-sensitive and leading edge
state elements updating as a result of applied clocks.
When set to on, the tool updates simulation data
between clock edges. This “split capture cycling”
of data allows the tool to determine correct capture
values.
2) Issue 2
As shown in figure 22, let’s take DFF1 updates on
the leading edge of the clock, while DFF2 updates on
the clock’s trailing edge due to the gating of the CLK
signal with the output of DFF1. Notice that the old
value of DFF1/q disables the clock input to DFF2.
The tool’s default simulation will therefore predict
there will be no clock pulse to DFF2 and that it will
hold its state as a result.
Figure 12: Clock Rule -2
Solution:
The preferred method is to enable the
set_split_capture_cycle command enables the
simulation of level-sensitive and leading edge
state elements updating as a result of applied clocks.
When set to on, the tool updates simulation data
between clock edges
VI. PATTERN S IMULATION
Pattern simulation consists of generating a test bench to
simulate the patterns around our design. Thus there are four
essential inputs to pattern simulation, i.e. patterns, testbench,
netlist and libraries [1]. In case of a mismatch the patterns
simulation tool will show the failing cycle as well as the type
of mismatch i.e. zero-one or x mismatch.
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(ICCMC)

VII. R ESULTS pattern generation have done through at speed testing in which
it have required two test vectors like one for launch & another
A. Scan Insertion Report Statistics one for capture to detect the targeted delay faults from the
design.
Here in the table IV, the measurable things is that the total That’s why in transition test pattern generation ,it is necessary
gate count is increased after the DFT insertion as well as to modify our spf(STIL procedure file)file in which whole test
leakage power is also increased.So, area overhead is also a procedure is changed.
big concern for DFT.

Table VI: Transition Report Statistics

Table IV: Report Statistics after Scan Insertion
Test coverage 94.72%
Project ID : ABCDEF Pattern count 6243
Pre -DFT Total Gate Count 1434182 Test time(s) 6369.3
Combinational Gate Count 533192
Logic Gate Count 706542
Total Leakage power(pW) 38154239107.66
Post - DFT Total Gate Count 1434225 VIII. C ONCLUSION & F UTURE W ORK
Combinational Gate Count 533236
Logic Gate Count 706585 From the analysis,this paper conclude that a number of
Total Leakage power(pW) 38154286974.08
Scan Input 204 challenges arrive at lower technology nodes for scan insertion
Scan Output 204 and ATPG techniques. These include power dissipation, test
Total Scan Chain 204 cost and yield loss due to the process variations in the newer
Scan chain length 110
Total Sequential cell 22390 semiconductor devices. Fault caused by a timing or power
issue during scan testing might never occur during functional
mode of operation and would introduce unnecessary yield loss
,This is a big concern for industry. Also need to solve some
B. ATPG Reports
DRCs which arrived at Scan and ATPG process will assure
that design is ready for further process or not.
Table V: Stuck at Report Statistics This paper includes Scan insertion and ATPG flow with
improvement in most affected test parameters through some
Iteration Test coverage Pattern count Test time(s) Technique efficient technique like ECO and fault grading on 28nm
1 96.74% 2299 518 - technology node files and generated test vectors for both
2 99.47% 3584 750.7 ECO
3 99.49% 906 156.8 Fault Grading stuck at and transition faults. For any design, most important
parameter is the appropriate test coverage because it may
result in unnecessary yield loss and pattern count is also
a) Stuck at Result: Here table V shows that how the test important because at ATE(Automatic test equipment)side
parameters have improved through some efficient techniques. memory is limited. As we moving to lower technology nodes
In which the initial test coverage is 96.74% due to the the ,we have to phase more challenges to insert DFT in any
observability missing at memory modules like assuming some design.
logic is preceding memory modules in which due to bypassed
memory modules it didn’t get observability and after memory
IX. ACKNOWLEDGMENT
modules there was a X value is propogating through whole
path. That’s why in 2nd iteration, ECO(Engineering change The Author would like to thank the reviewers for their
order) was performed and added a mux in between the same. constructive and helpful comments.

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[ ]Janki Chauhan received the Bachelor of

Engineering degree in Electronics and communication en-
gineering from the Parul Institute of Technology in 2013
and currently pursuing the Master of Engineering degree in
VLSI Design & Embedded System from Parul University
,2017.Carrying out Internship in Design For Test at eInfochips
pvt. ltd., Ahmedabad.

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