Ruchika Shukla

Total Experience 5.6 Years

Designation Lead Engineer – Design Verification
Qualification Bachelors’ Degree in Electronics and Telecommunication with 8.04 CGPA from
Rashtrasant Tukadoji Maharaj Nagpur University, 2017.
Executive Summary Having 5.6 years of experience in SOC and IP level Verification:
• Worked on C based test environment with ARM processor.
• Good Knowledge of developing verification environment, test cases.
• Worked on various serial protocols like I2C, I3C.
• Worked in SoC verification for PCIe.
• Developing and debugging assertions in test chip project
• Good analysis, debug and problem-solving skills and be self-driven.
Technical Skills • HVL / HDL: System Verilog, Verilog
• Methodology: UVM
• Programming Language: C, C++
• Scripting Language: Perl, TCL
• EDA Tools: Cadence Xrun, Questasim and Modelsim.

KEY PROJECTS
Project 1: ITP IP [April 2023 – Present]
Integrated Timer and PWM IP with capture capability. It generates the PWM waves at
Description
output and compare two different PWM waves.
Language UVM
Roles and • To go through the specification and come up with test plan and coverage bins.
Responsibilities • Set up the ENV for IP.
Project 2: ICF IP [March 2023 – April 2023]
It’s an Interconnect Fabric which defines an on-chip communications standard between
Description high-performance embedded microcontrollers and their typically associated
components.
Language UVM
Roles and • Worked on different testcase failures.
Responsibilities • Fixed some ENV issue.

Project 3: DMA IP [March 2023 – March 2023]

Direct memory access allows devices to transfer data without subjecting the processor a
Description
heavy overhead.
Language UVM
Roles and • Write one testcase for delay response from slave.
Responsibilities • Created common Interrupt agent.
Project 4: Test Chip [July 2022 – Jan 2023]
Description We are working on PCIE 8 lane PHY connection in test chip.
Language SVA
Roles and • Debugging register testcase
• Writing simple assertion for reset
Responsibilities
• Debugging regression failures
Project 5: Peripheral Component Interconnect Express [Dec 2021 - Jun 22]
Peripheral Component Interconnect Express (PCIe or PCI-E) is a serial expansion bus
Description
standard for connecting a computer to one or more peripheral devices.
Language C based test ENV with ARM processor.

Confidential – Signoff Semiconductors Pvt Ltd.

 • Verification of connections between 4 Pcie in SOC with help of external PHY
Roles and loopback
Responsibilities • Implementation of testcase
• Debugging in RTL and Gate level Simulation
Project 6: Universal Serial Bus [Feb 2020 – June 2022]
A Universal Serial Bus (USB) is a common interface that enables communication
Description
between devices and a host controller such as a personal computer (PC) or smartphone.
Language C based test env with ARM processor
• Identify test case scenarios and create test plan for block level verification.
Roles and
• Implementation of test cases
Responsibilities
• Regression simulations and debugging
Project 7: MCAN [Oct 2019 – June 2022]
A Controller Area Network (CAN bus) is a robust vehicle bus standard designed to allow
Description microcontrollers and devices to communicate with each other's applications without a
host computer.
• Identify test case scenarios and protocol.
Roles and
Responsibilities • Implementation and debugging of test cases for MCAN device features.
Regression simulations and debugging.
Project 8: I3C [Sep 2018 – Aug 2021]
MIPI I3C is a specification to enable communication between computer chips by
Description
defining the electrical connection between the chips and signaling patterns to be used.
• Identify test case scenarios and create a test plan.
Roles and
• Implementation of test cases
Responsibilities
• Regression simulations and debugging
Project 9: I2C [Nov 2018 – Aug 2021]
I2C stands for the inter-integrated controller. This is a serial communication protocol
Description that can connect low-speed devices. It is a master-slave communication in which we can
connect and control multiple slaves from a single master.
• Identify test case scenarios and create a test plan.
Roles and
• Implementation of test cases
Responsibilities
• Regression simulations and debugging
Project 10: RTI Timer [July 2018 – June 2022]
Real Time timer used to give reset or interrupt depends on configuration when
Description
processor is got hang.
• Understanding of Spec. and existing env (DMSC subsystem)
Roles and
• Based on new features, identify DV efforts
Responsibilities
• Regression simulations and debugging

Confidential – Signoff Semiconductors Pvt Ltd.