a small blue box around it and produce a dialog box for the change.

For the source, a dia- DD AA

log box labeled DC_POWER will result, in which the heading Label is selected and the
refDEs retyped as E. Click OK and the label E will appear. The same procedure can change
the value to 20 V, although in this case the Value heading is chosen and the units are chosen
using the scroll at the right of the entered value.
The next step is to determine what quantities are to be measured and how to measure
them. For this network a multimeter will be used to measure the current through the resistor
R1. The multimeter is found at the top of the Instrument toolbar. After selection it can be
placed on the screen in the same manner as the other elements. Double-clicking the meter
will then result in the Multimeter-XXM1 dialog box, in which A is selected to set the mul-
timeter as an ammeter. In addition, the DC box (a straight line) must be selected because
we are dealing with dc voltages. The current through the diode D1 and the voltage across
the resistor R2 will be found using Indicators, which are found as the tenth option to the
right on the Component toolbar. The software symbol looks like an LED with a red dashed
figure eight inside. Click on this option and a Select a Component dialog box will appear.
Under Family, select AMMETER and then take note of the Component listing and the
four options for the orientation of the indicator. For our analysis the AMMETER_H will
be chosen since the plus sign or entering point for the current is on the left for the diode
D1. Click OK and the indicator can be placed to the left of the diode D1. For the voltage
across the resistor R2, the option VOLTMETER_HR is chosen so the polarity matches
that across the resistor.
Finally, all the components and meters must be connected. This is accomplished by
simply placing the cursor at the end of an element until a small circle and a set of crosshairs
appear to designate the starting point. Once these are in place, click the location and an x
will appear at the terminal. Then move to the end of the other element and left-click the
mouse again—a red connecting wire will automatically appear with the most direct route
between the two elements. The process is called Automatic Wiring.
Now that all the components are in place it is time to initiate the analysis of the circuit,
an operation that can be performed in one of three ways. One option is to select Simulate
at the head of the screen followed by Run. The next is the green arrow in the Simulation
toolbar. The last is to simply toggle the switch at the head of the screen to the 1 position. In
each case a solution appears in the indicators after a few seconds that seems to flicker over
time. This flickering simply indicates the software package is repeating the analysis over
time. To accept the solution and stop the continuing simulation, either toggle the switch to
the 0 position or select the lightning bolt keypad again.
The current through the diode is 3.349 mA, which compares well with the 3.32 mA in
Example 13. The voltage across the resistor R2 is 18.722 V, which is close to the 18.6 V
of the same example. After the simulation, the multimeter can be displayed as shown in
Fig. 151 by double-clicking on the meter symbol. By clicking anywhere on the meter, the
top portion is dark blue, and the meter can be moved to any location by simply clicking on
the blue region and dragging it to the desired location. The current of 193.285 mA is very
close to the 212 mA of Example 13. The differences are primarily due to the fact that each
diode voltage is assumed to be 0.7 V, whereas in fact it is different for each diode of Fig.
151 since the current through each is different. In all, however, the Multisim solution is a
very close match with the approximate solution of Example 13.

OLM
l
*Note: Asterisks indicate more difficult problems.
2 Load-Line nalysis
1. a. Using the characteristics of Fig. 152b, determine ID, VD, and VR for the circuit of Fig. 152a.
b. Repeat part (a) using the approximate model for the diode, and compare results.
c. Repeat part (a) using the ideal model for the diode, and compare results.
2. a. Using the characteristics of Fig. 152b, determine ID and VD for the circuit of Fig. 153.
b. Repeat part (a) with R = 0.47 k.
c. Repeat part (a) with R = 0.68 k.
d. Is the level of VD relatively close to 0.7 V in each case?
How do the resulting levels of ID compare? Comment accordingly.

121
 DD AA + VD –
Si

ID
+
+
E 12 V R 0.75 k VR
–
–

(a)

ID (mA)

30

25

20

15

10

0 1 2 3 4 5 6 7 8 9 10 11 12 VD (V)
0.7 V

(b)

F. 152
Problems 1 and 2.

3. Determine the value of R for the circuit of Fig. 153 that will result in a diode current of
10 mA if E 5 7 V. Use the characteristics of Fig. 152b for the diode.
4. a. Using the approximate characteristics for the Si diode, determine VD, ID, and VR for the
circuit of Fig. 154.
b. Perform the same analysis as part (a) using the ideal model for the diode.
c. Do the results obtained in parts (a) and (b) suggest that the ideal model can provide a good
approximation for the actual response under some conditions?

+ VD –
+ VD –
ID Si
ID Si + +
+ +
E 30 V R 1.5 k VR
E 6V R 0.2 k VR –
– – –

F. 153 F. 154

Problems 2 and 3. Problem 4.

122
3 eries iode Configurations DD AA
5. Determine the current I for each of the configurations of Fig. 155 using the approximate equiv-
alent model for the diode.

–
+
I
+ –

(a)

(b) (c)

F. 155
Problem 5.

6. Determine Vo and ID for the networks of Fig. 156.

ID

Vo Vo

ID

–6 V
(a) (b)

F. 156
Problems 6 and 49.

*7. Determine the level of Vo for each network of Fig. 157.

12 V

10 k

10 V

(a) (b)

F. 157
Problem 7.

*8. Determine Vo and ID for the networks of Fig. 158.

Vo

2.2 k
–20 V

(a) (b)

F. 158
Problem 8.

123
 DD AA *9. Determine Vo1 and Vo2 for the networks of Fig. 159.

GaAs kΩ

(a) (b)

F. 159
Problem 9.

4 arallel and eries–arallel Configurations

10. Determine Vo and ID for the networks of Fig. 160.

20 V

12 V
Ge

GaAs

4V
(a) (b)

F. 160
Problems 10 and 50.

*11. Determine Vo and I for the networks of Fig. 161.

1V

GaAs

–4 V
(a) (b)

F. 161
Problem 11.

12. Determine Vo1, Vo2, and I for the network of Fig. 162.
*13. Determine Vo and ID for the network of Fig. 163.

124
 DD AA

+
Si
– GaAs

F. 162 F. 163

Problem 12. Problems 13 and 51.

5 /O ates
14. Determine Vo for the network of Fig. 39 with 0 V on both inputs.
15. Determine Vo for the network of Fig. 39 with 10 V on both inputs.
16. Determine Vo for the network of Fig. 42 with 0 V on both inputs.
17. Determine Vo for the network of Fig. 42 with 10 V on both inputs.
18. Determine Vo for the negative logic OR gate of Fig. 164.
19. Determine Vo for the negative logic AND gate of Fig. 165.

–5 V –5 V

Si Si

0V 0V
Vo Vo
Si Si

1 kΩ 2.2 kΩ

–5 V

F. 164 F. 165

Problem 18. Problem 19.

20. Determine the level of Vo for the gate of Fig. 166.

21. Determine Vo for the configuration of Fig. 167.

F. 166 F. 167

Problem 20. Problem 21.

6 inusoidal nputs; alf-Wave ectification

22. Assuming an ideal diode, sketch vi, vd, and id for the half-wave rectifier of Fig. 168. The input
is a sinusoidal waveform with a frequency of 60 Hz. Determine the profit value of vi from the
given dc level.
23. Repeat Problem 22 with a silicon diode (VK 5 0.7 V).
24. Repeat Problem 22 with a 10 k load applied as shown in Fig. 169. Sketch vL and iL.

125
 DD AA id + vd – Vdc = 2 V
Ideal
Ideal vi iL
Vdc = 2 V
+ + vd
– id +
vi 2 kΩ 2 k RL 10 k vL
– –

F. 168 F. 169

Problems 22 through 24. Problem 24.

25. For the network of Fig. 170, sketch vo and determine Vdc.
*26. For the network of Fig. 171, sketch vo and iR.

vi iR
2k
10 V
1 kΩ
+ +
2 0 t vi Si 1 kΩ vo

–10 V – –

F. 170 F. 171

Problem 25. Problem 26.

*27. a. Given Pmax = 14 mW for each diode at Fig. 172, determine the maximum current rating of
each diode (using the approximate equivalent model).
b. Determine Imax for the parallel diodes.
c. Determine the current through each diode at Vimax using the results of part (b).
d. If only one diode were present, which would be the expected result?

vi Imax
Si
160 V
+
0 t vi Si 4.7 kΩ 68 kΩ

F. 172
Problem 27.

7 ull-Wave ectification
28. A full-wave bridge rectifier with a 120-V rms sinusoidal input has a load resistor of 1 k.
a. If silicon diodes are employed, what is the dc voltage available at the load?
b. Determine the required PIV rating of each diode.
c. Find the maximum current through each diode during conduction.
d. What is the required power rating of each diode?
29. Determine vo and the required PIV rating of each diode for the configuration of Fig. 173. In
addition, determine the maximum current through each diode.

vi
+
100 V

vi Ideal diodes vo
t +
–100 V
2.2 kΩ
–
–

F. 173
Problem 29.

126
*30. Sketch vo for the network of Fig. 174 and determine the dc voltage available. DD AA

vi
+
100 V
Ideal diodes
vi vo
t +
–100 V
2.2 kΩ 2.2 kΩ 2.2 kΩ
–
–

F. 174
Problem 30.

*31. Sketch vo for the network of Fig. 175 and determine the dc voltage available.

vi
+
170 V Ideal 2.2 kΩ
diodes
– vo +
vi
t
2.2 kΩ
–170 V
2.2 kΩ
–

F. 175
Problem 31.

8 Clippers
32. Determine vo for each network of Fig. 176 for the input shown.

8V

+ –
100 kΩ 2 kΩ

F. 176
Problem 32.

33. Determine vo for each network of Fig. 177 for the input shown.

4V
12 V vo
vo
– +

1.8 kΩ 10 kΩ

–12 V
(a) (b)

F. 177
Problem 33.

127
 DD AA *34. Determine vo for each network of Fig. 178 for the input shown.

– 4 V + Ideal
+ +
vi 1 kΩ vo

– –

(a) (b)

F. 178
Problem 34.

*35. Determine vo for each network of Fig. 179 for the input shown.

3V
1 kΩ
+ –
Si
+
4V
–

(a) (b)

F. 179
Problem 35.

36. Sketch iR and vo for the network of Fig. 180 for the input shown.

+ –
5.3 V 7.3 V
– +

F. 180
Problem 36.

9 Clampers
37. Sketch vo for each network of Fig. 181 for the input shown.

–
+

(a) (b)

F. 181
Problem 37.

128
 38. Sketch vo for each network of Fig. 182 for the input shown. DD AA

Ideal
Ideal +
E
–
(a) (b)

F. 182
Problem 38.

*39. For the network of Fig. 183:

a. Calculate 5t.
b. Compare 5t to half the period of the applied signal.
c. Sketch vo.

12 V

–12 V +

F. 183
Problem 39.

*40. Design a clamper to perform the function indicated in Fig. 184.

F. 184
Problem 40.

*41. Design a clamper to perform the function indicated in Fig. 185.

Design

F. 185
Problem 41.

129
 DD AA 10 Zener iodes
*42. a. Determine VL, IL, IZ, and IR for the network of Fig. 186 if RL 5 180 .
b. Repeat part (a) if RL 5 470 .
c. Determine the value of RL that will establish maximum power conditions for the Zener diode.
d. Determine the minimum value of RL to ensure that the Zener diode is in the “on” state.

VZ = 10 V
PZ
max
= 400 mW

F. 186
Problem 42.

*43. a. Design the network of Fig. 187 to maintain VL at 12 V for a load variation (IL) from 0 mA
to 200 mA. That is, determine RS and VZ.
b. Determine PZ max for the Zener diode of part (a).
*44. For the network of Fig. 188, determine the range of Vi that will maintain VL at 8 V and not
exceed the maximum power rating of the Zener diode.

VZ

F. 187 F. 188

Problem 43. Problems 44 and 52.

45. Design a voltage regulator that will maintain an output voltage of 20 V across a 1-k load with
an input that will vary between 30 V and 50 V. That is, determine the proper value of RS and
the maximum current IZM.
46. Sketch the output of the network of Fig. 145 if the input is a 50-V square wave. Repeat for a
5-V square wave.

11 oltage-Multiplier Circuits
47. Determine the voltage available from the voltage doubler of Fig. 123 if the secondary voltage
of the transformer is 120 V (rms).
48. Determine the required PIV ratings of the diodes of Fig. 123 in terms of the peak secondary
voltage Vm.
14 Computer nalysis
49. Perform an analysis of the network of Fig. 156b using PSpice Windows.
50. Perform an analysis of the network of Fig. 161b using PSpice Windows.
51. Perform an analysis of the network of Fig. 162 using PSpice Windows.
52. Perform a general analysis of the Zener network of Fig. 188 using PSpice Windows.
53. Repeat Problem 49 using Multisim.
54. Repeat Problem 50 using Multisim.
55. Repeat Problem 51 using Multisim.
56. Repeat Problem 52 using Multisim.

130
OLO O LC O-M OLM DD AA
l
1. (a) IDQ  15 mA, VDQ  0.85 V, VR 5 11.15 V (b) IDQ  15 mA, VDQ = 0.71 V,
VR 5 11.3 V (c) IDQ = 16 mA, VDQ = 0 V, VR 5 12 V
3. R 5 0.62 k
5. (a) I 5 0 mA (b) I 5 2.895 A (c) I 5 1 A
7. (a) Vo 5 9.17 V (b) Vo 5 10 V
9. (a) Vo1 = 11.3 V, Vo2 = 1.2 V (b) Vo1 = 0 V, Vo2 = 0 V
11. (a) Vo 5 0.3 V, I 5 0.3 mA (b) Vo 5 14.6 V, I 5 3.96 mA
13. Vo 5 6.03 V, ID 5 1.635 mA
15. Vo 5 9.3 V
17. Vo 5 10 V
19. Vo 5 20.7 V
21. Vo 5 4.7 V
23. vi: Vm 5 6.98 V: rd: pos. max 5 0.7 V, neg. peak 5 26.98 V: id: pos. pulse of
3.14 mA
25. Pos. pulse, peak 5 169.68 V, Vdc 5 5.396 V
27. (a) IDmax = 20 mA (b) Imax 5 40 mA (c) ID 5 18.1 mA
(d) ID 5 36.2 mA . IDmax = 20 mA
29. Full rectified waveform, peak 5 2100 V; PIV 5 100 V, Imax 5 45.45 mA
31. Full rectified waveform, peak 5 56.67 V; Vdc 5 36.04 V
33. (a) Pos. pulse of 5.09 V (b) Pos. pulse of 15.3 V
35. (a) Clipped at 4.7 V (b) Pos. clip at 0.7 V, neg. peak 5 211 V
37. (a) 0 V to 40 V swing (b) 25 V to 35 V swing
39. (a) 28 ms (b) 56:1 (c) 21.3 V to 225.3 V swing
41. Network of Fig. 179 with battery reversed
43. (a) Rs 5 20 , VZ 5 12 V (b) PZmax 5 2.4 W
45. Rs 5 0.5 k, IZM 5 40 mA
47. Vo 5 339.36 V

131