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PDF Solution Manual For VHDL For Engineers Kenneth L Short Online Ebook Full Chapter
PDF Solution Manual For VHDL For Engineers Kenneth L Short Online Ebook Full Chapter
PDF Solution Manual For VHDL For Engineers Kenneth L Short Online Ebook Full Chapter
Kenneth L. Short
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Solution Manual for VHDL for Engineers Kenneth L.
Short
7.1 The two basic things that need to be verified about a design are: (1) does the design achieve its intended func-
tionality, (2) After being synthesized and mapped to the target PLD, will the design meet its timing requirements.
Both of these aspects of a design are verified through simulation using a testbench.
7.2 The three primary constituents of a simple testbench are the UUT, stimulus generator, and response monitor.
7.3 It is often possible to write a testbench so that the unit under test (UUT) is the only constituent of the test-
bench that must be changed to perform the three basic verifications. For a functional verification the design
description is the UUT. The VHDL netlist generated by the synthesizer is the UUT in a post-synthesis verifica-
tion. For a timing verification, the VHDL timing model generated by the place-and-route tool is the UUT.
7.4 An exhaustive verifcation is one where every possible input is applied and the output is verfied for each input
applied. Since a combinational design’s outputs at any time are a function only of its inputs at that time, the order
in which input combinations are applied does not affect the verification results. For a combinational design, an
exhaustive verification requires the application, in any order, of every possible input combination to the UUT
and verification of its outputs for each input combination.
In contrast, exhaustive verification of a sequential design requires that every possible sequence of input combina-
tions be applied to the UUT and its outputs verified. For even a moderately complex sequential design, it is
impractical to perform an exhaustive verification because of the enormous number of different input sequences
that would have to be applied. Therefore, it is usually impossible to prove that a complex sequential design is
error free. Consequently, a determination must be made as to what input sequences constitute an adequate verifi-
cation for a particular design.
7.5 A natural language specification for a system usually contains ambiguities. The more complex the system,
the more ambiguities in its specification. When writing a design description or a testbench starting from a natural
language specification, the designer must interpret the specification to determine the intent of the design. If the
same person writes both the design description and its testbench and they are both based on the same incorrect
interpretation of the system specification, then the verification may be successful, but the design is still incorrect.
If the testbench is written by a person( other than the person who wrote the design description, if the two inde-
pendent interpretations of design intent are not identical, the testbench should expose the differences, so that they
can be properly resolved.
7.6 Usually, only the two values '0' and '1' from the nine std_logic values are applied to a UUT’s inputs for
verification. For some timing verifications the value ‘X’ is sometimes applied to model when an input signal
will have an invalid or unstable value.
7.7 For a combinational design with n inputs there are 2n possible input combinations. The order in which the
input combinations is applied is not critical for a combinational system. The number of input combinations to be
applied to designs with 4, 9, 14, and 32 inputs are: 16, 512, 16,384 and 4,294,967,296 respectively.
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;
UUT : entity three_inputs port map (a => a_tb, b => b_tb, c => c_tb,
sum => sum_tb, carry_out => carry_out_tb );
end waveform;
7.9
library ieee;
use ieee.std_logic_1164.all;
entity nandwfb_tb is
end nandwfb_tb;
end tb_architecture;
7.10 The time component of each transaction in an assignment statement that describes a projected waveform is
the sum of the current simulation time (Tc) and the value of the corresponding after clause’s time expression. For
the assignment statement given the signal will take the value 0 at 150 ns, 1 at 160 ns, 0 at 175 ns, and 1 at 195 ns.
2
7.11 ##
7.12
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;
3
7.13 Wait statements are used to realize a specific delay between the application of each stimulus value. After the
delay, an assertion statement can be used to check the outputs.
There are three reasons why wait statements are required in a testbench. First, the signal assignments can’t take
effect until after the process suspends. Without the wait for statement, the response would be checked during the
current simulation cycle and would not be the response to the newly assigned input values. Second, waiting for a
time interval allows the new input values to appear in the simulator waveforms for this time period. This makes
it possible to view the waveform. Otherwise, all the actions in the process would take place in zero simulation
time. As a result, the waveform’s time axis would be compressed to zero length and the waveforms would not be
viewable. Third, the wait for statements allow the same testbench to be used later, without modification, for a
timing simulation. During the timing simulation, we want the simulator to wait a period of time, determined from
the design’s timing specification, before the UUT’s outputs are checked. The maximum propagation delay of the
design mapped to the target PLD must be less than or equal to this period of time, or the timing simulation fails.
The final wait statement, without a for clause, suspends the process indefinitely. This causes the simulation to
stop. Without this final wait statement, the process would repeat forever, or until the simulator time limit is
reached.
Use of assertion statements allows the testbench to automatically verify the UUT’s response, eliminating the
need to visually inspect timing waveforms.
7.14
library ieee;
use ieee.std_logic_1164.all;
entity half_adder is
port (a, b : in std_logic;
sum, carry_out: out std_logic);
end half_adder;
Since the description is to use a wait statement the process cannot have a sensitivity list. The wait statement must
be at the end of the description if the description if functionally the architecture is to be exactly equivalent to
Listing 2.6.1. This is because in Listing 2.6.1 both assignment statements get executed at initialization. If the
wait statement is put before either of the assignment statements this will the be the case. After initialization we
need the process to execute every time there is an event on either a or b. Accordingly a wait on statement is
chose because it has a sensitivity list. While a process is suspended due to the execution of a wait on statement,
all signals in the statement’s sensitivity list are monitored by the simulator. When an event occurs on any signal
4
in the wait on statement’s sensitivity list the process that contains it is activated and the process resumes execu-
tion at the statement following the wait on statement (in this case the beginning of the process).
7.15
process
begin
a_tb <= '0';
b_tb <= '0';
wait for 20 ns;
b_tb <= '1';
wait for 20 ns;
a_tb <= '1';
b_tb <= '0';
wait for 20 ns;
b_tb <= '1';
wait;
end process;
This process creates exactly the same stimulus as the concurrent assignment statements in Listing 7.15. However,
if you want each input to be applied for 20 ns the simulator must be set to run for 80 ns or a wait for 20 ns
statement can be added just before the last wait statement.
7.16 If the condition in an assertion statement evaluates false, an assertion violation occurs. If the assertion state-
ment includes a report clause, the string that comprises the expression in the report clause is displayed. A report
statement is a separate statement. A report statement displays its message every time the statement is executed. If
a report statement’s severity clause is omitted, its severity level defaults to note (instead of the default level of
error for an assertion statement).
7.17 If a semicolon is inadvertently placed after the assert clause in an assertion statement, in addition to after its
severity clause, two statments are created. The first is an assertion statement without a report clause or severity
clause. If the condition in the assertion statement evaluates false when the assertion statement is executed, the
simulator displays the default error message “Assertion violation” and the default severity level is error. The sec-
ond statement is a report statement. The message that was intended to be part of the assertion statement becomes
part of the report statement and is always displayed when the report statement is executed and has the severity
level intended for the assertion statement.
7.18
library ieee;
use ieee.std_logic_1164.all;
entity testbench is
end testbench;
5
uut: entity half_adder port map(a => a_tb, b => b_tb,
sum => sum_tb, carry_out => carry_out_tb);
tb : process
constant period: time := 20 ns;
begin -- Apply every possible input combination
wait;
end process;
end;
When the assertion statement’s condition for correct operation is contingent on correct values for several signals
then writing the condition in terms of incorrect operation can be complex. In this example, not only does the not
operator have to be place in front of the condition and the values of the signals complemented but the and opera-
tor must be changed to an or operator. You can think of this in terms of DeMorgan’s theorem.
7.19 ##
7.20
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fuel_encoder_tb is
end fuel_encoder_tb;
6
signal fuel : std_logic_vector(3 downto 0);
signal leds : std_logic_vector(3 downto 0);
begin
process
begin
for i in 0 to 15 loop
fuel <= std_logic_vector(to_unsigned(i,4));
wait for 20 ns;
assert leds = patterns(i)
report "test failed for input integer'image(i)";
end loop;
wait;
end process;
end tb_architecture;
7,21 The first sentence in the statement of Problem 7.21 should be deleted. The problem statement starts with the
next sentence: “A demultiplexer has ....”
library ieee;
use ieee.std_logic_1164.all;
entity demux_1to4_tb is
end demux_1to4_tb;
7
constant test_vectors : test_vector_array := (
('0', "00", "0000"),
('0', "01", "0000"),
('0', "10", "0000"),
('0', "11", "0000"),
('1', "00", "0001"),
('1', "01", "0010"),
('1', "10", "0100"),
('1', "11", "1000"));
begin
-- Stimulus
verify: process
variable vector : test_vector;
begin
for i in test_vectors'range loop
vector := test_vectors(i);
wait;
end process;
end tb_architecture;
7.22
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ones_count_tb is
end ones_count_tb;
8
signal num_ones, num_ones_exp : std_logic_vector(3 downto 0);
constant period : time := 20 ns;
begin
stimulus: process
begin
for i in 0 to 7 loop
inp <= std_logic_vector(to_unsigned(i,3));
wait for period;
assert num_ones = num_ones_exp
report "error for input test vector " & integer'image(i)
severity error;
end loop;
wait;
end process;
end tb_architecture;
7.23
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity therm2bin_tb is
end therm2bin_tb;
constant n : integer := 7;
9
constant period : time := 20 ns;
begin
tb: process
variable therm_var : bit_vector (6 downto 0);
begin
for i in 0 to 7 loop
therm_var := "1111111" sll i;
therm <= to_stdlogicvector(not(therm_var));
7.24
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity ic74ac280_tb is
end ic74ac280_tb;
tb: process
constant period : time := 100ns;
variable sum_even_actual : std_logic;
variable sum_even_expected : std_logic;
10
variable sum_odd_actual : std_logic;
variable sum_odd_expected : std_logic;
begin
for j in 0 to 511 loop
i <= conv_std_logic_vector (j, 9);
wait for period;
sum_even_actual := sum_even;
sum_even_expected := not (i(8) xor i(7) xor i(6) xor i(5) xor i(4)
xor i(3) xor i(2) xor i(1) xor i(0));
assert sum_even_actual = sum_even_expected
report "error for input vector " & integer'image(j)
severity error;
sum_odd_actual := sum_odd;
sum_odd_expected := i(8) xor i(7) xor i(6) xor i(5) xor i(4)
xor i(3) xor i(2) xor i(1) xor i(0);
assert sum_odd_actual = sum_odd_expected
report "error for input vector " & integer'image(j)
severity error;
end loop;
wait;
end process;
end tb_architecture;
7.25
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tally_tb is
end tally_tb;
begin
11
variable stimulus_vector : std_logic_vector (5 downto 0);
begin
for i in 0 to 63 loop
stimulus_vector := std_logic_vector(to_unsigned(i, 6));
scoresb <= stimulus_vector(5 downto 3);
scoresa <= stimulus_vector(2 downto 0);
wait for 20 ns;
end tb_architecture;
7.26
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_2_bar_tb is
end bcd_2_bar_tb;
begin
12
bcd => bcd,
bargraph => bargraph
);
tb : process
constant period: time := 20 ns;
variable expected : std_logic_vector(8 downto 0);
type table_array is array (0 to 9) of std_logic_vector(8 downto 0);
constant table_entry : table_array := (
"000000000",
"000000001",
"000000011",
"000000111",
"000001111",
"000011111",
"000111111",
"001111111",
"011111111",
"111111111");
begin
-- Apply input combinations 0 through 9, output is checked
for i in 0 to 9 loop
bcd <= std_logic_vector(to_unsigned(i,4));
wait for period;
expected := table_entry(to_integer(unsigned(bcd)));
assert bargraph = expected
report "test failed for input integer'image(i)";
-- compute next expected value
end loop;
wait;
end process;
end tb_architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_2_bar_tb is
end bcd_2_bar_tb;
13
begin
tb : process
constant period: time := 20 ns;
variable expected : std_logic_vector(8 downto 0);
wait;
end process;
end tb_architecture;
7.27 ##
7.28 The problem statement asks for a solution using two loops. The solution given here uses a single loop and is
more concise to write. It uses a boolean constant name dont_care that is set to true for a functional simula-
tion where the model’s output is verified to be don’t cares when neither the blanking input nor lamp test input is
asserted and the BCD input is invalid. Constant dont_care that is set to false for a post-synthesis or a tim-
ing simulation where the model’s output is not verified when neither the blanking input nor lamp test input is
asserted and the BCD input is invalid.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd_7seg_tb is
end bcd_7seg_tb;
14
signal bi_bar : std_logic;
signal lt_bar : std_logic;
signal dcba : std_logic_vector(3 downto 0);
signal seg, seg_gld : std_logic_vector(6 downto 0);
-- Set constant dont_care to true if UUT model has don't care outputs
-- and they are to be checked (for example for functional simulation).
-- Set constant dont_care to false if model does not have don't care
-- outputs (post_synthesis or timing simulation).
begin
stimulus : process
variabletstvec : std_logic_vector(5 downto 0);
begin
for i in 0 to 2 ** 6 - 1 loop
tstvec := std_logic_vector(to_unsigned(i,6));
bi_bar <= tstvec(5);
lt_bar <= tstvec(4);
dcba <= tstvec(3 downto 0);
if
(dont_care = false and not (dcba > "1001" and bi_bar = '1' and lt_bar = '1'))
or dont_care = true then
assert seg = seg_gld
report "error input vector" & integer'image(i)
severity error;
end if;
end loop;
wait;
end process;
15
"0001111",
"0000000",
"0001100",
"-------",
"-------",
"-------",
"-------",
"-------",
"-------"
);
begin
if bi_bar = '0' then
seg_gld <="1111111";
elsif lt_bar = '0' then
seg_gld <="0000000";
else
seg_gld <= segout(to_integer(unsigned(dcba)));
end if;
end process;
end tb_architecture;
7.29
(a)
end dataflow;
(b)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mux_4_to_1_tb is
end mux_4_to_1_tb;
16
port map (
i => i,
s => s,
y => y
);
i <= "1110";
for j in 0 to 3 loop
for k in 0 to 3 loop
s <= std_logic_vector(to_unsigned(k,2));
wait for period;
if (j = k) then
assert y = ('0') report "output error" severity error;
else
assert y = ('1') report "output error" severity error;
end if;
end loop;
i <= i(2 downto 0) & '1';
end loop;
i <= "0001";
for j in 0 to 3 loop
for k in 0 to 3 loop
s <= std_logic_vector(to_unsigned(k,2));
wait for period;
if (j = k) then
assert y = ('1') report "output error" severity error;
else
assert y = ('0') report "output error" severity error;
end if;
end loop;
i <= i(2 downto 0) & '0';
end loop;
wait;
end process;
end tb_architecture;
7.30
library ieee;
use ieee.std_logic_1164.all;
17
Solution Manual for VHDL for Engineers Kenneth L. Short
use ieee.numeric_std.all;
entity synthfcn_tb is
end synthfcn_tb;
begin
-- "golden" entity
u1 : entity golden
port map(
goldnin => goldnin,
goldnout => goldnout
);
18
Author: AntoineMativet
Language: French
MONCHOISY
J’étais là, telle chose m’advint.
PARIS
G. CHARPENTIER ET Cie, ÉDITEURS
11, RUE DE GRENELLE, 11
1888
ASNIÈRES. — IMPRIMERIE LOUIS BOYER ET Cie
LA
NOUVELLE CYTHÈRE
A beau mentir qui vient de loin.