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IBEX PEAK-M (GND)

<30> BMBUSY#
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
BMBUSY# Y3
U23F

BMBUSY# / GPIO0(+3V)
Ibex-M
6 OF 10 CLKOUT_PCIE6N
CLKOUT_PCIE6P
AH45
AH46
AB16
AA19
U23H

VSS[0]
VSS[1]
VSS[80]
VSS[81]
AK30
AK31 <9> GNT3# R507
10
*10K_NC
<29> SIO_EXT_SMI# C38 TACH1 / GPIO1 (+3V) AA20 VSS[2] VSS[82] AK32
AA22 VSS[3] VSS[83] AK34
<29> SIO_EXT_SCI# D37 TACH2 / GPIO6 (+3V) AM19 VSS[4] VSS[84] AK35 A16 swap override Strap/Top-Block
CLKOUT_PCIE7N AF48 AA24 VSS[5] VSS[85] AK38 Swap Override jumper
J32 AF47 AA26 AK43
A
<26> BT_OFF# TACH3 / GPIO7 (+3V) GPIO CLKOUT_PCIE7P
AA28
VSS[6]
VSS[7]
VSS[86]
VSS[87] AK46 A
TP0 PCH_GPIO8 F10 AA30 AK49 Low = A16 swap
GPIO8(+3V_S5) MISC AA31
VSS[8]
VSS[9]
VSS[88]
VSS[89] AK5 override/Top-Block
<27,29> LAN_DISABLE# R234 *0_4 LAN_DISABLE_R# K9 U2 GATEA20 <29> AA32 AK8 GNT3# Swap Override enabled
LAN_PHY_PWR_CTRL / GPIO12(+3V_S5) A20GATE VSS[10] VSS[90]
AB11 VSS[11] VSS[91] AL2 High = Default
<31> RF_OFF# T7 GPIO15(+3V_S5) AB15 VSS[12] VSS[92] AL52
AB23 VSS[13] VSS[93] AM11
<30> SATA4GP SATA4GP AA2 AM3 CLK_CPU_BCLK# <3> AB30 BB44
SATA4GP / GPIO16(+3V) CLKOUT_BCLK0_N/CLKOUT_PCIE8N VSS[14] VSS[94]
AB31 VSS[15] VSS[95] AD24
PCH_GPIO17 F38 TACH0 / GPIO17(+3V) CLKOUT_BCLK0_P/CLKOUT_PCIE8P AM1 CLK_CPU_BCLK <3> AB32 VSS[16] VSS[96] AM20
AB39 AM22 SV_SET_UP R259 10K/F_4 +3V
BIOS_REC VSS[17] VSS[97]
Y7 SCLOCK / GPIO22(+3V) PECI BG10 PCH_PECI_R H_PECI <3> AB43 VSS[18] VSS[98] AM24
GPIO27 left NC for AB47 VSS[19] VSS[99] AM26
internal VR. TP3 GPIO27 AB12 T1 RCIN# <29> AB5 AM28
GPIO27(+3V_S5) RCIN# VSS[20] VSS[100]
AB8 BA42
<30> TP_PCH_GPIO28 TP_PCH_GPIO28 V13
GPIO28 (+3V_S5)
CPU PROCPWRGD BE10 H_PW RGOOD <3,30> AC2
VSS[21]
VSS[22]
VSS[101]
VSS[102] AM30 SV_SET_UP 1-X High = Strong (Default)
AC52 VSS[23] VSS[103] AM31
<30> SATA2GP SATA2GP AB7 BD10 PCH_THRMTRIP#_R PM_THRMTRIP# <3,29> AD11 AM32
SATA2GP / GPIO36 (+3V) THRMTRIP# R262 56.2/F_4 AD12
VSS[24] VSS[104]
AM34
SATA3GP VSS[25] VSS[105]
<30> SATA3GP AB13 SATA3GP / GPIO37 TP1 BA22 +1.05V_VTT AD16 VSS[26] VSS[106] AM35
(+3V) AW22 R266 56.2/F_4 AD23 AM38
LCD_BK TP2 VSS[27] VSS[107] GNT0# R302 *1K/F_4
<20> LCD_BK P3 SDATAOUT0 / GPIO39(+3V) TP3 BB22 AD30 VSS[28] VSS[108] AM39 <9> GNT0#
AY45 AD31 AM42 <9> GNT1# GNT1# R506 *1K/F_4
TP4 VSS[29] VSS[109]
TP5 AY46 AD32 VSS[30] VSS[110] AU20
<3> PCIE_CLK_REQ7# PCIE_CLK_REQ7# F1 AV43 AD34 AM46
PCIECLKRQ7# / GPIO46(+3V_S5) TP6 VSS[31] VSS[111]
TP7 AV45 AU22 VSS[32] VSS[112] AV22
SV_SET_UP AB6 AF13 AD42 AM49
SDATAOUT1 / GPIO48 (+3V) TP8 VSS[33] VSS[113]
TP9 M18 AD46 VSS[34] VSS[114] AM7 Boot BIOS Strap
<29,30> SATA5GP AA4 SATA5GP / GPIO49 (+3V) TP10 N18 AD49 VSS[35] VSS[115] AA50
B RSVD AJ24 AD7 BB10 PCI_GNT0# GNT#1 Boot BIOS Location B
TP11 VSS[36] VSS[116]
TP12 AK41 AE2 VSS[37] VSS[117] AN32
AK42 AE4 AN50 0 0 LPC
TP13 VSS[38] VSS[118]
TP14 M32 AF12 VSS[39] VSS[119] AN52
BOARD_ID0 H10 N32 Y13 AP12 0 1 Reserved (NAND)
BOARD_ID1 GPIO24 (+3V_S5) TP15 VSS[40] VSS[120]
H3 PCIECLKRQ6# / GPIO45(+3V_S5) TP16 M30 AH49 VSS[41] VSS[121] AP42
BOARD_ID2 F8 N30 AU4 AP46 1 0 PCI
BOARD_ID3 GPIO57 (+3V_S5) TP17 VSS[42] VSS[122]
M11 STP_PCI# / GPIO34 TP18 H12 AF35 VSS[43] VSS[123] AP49
BOARD_ID4 V6 (+3V) AA23 AP13 AP5 1 1 SPI
BOARD_ID5 SATACLKREQ# / GPIO35(+3V) TP19 VSS[44] VSS[124]
V3 AB45 AN34 AP8
SLOAD / GPIO38 (+3V) NC_1
AB38 AF45
VSS[45] VSS[125]
AR2
NC_2 VSS[46] VSS[126]
NC_3 AB42 AF46 VSS[47] VSS[127] AR52
NC_4 AB41 AF49 VSS[48] VSS[128] AT11
NC_5 T39 AF5 VSS[49] VSS[129] BA12
INIT3_3V# P6 AF8 VSS[50] VSS[130] AH48
+3VS5 C10 AG2 AT32
TP24 VSS[51] VSS[131]
AG52 VSS[52] VSS[132] AT36
A4 BH2 +3V AH11 AT41
R271 10K/F_4 TP_PCH_GPIO28 VSS_NCTF_1 VSS_NCTF_16 VSS[53] VSS[133]
A49 VSS_NCTF_2 VSS_NCTF_17 BH52 AH15 VSS[54] VSS[134] AT47
A5 BH53 RCIN# R228 10K/F_4 AH16 AT7
VSS_NCTF_3 VSS_NCTF_18 GATEA20 R229 10K/F_4 VSS[55] VSS[135]
A50
A52
VSS_NCTF_4 NCTF VSS_NCTF_19 BJ1
BJ2 SATA2GP R260 10K/F_4
AH24
AH32
VSS[56] VSS[136] AV12
AV16 Danbury Technology Enabled
VSS_NCTF_5 VSS_NCTF_20 SATA3GP R268 10K/F_4 VSS[57] VSS[137]
A53 VSS_NCTF_6 VSS_NCTF_21 BJ4 AV18 VSS[58] VSS[138] AV20
B2 BJ49 SATA4GP R459 10K/F_4 AH43 AV24 High = Enable
VSS_NCTF_7 VSS_NCTF_22 SATA5GP R458 10K/F_4 VSS[59] VSS[139] NV_ALE
B4 VSS_NCTF_8 VSS_NCTF_23 BJ5 AH47 VSS[60] VSS[140] AV30
B52 BJ50 BMBUSY# R461 10K/F_4 AH7 AV34 Low = Disable
VSS_NCTF_9 VSS_NCTF_24 SIO_EXT_SMI# R286 10K/F_4 VSS[61] VSS[141]
B53 VSS_NCTF_10 VSS_NCTF_25 BJ52 AJ19 VSS[62] VSS[142] AV38
BE1 BJ53 SIO_EXT_SCI# R287 10K/F_4 AJ2 AV42
VSS_NCTF_11 VSS_NCTF_26 BT_OFF# R285 10K/F_4 VSS[63] VSS[143]
BE53 VSS_NCTF_12 VSS_NCTF_27 D1 AJ20 VSS[64] VSS[144] AV46
C BF1 D2 LCD_BK R447 10K/F_4 AJ22 AV49 DMI Termination Voltage C
VSS_NCTF_13 VSS_NCTF_28 VSS[65] VSS[145]
BF53 VSS_NCTF_14 VSS_NCTF_29 D53 AJ23 VSS[66] VSS[146] AV5
BH1 VSS_NCTF_15 VSS_NCTF_30 E1 AJ26 VSS[67] VSS[147] AV8
E53 PCH_GPIO17 R289 10K/F_4 AJ28 AW14 Set to Vcc when LOW
VSS_NCTF_31 VSS[68] VSS[148] NV_CLE
AJ32 VSS[69] VSS[149] AW18
IbexPeak-M_Rev1_0 AJ34 AW2 Set to Vcc/2 when HIGH
VSS[70] VSS[150]
AT5 VSS[71] VSS[151] BF9
AJ4 VSS[72] VSS[152] AW32
AK12 VSS[73] VSS[153] AW36
+3V +3VS5 AM41 AW40
VSS[74] VSS[154]
AN19 VSS[75] VSS[155] AW52
AK26 VSS[76] VSS[156] AY11
BIOS_REC R244 10K/F_4 RF_OFF# R275 1K/F_4 AK22 AY43
BIOS RECOVERY AK23
VSS[77] VSS[157]
AY47
No Reboot Strap
VSS[78] VSS[158]
HIGH : DISABLE AK28 VSS[79]
LOW : ENABLE LAN_DISABLE_R# R235 10K/F_4
IbexPeak-M_Rev1_0

+3VS5 <7,25> ACZ_SPKR +3V

*1K/F_4 R466
RU0 RD0
R236 *10K/F_4 BOARD_ID0 R237 10K/F_4 R283 *100K/F_4
Board ID ID0 ID1 ID2 ID3 ID4 ID5 <7,29> PCH_GPIO33

BOARD ID SETTING RU1 RD1

R224 *10K/F_4 BOARD_ID1 R225 10K/F_4
UMA FF 0 0 0 0 0 0
RU2 RD2
D Board ID5: For idenify UMA and DIS R249 *10K/F_4 BOARD_ID2 R248 10K/F_4 <3,5,11,29,30,34,35,40> +1.05V_VTT D
+3V
Board ID4: For idenify FF and DF UMA DF 0 0 0 0 1 0 RU3 RD3 <5,11,33,38> +1.8V
<2,3,7,8,9,11,12,13,15,20,21,22,23,24,25,26,27,28,29,30,31,34,38> +3V
Board ID3: Reserve R254 *10K/F_4 BOARD_ID3 R255 10K/F_4 <3,8,9,11,30,38> +3VS5
Board ID2: Reserve RU4 RD4
DIS 0 0 0 0 0 1
Board ID1: Reserve R242 *10K/F_4 BOARD_ID4 R243 10K/F_4
PROJECT :AX1
RU5 RD5 Quanta Computer Inc.
R462 10K/F_4 BOARD_ID5 R463 *10K/F_4

Size Document Number Rev

Custom 1A
PCH 4/5 (GPIO & Strap)
Date: Thursday, November 12, 2009 Sheet 10 of 40
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