Optik - International Journal for Light and Electron Optics 178 (2019) 909–917

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Optik
journal homepage: www.elsevier.com/locate/ijleo

Original research article

Optically-activated cascode configuration for 650 V GaN FET

T
devices and packaging parasitic inductance effects
⁎ ⁎
Zahra Hemmata, , Alireza Mojabb, , Enrique Morenoc, Alireza Ahmadiparidaria,
Mohsen Paryavid, Mehrdad Alizadehe, Ernest Alexander Michaelc
a
Nanomaterial and Energy Systems Laboratory, University of Illinois at Chicago, Chicago, IL, USA
b
NuCurrent Inc., Advanced Wireless Power, Chicago, IL, USA
c
Photonics Group, University of Chile, Chile
d
University of Hawaii at Manoa, Honolulu, HI, USA
e
AT&T Labs, Middletown, NJ, USA

A R T IC LE I N F O ABS TRA CT

Keywords: In this paper, a novel optically-activated cascode structure is proposed to be used with a nor-
Gallium nitride field-effect transistor (GaN mally-on gallium nitride (GaN) field-effect transistor (FET) device to achieve an overall normally-
FET) off configuration. Using this novel configuration, cost-effective infrared (IR) lasers can be utilized
Optical switch (OS) instead of expensive ultraviolet (UV) lasers to activate this structure which includes a wide-
Cascode configuration
bandgap-material device (GaN FET). Furthermore, the effect of parasitic inductance available in
Wide bandgap power semiconductor devices
the package and connections of this proposed configuration is evaluated using Silvaco TCAD
Packaging parasitic inductance
simulations. In practice, one high-power normally-on FET device is connected in series with a
low-power optical switch (OS) to make the proposed overall normally-off cascode structure. The
capability of being optically-activated for the proposed structure has many advantages over the
conventional electrically-activated cascode structures including but not limited to: more im-
munity to electromagnetic interference (EMI), using only one main bias as the power source,
using cost-effective long-wavelength laser instead of expensive short-wavelength lasers to trigger
the GaN devices, reduced current and voltage ringing during switching transitions, etc.
Comprehensive device modeling and parasitic inductance analysis for this new proposed optical
cascode GaN FET device are provided in this work.

1. Introduction

Cascode GaN FETs are introduced to offer a normally-off solution with a higher threshold voltage, higher maximum gate voltage,
and less susceptibility compared to enhancement mode high-electron-mobility transistors (HEMTs) [1–3]. They also offer improved
efficiency through higher frequency, higher power density, lower gate charge, lower crossover loss, and lower reverse recovery
charge compared to silicon MOSFETs [4]. In recent decades, optical triggering of power semiconductor devices has been improved to
mitigate the EMI problems associated with electrical high-power high-frequency switching applications [5]. Optical triggering of
wide bandgap semiconductor devices requires short wavelength light sources which is mostly applicable in photoconductive semi-
conductor switches (PCSS) [6–8]; However, there is no record of utilizing short wavelength lasers for GaN FET devices due to the high
bandgap of GaN material and subsequently expensive light sources. To overcome this challenge, optical cascode (OC) GaN FET device

⁎
Corresponding authors.
E-mail addresses: zhemma2@uic.edu (Z. Hemmat), amojab2@uic.edu (A. Mojab).

https://doi.org/10.1016/j.ijleo.2018.10.086
Received 24 August 2018; Accepted 11 October 2018
0030-4026/ © 2018 Elsevier GmbH. All rights reserved.
Z. Hemmat et al. Optik - International Journal for Light and Electron Optics 178 (2019) 909–917

Fig. 1. Schematic electrical structure for the proposed normally-OFF OC GaN FET.

has been introduced and evaluated for the first time in [9] which enables one to use cost-effective long wavelength light sources to
trigger GaN FET devices. Furthermore, the OC GaN FET provides a reliable normally-off configuration which is less susceptible to EMI
and gate oscillations.
The OC GaN FET topology is depicted in Fig. 1 in which a low-voltage OS is connected in series with the main high-voltage
depletion-mode GaN FET device to form an overall normally-off configuration. Source and gate terminals of the GaN FET device are
connected to the collector and emitter terminals of the OS, respectively. Compared to the conventional electrical cascode (EC) GaN
FET devices, the OC GaN FET offers many advantageous properties. The OC GaN FET is operated under a single-biased condition with
no low-voltage bias which existed in the conventional electrical gate driver for EC GaN FET [10–12]. The low-voltage driver circuit is
always prone to the EMI noise in very fast and high-voltage pulsed power applications. In the OC GaN FET configuration, the laser can
be placed far away from the main high-voltage circuit to immune the system from radiative and back-propagation noise. Another
important advantage of the proposed OC GaN FET configuration is the elimination of gate parasitic inductance which has the highest
value compared to other stray and parasitic inductances according to [12–14].
The proposed OC GaN FET structure enables one to use cheap and cost-effective infrared (IR) lasers to optically activate wide
bandgap GaN devices instead of using complex and expensive ultraviolet (UV) lasers. If one needs to activate a wide bandgap GaN
device optically, an expensive short-wavelength light source is required to overcome the material bandgap and generate electron-hole
pairs. Now, with this proposed OC GaN FET, the illumination is taking place on the series-connected low-power OS which is made of
narrow bandgap materials like silicon or gallium arsenide (GaAs). Therefore, cost-effective long-wavelength light sources (like IR
lasers) can be used efficiently.
The 2D structures for GaN FET and GaAs OS devices used in the analysis and simulations of this paper are shown in Fig. 2. The two
top AlGaN and GaN layers for the GaN FET device are un-doped to provide the highest possible blocking voltage. With a gate-to-drain
distance of 10 μm, a blocking voltage of more than about 650 V is achieved for the GaN FET device. On the other hand, the GaAs OS is
designed for a low-voltage rating of about 30 V. By growing a drift layer with a thickness of 2.5 μm and a doping of 1 × 1015 cm−3, a
breakdown voltage of more than 30 V is achieved for the GaAs OS. The on-state voltage of the GaAs OS is designed to be less than
0.5 V under a load current of 10 A.

2. Switching transitions for the proposed OC GaN FET

2.1. Turn-on procedure

The OC GaN FET is turned on by illuminating the OS device. The on-state voltage of the OS is then reduced to less than about 0.5 V
depending on the optical power used to illuminate the device. This small on-state voltage is dropped across the source-gate contacts
of the normally-on GaN FET. The normally-on GaN FET has a negative threshold voltage and the OS on-state voltage is negatively
greater than the threshold voltage of the GaN FET. Therefore, the GaN FET device is also turned on, turning the entire cascode
structure on. The complete on-state voltage of the cascode configuration is the sum of on-state voltages across GaN FET and OS

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Fig. 2. Schematic 2D device structures for (a) GaN FET and (b) GaAs OS used in the configuration of OC GaN FET.

devices. Therefore, the OS should be designed to handle the high rated current of the GaN FET while keeping a low on-state voltage
[15].
The rise time of the entire cascode structure depends on the rise times of both OS and GaN FET devices. The GaN FET technology
has been already known to be much faster than silicon and GaAs technologies. In order to meet the speed requirement of the GaN FET
device, it is suggested to use GaAs technology rather than silicon to fabricate the OS device. Silicon technology can also be used to
fabricate the OS as a cheaper and cost-effective option; however, the speed of silicon OS will be deteriorated due to the indirect
bandgap of silicon and introduced trap levels in the bandgap of silicon. GaN as a direct bandgap material can also be used to fabricate
the OS to achieve very high-speed transitions and possibly integrated structure for the complete cascode configuration; however, the
required short-wavelength laser to trigger the GaN material is very expensive with a very low optical power available in the market.
Hence, GaAs as a direct bandgap material, requiring cheaper long-wavelength lasers with higher optical powers, is proposed for the
fabrication of OS in the configuration of optical cascode GaN FET presented in this paper.
Turn-on time of the OS shown in Fig. 2(b) can be reduced by many parameters. The most important device factors affecting the
turn-on time (rise time plus turn-on delay time) are the doping concentration and thickness of the P-Base layer. By decreasing both of
these parameters, the OS turn-on time can be reduced. Furthermore, the on-state voltage of the OS is decreased as well; however, on
the other side, the fall time and turn-off delay time will be increased remarkably. Moreover, by decreasing the doping level or
thickness of the P-Base layer, the probability of punch-through breakdown within the P-Base layer is increased. Therefore, there is a
trade-off between rise time and on-state voltage parameters in one side and leakage current, fall time, and breakdown voltage
parameters on the other side. The thickness of the P-Base layer for a typical GaAs or silicon OS should be long enough (more than
about 0.5 μm) to avoid punch-through breakdown voltage, and should be short enough (less than about 1 μm for GaAs OS and 1.5 μm
for silicon OS) to be within the effective light penetration depth of the GaAs or silicon material. The typical doping density for the P-
Base layer to obtain the best optimal results is within the range of 1017 to 1018 cm−3. For the purpose of this paper, the optimal point
to achieve the best on-state voltage, breakdown voltage, rise time and fall time is found using Silvaco TCAD modeling and simulations
based on the voltage and current ratings of the OS operating in the cascode structure.

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2.2. Turn-off procedure

The OC GaN FET is turned off when the illumination on the OS is removed. The photogeneration process stops and the voltage
across the collector-emitter contacts of the OS increases. This increasing voltage is dropped reversely across the gate-source contacts
of the GaN FET. Once this voltage exceeds the absolute value of the threshold voltage, the GaN FET turns off rapidly and blocks
almost all the bias voltage. Since the GaN FET device is turned off very fast, it will not allow any high-voltage stress across the OS
device. However, due to parasitic inductances introduced in the package and interconnect between the two devices, there is a small
overshoot voltage across the OS during the cascode turn-off transient time. Therefore, the breakdown voltage of the OS is designed to
be about two times greater than its turn-off overshoot voltage. The turn-off overshoot voltage across the OS can be calculated in the
worst case by the following equation:
di
Vovershoot = Lloop
dt (1)

in which Lloop is the total parasitic inductances in the main current path of the cascode structure and di/dt is the rate at which the load
current is turned off. Lloop is the total parasitic inductances available at drain and source contacts of the GaN FET device plus the
parasitic inductances from collector and emitter contacts of the OS. As an example for the worst case study in this paper, if the loop
inductance is 15 nH and the load current of 10 A is considered to be turned off within 10 ns, then the maximum overshoot voltage is
calculated to be 15 V. Therefore, the breakdown voltage of the OS is designed to be more than about 30 V.
Similar to rise time procedure, the fall time of the entire cascode structure depends on the fall times of both OS and GaN FET
devices. The GaN FET device is turned off much faster compared to silicon- or GaAs-based devices. The fall time of GaAs devices is
generally faster than silicon devices due to direct bandgap nature of GaAs. For indirect bandgap materials, the carrier recombination
process takes place through intermediate trap levels between the conduction and valence bands of the material, which is usually
slower compared to direct bandgap materials. Therefore for high-frequency applications, GaAs as a direct bandgap material com-
pared to silicon, and furthermore with rather narrower bandgap energy compared to GaN, is preferred to be used for the OS device.
The most important device parameter affecting the fall time is the doping concentration and thickness of the P-Base layer. By
either increasing the doping concentration level or thickness of the P-Base layer in the device structure of the OS shown in Fig. 2(b),
we can decrease the fall time and turn-off delay time of the OS; however, on the other hand, the on-state voltage of the OS will be
increased remarkably. Moreover, P-Base layer thickness greater than the light penetration depth of GaAs or silicon can prevent
effective photogeneration process in the OS. Therefore, in order to design the doping concentration and thickness of the P-Base layer,
there is an important trade-off to be considered between turn-on transition time (rise time plus turn-on delay time) and turn-off
transition time (fall time plus turn-off delay time). Furthermore, one needs to consider the trade-off between the on-state voltage drop
and off-state leakage current on the other hand as well. A better understanding of these trade-off adjustments can be explained by
defining the common-emitter current gain for the OS device (with a similar epitaxial layer as a BJT device) as [16]:
1
β= DE NB tB 1 t
DB NE LE
+ 2 ( LB )2 (2)
B

in which DB, NB, LB, and tB are diffusion coefficient, doping concentration, diffusion length, and width of the P-Base Layer, re-
spectively. Similarly, DE, NE, and LE are diffusion coefficient, doping concentration, and diffusion length for the emitter layer. Ac-
cording to this equation, the current gain of the OS device can be increased by either reducing the thickness or doping concentration
of the P-Base layer. Increasing the OS current gain means reduction in the on-state voltage drop under the same rated load current
and also faster turn-on time. On the other hand, decreasing the current gain results in lower off-state leakage current under the same
rated voltage bias and also faster turn-off time.

3. Results and discussion

3.1. Physics, modeling, and default results

Silvaco TCAD software is used to evaluate the operation of the proposed OC GaN FET and the effect of parasitic inductances. The
device structures for both GaN FET and OS are generated in the Athena module of Silvaco TCAD. Then the generated devices are
imported in the mixed-mode module of Silvaco TCAD along with other necessary passive elements, power supply, and optical laser
sources. Parasitic inductances between GaN FET and OS devices and those spray inductances existing in wire connections and device
packaging are also included in the mixed-mode simulations. In Tables 1 and 2, a brief list of important material properties and
physical modeling used in Silvaco TCAD simulations for both GaN FET and GaAs OS devices are provided.
In Fig. 3, a complete mixed-mode circuit for the OC GaN FET evaluated in Silvaco Atlas (mixed-mode module) is shown. The
default approximate values for the parasitic inductances are extracted from Refs. [13] and [14] which were obtained for an electrical
cascode structure with silicon MOSFET in series with GaN FET. One important advantage of optical cascode configuration is that the
gate parasitic inductance, which is the largest inductance in the gate controlling path of EC GaN FET structure according to [12–14],
does not exist in OC GaN FET anymore. In our study, the same approximate values can be used for other parasitic inductances
available in the optical package. However, higher parasitic inductances are also studied to investigate their effect on the overall
switching transitions during rise and fall times. A list of default values for parasitic inductances are provided in Table 3 in which a

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Table 1
Physical parameters used for GaN and GaAs in Silvaco TCAD simulations.
Material Properties Symbol and unit Al0.3Ga0.7N GaN GaAs

Bandgap Eg (eV) 3.96 3.42 1.42

Breakdown field (V/cm) ∼ 4 × 106 5 × 106 4 × 105
Relative permittivity (Dielectric constant) εr 9.35 9.5 12.9
Electron affinity χ (eV) 3.82 4.1 4.07
Mobility of electrons μn (cm2/Vs) 600 1500 8500
Mobility of holes μp (cm2/Vs) 10 30 400
Saturation velocity vsat (cm/s) 1.5 × 107 1.4 × 107 1.2 × 107
Thermal conductivity (W/cmC) ∼ 0.35 1.3 0.55
Intrinsic carrier concentration ni (cm−3) 1.9 × 10−9 1.9 × 10−9 2.1 × 106

Table 2
Physical models and parameters used in Silvaco TCAD simulations [17,18].
Silvaco TCAD Models GaN HEMT GaAs OS

SRH recombination τp = 10 ns τp = 20 ns
pn
RSRH = τn = 10 ns τn = 1 ns
Et − Ei E − Et
τp [n + ni exp( )] + τn [p + pi exp( i )] Et = Ei Et = Ei
kT kT
Auger recombination N/A ACn = 5 × 10−30
RAuger = CAn (n2p − nni2) + CAp (np2 − pni2) ACp = 1 × 10−31
Field-dependent mobility βn = 1 βn = 1
1
1 βp = 1 βp = 1
μn (E ) = μn0 [ μ E
] βn
1 + ( n0 ) βn
νsatn
1
1
μp (E ) = μ p0 [ μp0 E β
] βp
1+( ) p
νsatp
Concentration-dependent mobility N/A Look-up table [17]
Impact ionization An = 2.52 × 108 An = 1.89 × 105
→ →
G = αn |J |n + αp |J |p Bn = 3.41 × 107 Bn = 5.75 × 105
Bn β Bp β Ap = 5.37 × 106 Ap = 2.22 × 105
αn = An exp[−( ) n], αp = Ap exp[−( ) p]
E E Bp = 1.96 × 107 Bp = 6.57 × 105
βn = βp = 1 βn = 1.82 , βp = 1.75
Polarization model and polarization charge at the interface Activated N/A
Strain from lattice mismatch Activated N/A
Complex refractive index N/A SOPRA database [17]

Fig. 3. Complete configuration of the OC GaN FET including parasitic inductances evaluated in Silvaco mixed-mode simulations.

loop inductance (Lloop=LD+Lint+LE+LS) of 3.6 nH is reported for the main current path.
The bias voltage and current for the OC GaN FET structure are considered to be 650 V and 10 A, respectively. The blocking voltage
of the normally-ON GaN FET and OS devices are designed to be 650 V and 30 V, respectively. In Fig. 4, the optical pulse on the OS

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Table 3
Default values (LB) for the package and parasitic inductances shown in Fig. 3.
Inductance LD LG Lint LE LS

Value (nH) 1.9 0.3 0.3 0.5 0.9

Fig. 4. Optical Signal on the OS device and OC GaN FET current for a complete switching cycle.

device and the resulted OC Gan FET current are shown for a complete switching cycle. Default values for the inductances as shown in
Table 3 and a loop inductance of 3.6 nH are considered for the simulation results shown in Fig. 4.
According to Fig. 4, turn-on delay time and rise time of the default OC GaN FET are found to be 2.63 ns and 7.58 ns, respectively.
Turn-on delay is calculated from the onset of laser illumination time to the time when 10% of the final load current (1 A in this work)
is reached. Rise time is considered to be the time from 10% to 90% of the final load current (from 1A to 9A). Similarly, the turn-off
delay time (from the onset of laser turn-off time to 90% load current time) and fall time (from 90% to 10% of the load current) is
found to be 3.41 ns and 3.72 ns, respectively. If a proper packaging technology can be used to reduce the loop inductances [19], faster
rise and fall times can be obtained. The on-state voltages across GaN FET and GaAs OS devices are found to be 2.19 V and 0.31 V,
respectively.
The overshoot voltage on the GaAs OS during turn-off transient time is 6.4 V within about 7 ns. The peak power across the GaAs
OS device reaches about 41 W. Therefore, the average energy dissipated in the GaAs OS during each turn-off is calculated to be about
287 nJ. Similarly, the energy dissipated for the complete structure of the OC GaN FET is calculated from the following equation
during both turn-on and turn-off switching times:
1
EC = max(VCascode × ICascode ) tsw
2 (3)

in which VCascode and ICascode are the voltage and current across the two GaN FET and GaAs OS devices in series, and tsw is the transient
switching time either during cascode turn-on or turn-off. According to the above equation and simulation results, the energy dis-
sipated in the OC GaN FET during turn-on and turn-off times are calculated to be about 9.36 μJ and 6.75 μJ, respectively. The peak
power across the OC GaN FET during turn-on and turn-off times are found to be about 1574 W and 1500 W, respectively.

3.2. Effects of package parasitic inductance

A variety of different inductance values, for all the basic inductances (LB) shown in Table 1, from 0.5 LB to 5 LB has been studied
and simulated. Here, LB represents all the default basic parasitic inductances including LD, LG, Lint, LE, and LS. In Fig. 5, the OC GaN
FET current curves during turn-on transient time considering different parasitic inductances from 0.5 LB to 5 LB are shown. The delay
in turn-on for all of the different parasitic inductances is about the same (from 2.29 ns to 4.24 ns); however, the rise time is affected
remarkably. By increasing the base parasitic inductances from 0.5 LB to 5 LB, the rise time is increased from 2.29 ns to 20.2 ns.
In Fig. 6, the power curves across the OC GaN FET for different parasitic inductances from 0.5 LB to 5 LB are shown during the

Fig. 5. OC GaN FET current during turn-on transient time for different parasitic inductances.

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Fig. 6. OC GaN FET power during turn-on transient time for different parasitic inductances.

turn-on time. According to Fig. 6, the maximum power for all different cases are about 1500 W; however, the dissipated energy in the
cascode structure during turn-on time is increased from about 7.28 μJ to 22.89 μJ by increasing parasitic inductances from 0.5 LB to 5
LB.
Similar to the study during cascade turn-on time, the cascode current curves for different parasitic inductances during turn-off
transient time are shown in Fig. 7. The delay in turn-off is increased from 3.38 ns to 4.14 ns by increasing the parasitic inductances
from 0.5 LB to 5 LB. Fall time is also increased generally from 3.72 ns to 4.53 ns; however, fall time for the parasitic inductance of 0.5
LB is a bit increased to 3.89 ns due to the slower transition to steady state and tail current as shown in Fig. 7.
In Fig. 8, the power curves across the OC GaN FET for different parasitic inductances from 0.5 LB to 5 LB are shown during the
turn-off time. The energy dissipated in turn-off switching is increased from 6.75 μJ to 8.63 μJ while the peak power is about 1500 W
for all different cases.
The overshoot voltage on GaAs OS is also increased when the parasitic inductances are increased. This is very important since the
breakdown voltage of the GaAs OS device should be designed based on this overshoot voltage during cascode turn-off transient time.
In Fig. 9, the voltage across GaAs OS is shown during OC GaN FET turn-off time. As shown, the peak voltage on the GaAs OS is
increased from 4.46 V to 12.51 V by increasing all the parasitic inductances from 0.5 LB to 5 LB. The breakdown voltage of the GaAs
OS (more than 25 V) is designed to be about two times of the overshoot voltage in the worst case (12.51 V).

3.3. Comparison between OC and EC GaN FET structures

Although higher package parasitic inductances result in increased turn-on and turn-off times and consequently increased
switching losses, it is worth to compare the switching behavior of the proposed OC GaN FET with the conventional EC GaN FET. In
the conventional EC GaN FET structure, a low-power MOSFET device is used instead of the OS device. Furthermore, positive electrical
signal is used to turn on the EC GaN FET and zero-bias voltage is applied to turn off the structure. According to [12–14], gate
inductance of the low-power MOSFET (about 3.1 nH) has the largest value in EC GaN FET structure. Combined with the gate
capacitance of the MOSFET, a large oscillation is observed across the EC GaN FET especially when the structure is being turned off.
However, in the proposed OC GaN FET configuration, neither gate inductance nor gate capacitance does not exist. Therefore, a much
smoother transition is observed in the Silvaco TCAD simulations.
In Fig. 10, the GaN FET current curves during turn-on transient time in both OC and EC structures are shown. The EC GaN FET
with a default parasitic inductance (LB) shows a slower delay in turn-on but a faster rise time compared to the OC GaN FET with
similar condition. However, the turn-off behavior of the EC GaN FET is remarkably deteriorated compared to the OC GaN FET. In
Fig. 11, the GaN FET current curves are shown during turn-off transient time. A significantly larger oscillation is observed for the EC
GaN FET which is mainly attributed to the combination of gate parasitic inductance and gate-source capacitance of the low-power
MOSFET. Therefore, a significantly lower switching loss is expected to be obtained using the proposed OC GaN FET structure.
It should also be noted that larger oscillation during turn-off time results in higher voltage drop across the MOSFET in the EC GaN
FET structure. In Fig. 12, the voltage across the OS device in OC GaN FET is compared with the voltage across the MOSFET in EC GaN
FET during turn-off time. As shown, an overshoot voltage of about 24 V is dropped across the MOSFET in EC GaN FET which is about

Fig. 7. OC GaN FET current during turn-off transient time for different parasitic inductances.

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Fig. 8. OC GaN FET power during turn-off transient time for different parasitic inductances.

Fig. 9. Voltage across the GaAs OS device in OC GaN FET structure during turn-off transient time for different parasitic inductances.

Fig. 10. Comparison of GaN FET current during turn-on transient time for OC and EC structures.

Fig. 11. Comparison of GaN FET current during turn-off transient time for OC and EC structures.

4 times of the overshoot voltage dropped across the GaAs OS in OC GaN FET with a similar condition. Therefore, a MOSFET with
higher voltage rating is required to be used in the conventional EC GaN FET structure.

4. Conclusion

In this paper, a novel optically-activated cascode configuration is introduced for normally-on GaN FET devices to offer a final
normally-off configuration. The turn-on and turn-off procedures for the proposed OC GaN FET is similar to that of EC GaN FET except
that the electrical signal is now replaced with an optical signal. Not only this proposed structure operates under the single-biased
condition, but also it utilizes cost-effective IR lasers instead of expensive UV light sources. The effect of parasitic inductances during

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Fig. 12. Comparison of voltage across the OS and MOSFET devices in OC and EC GaN FET structures, respectively.

both turn-on and turn-off times are investigated in this paper. By increasing the default basic parasitic inductances, the rise and fall
times are increased remarkably which results in higher switching power loss and dissipated energy. By increasing the basic default
values for the parasitic inductances from 0.5 LB to 5 LB, the dissipated energy is increased from 7.28 μJ to 22.89 μJ during turn-on and
from 6.75 μJ to 8.63 μJ during turn-off, respectively. Furthermore, the overshoot voltage across the GaAs OS device is increased from
4.46 V to 12.51 V. This study is important in order to design the required breakdown voltage for the OS device which needs to be
typically more than about two times of the overshoot voltage in the worst case. Finally, a comparison between OC and EC GaN FET
structures is provided in this work. Although EC GaN FET is showing slightly better performance compared to OC GaN FET during
turn-on time, but a significantly larger oscillation and higher voltage drop is observed for the EC GaN FET during turn-off time.
Therefore, not only larger switching loss is expected using the conventional EC GaN FET but also a MOSFET with higher voltage
rating is required.

Conflict of interest

None.

Acknowledgment

The authors would like to thank Transphorm Inc. for providing helpful discussion and datasheet of the stand-alone normally-ON
GaN FET device.

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