1ns/1ps,100ns/100ps,10n Functions Tasks - Can enable (call)

s/1ps timescale in Verilog - Can enable (call) just other tasks and functions -
another function (not
task) - Execute in 0
simulation time - No
timing control statements
allowed - At lease one
input, none output
- Return only a single
value - Synthesizable
May execute in non -zero
simulation time- May contain
any timing control
statements- May have
arbitrary (none, one ormany)
inputs, outputs, or inouts
- Do not return any value
Not synthesizable

Delay Used to delay statement by specified amount of

simulation time, Event Control @
Delay execution until event occurs
Event may be single signal/expression change
Multiple events linked by or
Both - defined in a module, local to the module can
have local variables (registers, but not nets) and
events, do not contain initial or always statements,
they are only blocked by “begin …end”.,are called
from initial or always statements or others task and
functions.

Shifter Keywords: task, endtask

MooreFSM 101 Dectector
module moore_detector( input x, rst,
clk, output z);
localparam [1:0]
reset=0, got1=1, got10=2, got101=3;
reg [1:0] state, next_state;
always @(*)
case (state)
reset:
if (x=1'b1) next_state = got1;
else next_state= reset;
got1:
if (x=1'b1) next_state = got1;
else next_state = got10;
got10:
if (x=1'b1) next_state =got101;
else next_state= reset;
got101:
if (x=1'b1) next_state = got1;
else next_state = got10;
default:
next_state = reset;
endcase // case(state)
//---State FF Transition (current state)
always @(posedge clock)
if (reset ==1'b0) state <= reset;
else state <= next_state;
assign z= (state== got101) ? 1:0;
endmodule
module FSM(o, a, b);
output o; reg o; input a, b; reg[1:0]state;
always @(posedge clk or reset)
if (reset) state <= 2'b00;
else case (state)
2'b00: begin state <= a? 2'b00: 2'b01;
o <= a & b; end
2'b01: begin state <= 2'b10; o <= 0;
end endcase
module traffic_light(HG, HY, HR, FG,
FY, FR,ST_o, tl, ts, clk, reset, c) ;
output HG, HY, HR, FG, FY, FR, ST_o;
input tl, ts, clk, reset, c ;
reg ST_o, ST ; reg[0:1] state, next_state ;
parameter EVEN= 0, ODD=1 ;
parameter S0= 2'b00, S1=2'b01,
S2=2'b10, S3=2'b11;
assign HG = (state == S0) ;
assign HY = (state == S1) ;
assign HR = ((state == S2)||(state == S3)) ;
assign FG = (state == S2) ;
assign FY = (state == S3) ;
assign FR = ((state == S0)||(state == S1)) ;
Parameters are constants. There are two types of parameters: module parameters and specify parameters.
Parameters are not variables, they are used for “per instance” constants.For global constants, using ‘define
… - Examples:adders, multiplexers,
Create:
AnhTuanMien
TrungVipPro
module Mealy101Detector (dataIn, Shifter
found, clock, reset); module shifter(
input dataIn, clock, reset, found; input [7:0] data_in, // 8-bit data input
reg [3:0] state, next_state; input [2:0] shift_amt, // 3-bit shift amount
parameter reset = 3'b000; input dir, // Shift direction (0 right, 1 left)
parameter got1 = 3'b001; output reg [7:0] data_out // 8-bit dataout);
parameter got10 = 3'b010; // Perform the shift operation
always @(state or dataIn) always @(*) begin
case (state) if (dir) begin // Left shift
reset: data_out = data_in << shift_amt;
if (dataIn) next_state = got1; end else begin // Right shift
else next_state = reset; data_out = data_in >> shift_amt;
got1: end end endmodule
if (dataIn) next_state = got1;
else next_state = got10; Counter4bit
got10: module counter_4bit(
if (dataIn) next_state = got1; input wire clk, //Clock input
else next_state = reset; input wire rst_n, //low reset
default: output reg [3:0] out);
next_state = reset; always@(posedge clk
endcase or negedge Ist_n) begin
always @(posedge clock) if (!rst_n) begin
if (reset == 1) state <= reset; // Reset the counter to 0
else state <= next_state; out <= 4'b0000;
assign found = (state == got10 end else begin
&& dataIn == 1) ? 1: 0; // Increment the counter
endmodule // Mealy101Detector out <= out + 1'b1;
end endendmodule
A variables used in behavioral
description
A storage device or a
temporary variable
Types of register: reg :
unsigned integer
variables of varying bit width
integer: 32-bit signed integer
real: signed floating-point
time: 64-bit unsigned integer
// flip-flops S1: if (ts) begin
always@ next_state = S2 ; ST = 1 ;
(posedge clk or posedge reset) end else begin
if(reset) // asynchronous reset next_state = S1 ; ST = 0 ;
begin state = S0 ; end S2: if(tl | !c)begin
ST_o = 0 ; end next_state= S3;ST = 1;
else begin state = next_state ; end else begin
ST_o = ST ; end next_state = S2; ST = 0;
always@ (state or c or tl or ts) end
case(state) // state transition S3: if(ts) begin
S0: if(tl & c) begin next_state = S0 ; ST = 1 ;
next_state = S1 ; ST = 1 ; end end else begin
else begin next_state = S3 ; ST = 0 ;
next_state = S0; ST = 0; end end endcase endmodule
module shifter( Must be used if the procedure
input [7:0] data_in, // 8-bit data input has - any timing control
input dir, // Shift direction (0 right, 1 left) constructs - zero or more than
output [7:0] data_out // 8-bit data output); one output argument
// Wires for internal connections
Keyword:function,endfunction
wire [7:0] left_shift, right_shift;
Can be used if the procedure -
// Left shift by one bit
does not have any timing
assign left_shift[7:1] = data_in[6:0];
control constructs - returns
assign left shift[0]=1'b0;//LSB filled w O
exactly a single value -does not
// Right shift by one bit
have any output
assign right_shift[6:0]= data_in[7:1];
has at least one input argument
assign right_shift[7]=1'b0;//MSBfilled w O primitive latch (q, clock, data);
// Mux to select output output reg q; input clock, data;
assign data_out table // clock data q q+
= dir ? left shift: right_shift; endmodule 01:?:1;
Mos switch:cmos,nmos,pmos,rcmos,rnmos,rpmos 00:?:0;
Bidirectional pass switch:tran,rtran,tranif1,rtranif1 1 ? : ? : - ; // - = no change
endtable endprimitive
module encoder8_3 Gates provide a much closer one-to-one
( encoder_out, enable, encoder_in ); mapping between the actual circuit and the
output[2:0] encoder_out; model.There is no continuous assignment
input enable; equivalent to the bidirectional transfer gate.
input[7:0] encoder_in;
reg[2:0] encoder_out; - Tasks can be used for common Verilog
always @ (enable or encoder_in) code (is used for both combinational and
begin if (enable) sequential logic) - Function are used whe
case (encoder_in) the common code (is used for purely
8'b00000001: encoder_out = 3'b000; combinational logic) - Functions are
8'b00000010: encoder_out = 3'b001;
typically used for conversions and
8'b00000100: encoder_out = 3'b010;
8'b00001000: encoder_out = 3'b011;
commonly used calculations
8'b00010000: encoder_out = 3'b100;
8'b00100000: encoder_out = 3'b101;
8'b01000000: encoder_out = 3'b110;
8'b10000000 : encoder_out = 3'b111;
default: $display("Check input bits.");
end endcase endmodule
- Nets data types present the
physical connections between
devices. A net does not store a
value, it must be driven by a gate
or continuous assignment. If a
net variable has no driver, then it
has a high-impedance value (z). - A net or reg declaration without a <range>
Net data type can be declared by specification is one bit wide; that is, it is
following keywords : wire, wand, scalar.Multiple bit net and reg data types are
wor, supply0, supply1, …- Cannot declared by specifying a <range>, and are
be assigned in an initial or always known as vectors.
block Net data type represent - Vector can be declared at [high# : low#] or
physical connections between [low# : high#], but the left number in the
structural entities. A net must be squared brackets is always the most
driven by a driver, such as a gate significant bit of the vector
or a continuous assignment. - Vectors can be declared only for nets and
reg data types. (Vector declaration for
• Combinational Logic
integer, real, realtime, and time data types
- Logic without state variables
are illegal.)
decoders, encoders • Sequential Logic
- No clock involved - Logic with state variables
VHDL = VHSIC HDL = - State variables: latches, flip-flops, registers, memories
Very High Speed - Clocked
Integrated Circuit HDL - State machines, multi-cycle arithmetic, processors
HaftAdder(Structural) FullAdder1b(Struct) FullAdder3b(Struct) SingleRam2port SingleRam1Port
module HA( module test(a, b, cin, module fa3bit(a,b,cin,s,cout); module single_ram( module single_port_ram(
input a, b, sum, cout);input a, b, input [2:0] a, b; input clk, en, we
input clk,input [3:0]addr, data_in,
output sum, carry); cin; input cin; input [2:0] addr,
assign sum=a^b(xor); output sum, cout; output [2:0] s; input [7:0] din, output reg [3:0] data_out);
assign carry=a&b(and) wire m, n, k; output cout; output reg[7:0] dout); reg [3:0] ram[15:0];
endmodule xor x1(m, a, b); wire [1:0] c; reg [7:0] mem[7:0]; always @(posedge clk) begin
The “assign” statement and a1(n, a, b); test(a[0], b[0], cin, s[0], c[0]); always@(posedge clk) begin if (we) begin ram[addr] <= data_in;
can be used to xor x2(sum, m, cin); test(a[1], b[1], c[0], s[1], c[1]); if (en) begin
and a2(k, m, cin); test(a[2], b[2], c[1], s[2], cout); if( we) mem[addr] <= din;
end
implement both
or o1(cout, n, k); endmodule else dout <= mem[addr]; always @(posedge clk) begin
combinational as well
endmodule end end endmodule data_out <= ram[addr];
as sequential circuits
end endmodule
RegisterFile LIFO FIFO LockControl
Module Register_File module lifo(input clk,input rst,input push,input pop, module fifo module lock_control (lock, A, B, C, D, clk, rst);
(clk,WE,DataW,A1,A2,AData,’ input [7:0] data_in, output reg [7:0] data_out, #(parameter DATA_WIDTH = 8, FIFO_DEPTH = 16) output lock;
RD1,RD2); output reg full, output reg empty); ( input A, B, C, D, clk, rst;
input clk,WE; parameter DEPTH = 16; // Size of the stack input clk, reset, write, read, reg[32:0] counter;
input [4:0]A1,A2,AData; parameter ADDR_WIDTH = 4;// Address width, log2 input [DATA_WIDTH-1:0] data_in, reg skip,fail_1,fail_2,fail_3,fail_4;
input [31:0]DataW; reg [7:0] stack[DEPTH-1:0]; // Stack memory output reg [DATA_WIDTH-1:0] data_out, wire fail;
output [31:0]RD1,RD2; reg [ADDR_WIDTH-1:0] sp; // Stack pointer output reg full, empty); reg [2:0] state, next_state;
reg [31:0] Register [31:0]; // Reset and stack pointer management //Biến đêm và các mảng lưu trữ parameter[2:0] s0=0, s1=1,
always @ (posedge clk) always @(posedge clk) begin reg [DATA_WIDTH-1:0] fifo_array [FIFO_DEPTH-1:0]; s2=2, s3=3, s4=4, s5=5;
begin if (rst) begin reg [$clog2(FIFO_DEPTH):0] write_ptr, read_ptr, count; always @(posedge clk) begin
if(WE) #1=write, 0=read sp <= 0; empty <= 1; full <= 0; // Logic cập nhật FIFO if (rst==1) state= s0;
Register[AData] <= DataW; end else begin // Push operation always @(posedge clk or posedge reset) begin else state= next_state;
end if (push && !full) begin if (reset) begin if (skip==1) counter= 0;
assign RD1 = Register[A1]; stack[sp] <= data_in; sp <= sp+ 1; empty <= 0; write_ptr<= 0; read_ptr<= 0; count <= 0; empty <= 1; else counters counter +1;
assign RD2 = Register[A2]; full <= (sp == (DEPTH - 2)); end full <= 0; end
endmodule // Pop operation else if (pop && !empty) begin end else begin always @() begin case(state)
sp <= sp 1; full <= 0; empty <= (sp == 1);| If (write && !full) begin // Ghi dữ liệu se: if (counters=1) begin
ALU32BIT end end end // Data out management fifo_array[write_ptr] <= data_in; next_state=s1;
module ALU_32bits always @(posedge clk) begin write_ptr<= write_ptr + 1; count <= count + 1; skip=1; end else begin
(S, A, B, M, S1, S0); if (pop && !empty) begin data_out <= stack[sp-1]; if (read && !empty) begin // Đọc dữ liệu next_state= s0;
output reg [31:0] S; end end endmodule data_out <= fifo_array[read_ptr]; skip=0; end
input [31:0] A; read_ptr<= read_ptr + 1; count <= count - 1; s1: if (counter==1) begin
input [31:0] B; Continuous assignment, which assigns values to end //Cập nhật tín hiệu trạng thái next_state=s2;
nets. Procedural assignment, which assigns empty <= (count = 0); full <= (count == FIFO_DEPTH); skip=1; end else begin
input M, S1, S0;always values to variables. end end endmodule next_state= s1;
@(A, B, M, S1, S0) begin skip=0; end
case ({M, S1, S0}) s2: if (counter==1) begin
3'b000: S = ~A; next_state=s3;
3'b001: S = A&B; skip=1; end else begin
3'b010: S = A^B; next_state= s2;
3'b011: S = A|B; skip=0; end
3: if (counter==1) begin
3'b100: S = A+1; Blocking Assignment: Thường next_state=s4;
3'b101: S = A+B; được sử dụng trong khối skip=1; end else begin
3'b110: S = A-B; procedural để đảm bảo thứ tự
next_state= s3;
thực hiện đúng.Non-Blocking
3'b111: S = A-1; Assignment: Thường được sử skip=0; end
default: S=0; dụng trong các khối procedural s4: if (fail==1) begin
endcase end endmodule đề mô hình các phép gán đồng next_state= s0;
Two basic forms of behavioral assignments:
thời và tránh các điều kiện đua. skip=1; end else begin
1.Continuous assignment, which assigns values to nets. next_state=s5;
Continuous assignments drive nets and are evaluated and updated whenever skip=1; end
an input operand changes value. s5: if (counter==3) begin
2.Procedural assignment, which assigns values to variables. next_state=s0;
Procedural assignments update the value of variables under the control of the skip= 1; end else begin
procedural flow constructs that surround them. next_state= s5;
skip=0; end
primitive multiplexer module operation; module shifter; default: begin
Procedural assignment
(mux, control, dataA, parameter delay = 10; define LEFT_SHIFT1'b0 next_state=s0;
Module bcd_counter
dataB); reg [15:0] A, B; define RIGHT_SHIFT 1'b1 skip=0; end
(count,ripple_out,clr,clk) ;
output mux; reg [15:0] AB_AND, AB_OR, reg [31:0] addr, left_addr, endcase
output [3:0] count ;
input control, dataA, dataB; AB_XOR; initial right_addr; end
output ripple_out ;
table $monitor( …); reg control; always @(*) begin
reg [3:0] count ;
control dataA dataB mux Initial begin initial begin…end case (state)
input clr,clk ;
010:1;011:1; … always @(addr)begin s1: fail 1 = !(B==1&&D==0&&A==0&&C==0);
wire ripple_out
01x:1;000:0; end left_addr = s2: fail 2 = !(B==1&&D==1&&A==0&&C==0);
= (count == 4'b1001) ? 0:1 ;
001:0;00x:0; always @(A or B) begin shift(addr, `LEFT_SHIFT); s3: fail 3 = !(B==1&&D==1&&A==1&&C==0);
// combinational
101:1;111:1; bitwise_oper(AB_AND, AB_OR, right_addr= s4: fail 4 = !(B==1&&D==1&&A==1&&C==1);
always @ (posedge clk or
1x1:1;100:0; AB_XOR, A, B); end shift(addr,`RIGHT_SHIFT); default: begin
posedge clr)
110:0;1x0:0; task bitwise_oper; end fail_1= 0; fail_2= 0; fail_3= 0; fail_4= 0; end
//combinational+sequential
x00:0;x11:1; output [15:0]ab_and,ab_or,ab_xor; function [31:0] shift; endcase
if(clr) count = 0 ;
endtable endprimitive input [15:0] a, b; input [31:0] address; assign fail= fail_1||fail_2||fail_3||fail_4;
else if (count == 4'b1001)
begin input control; assign locks (state==s5)?1:0;
count = 0 ;
#delay ab_and = a & b; begin end endmodule
else count = count + 1 ;
endmodule ab_or = a | b; shift=(control==`LEFT_SHIFT)
ab_xor = a ^ b; ?(address<<1) : (address>>1);
end endtask endmodule end endfunction endmodule