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PCB Design for External
DDR Memory
80-VT310-10 Rev. A
Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm
or its subsidiaries without the express approval of Qualcomm’s Configuration Management.
Confidential and Proprietary – Qualcomm Technologies, Inc.
NO PUBLIC DISCLOSURE PERMITTED: Please report postings of this document on public servers or websites to: DocCtrlAgent@qualcomm.com.
Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm or its subsidiaries without the express approval of Qualcomm’s
Configuration Management.
Not to be used, copied, reproduced, or modified in whole or in part, nor its contents revealed in any manner to others without the express written permission of Qualcomm
Technologies, Inc.
Qualcomm is a trademark of QUALCOMM Incorporated, registered in the United States and other countries. All QUALCOMM Incorporated trademarks are used with
permission. MSM is a trademark of Qualcomm Incorporated, registered in the United States and other countries. Other product and brand names may be trademarks or
registered trademarks of their respective owners.
This technical data may be subject to U.S. and international export, re-export, or transfer (“export”) laws. Diversion contrary to U.S. and international law is strictly prohibited.
Qualcomm Technologies, Inc.
5775 Morehouse Drive
San Diego, CA 92121
U.S.A.
Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 2
Revision History
Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 3
Agenda
1 Overview 6
2 Introduction to the Memory Interface 9
3 PCB Memory Bus Design Guidelines 18
4 PCB Design Example 59
5 Frequently Asked Questions (FAQ) 82
Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 4
Terms and Definitions
Term Definition
Processor Qualcomm Technologies, Inc. (QTI) ICs – MSM™, APQ, MPQ, and MDM
Controller QTI ICs – MSM, APQ, MPQ, and MDM. Controllers drive the bus in WRITE mode.
DRAM DRAM memory IC packages. DRAM drives the bus in READ mode.
DDR; LPDDR Double data rate and lower power double data rate memory standard.
Reference plane The metal plane closest to a signal trace. It is a GND plane most of the time, but can be a
power plane too.
Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 5
Section 1
Overview
Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 6
Scope and Intended Audience
This document is intended for engineers who are designing with QTI devices driving
the LPDDR2/LPDDR3 external memory interface. This document describes the
fundamental DDR memory channel, and demonstrates PCB design techniques and
strategies that lead to better signal integrity performance.
Sec. 1 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 7
Section 2
Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 8
External Memory Interface for Mobile Devices
The CPU needs memory to store, access, and compute data.
DRAM components provide high data bandwidth to enable fast data access.
DDR and LPDDR
DDR is used mostly for PCs. VDDQ = 1.8 V, 1.5 V, and 1.35 V
LPDDR was created for mobile devices to reduce power consumption. VDDQ = 1.2 V
PoP memory, stacked memory, and external memory
This document only covers the external memory bus design.
Sec. 2 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 9
External Memory Interface Example for Mobile Devices
Sec. 2 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 10
Memory Speed
DDR
Data is transferred at the rising and falling edge of CLK. Therefore, the data rate is double
the clock frequency.
– LPDDR2 at 533 MHz has a data rate of 1066 MT/s (mega transfers/s).
Higher data rate → smaller PCB area → more stringent timing requirement → PCB
CAD is more important.
Sec. 2 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 12
Memory Topology (2 of 2)
PCB dominates the channel because its trace length is the longest.
Longer trace length → more crosstalk, jitter, and other problems.
QTI
DRAM
MSM/APQ/MDM PCB
package
package
Sec. 2 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 13
Waveform and Eye Diagram (1 of 2)
Time domain
waveform
Sec. 2 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 14
Waveform and Eye Diagram (2 of 2)
Eye diagram
The eye diagram is a very useful tool for assessing signal integrity.
Overshoot, undershoot,
crosstalk, impedance
control
Sec. 2 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 15
Design Workflow
Follow QTI’s design guidelines closely and design the PCB layout to achieve
successful memory bus design.
No
Sec. 2 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 16
Section 3
Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 17
PCB Stack-up
Creating the PCB stack-up is the first step in designing a PCB.
The stack-up drives the layers that are suitable for DDR memory bus routing.
Factors to consider:
Cost
Performance target
Number of build-up layers and core layers
Design constraints for signal layers
Whether the first layer is flooded by a VSS plane
Impedance control
S
Popular PCB stack-up choices G
S
10+ Layers
P
2-4-2 : Core via from L3 to L6
G ?? G
S
1-4-1 : Core via from L2 to L5 S
S ?
1-2-1 : Core via from L2 to L3 PG
S S
G
P
S
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 18
PCB Stack-up: 2-4-2
2-4-2 stack-up, GSSGS 2-4-2 stack-up, SGSGS
G S
S G
S S
PG PG
S S
PG PG
Cons • May need up to three layers for signal • May need up to three layers for signal
routing routing
• Higher cost • Higher cost
• L1 GND plane may be less than ideal • Impedance control can be a challenge for
• Crosstalk in dual stripline traces L3 traces
• Sensitive to design constraint (u-strip and
stripline)
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 19
PCB Stack-up: 1-4-1 and 1-2-1
1-4-1 stack-up
1-2-1 stack-up
S
S S
G G
S
PS
P
SG
G
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 20
PCB Stack-up Summary
The first step in the board design is picking the right PCB stack-up.
Choose the PCB stack-up wisely based on cost/performance goals. Plan the DDR
memory bus design based on the desired PCB stack-up.
Each stack-up has its own pros and cons. The designer must understand the goal.
After a stack-up is chosen, performance is likely bounded.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 21
PCB Topology (1 of 3)
For the LPDDR2/LPDDR3 memory bus on the PCB, there are two likely topologies:
One DRAM component – it can be single rank or dual rank.
Two DRAM components – they are dual rank.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 22
PCB Topology (2 of 3)
One DRAM component on the PCB (the most common case).
CS1/CE1 is only needed if the DRAM is a dual rank device.
DQ[0:31]
Controller package DQS/b[0:3] DRAM
DM[0:3] package
QTI
MSM/APQ/MDM Command/address
CK/b
CS0, CE0
CS1, CE1
Route DQ[0:7], DM0, and DQS/b0 as Byte0, DQ[8:15], DM1, and DQS/b1 as Byte1,
DQ[16:23], DM2, and DQS/b2 as Byte2, and DQ[24:31], DM3, DQS/b3 as Byte3.
Route all command/address, CS, CE, CK/b signals as a group.
Signals in a group should be trace length-matched and have the same spacing and
impedance control.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 23
PCB Topology (3 of 3)
Two DRAM components on the PCB.
CS1/CE1/ZQ1 is needed for a dual rank system.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 24
PCB Topology Summary
Find out if the memory channel has one or two DRAM components, and if the
channel is single rank or dual rank.
If there is one DRAM component, route all signals as point-to-point connections. DQ
and C/A groups need to be length-matched and impedance-controlled.
If there are two DRAM components, route signal traces as T topology.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 25
Component Placement (1 of 4)
External DDR memory bus design requires at least two components: the controller
chip and the DRAM chip.
Good placement minimizes net crossing and makes routing easier from the
beginning.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 26
Component Placement (2 of 4)
Look at rats nest to gauge the orientation of the components.
Leave some distance between the components for routing convenience.
IPC recommends that component-to-component clearance be at least 40 mil (1 mm).
Vias for layer transition, trace crossing, length matching, and PDN routing may also require
some space.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 27
Component Placement (3 of 4)
Allow space for decoupling capacitors for VDDQ, VDD1, VDD2, and VREF rails.
Allow space for power planes and core vias.
Example below: MSM8909 1-2-1 PCB design.
DRAM
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 28
Component Placement (4 of 4)
In the case of SSGS or GSSG stack-up, the signal traces on adjacent layers is
strongly coupled.
G
S
S
Strongly coupled
G
To reduce crosstalk at near end and far end (NEXT and FEXT), the PCB channel
length needs to be shortened.
Noise = 105 mV Noise = 38 mV
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 29
Component Placement Summary
Orient components to minimize “rats nest” crossing.
Allow space for decoupling capacitors, core vias, VDD/VSS plane, and delay tuning.
Shorter channel length → lower crosstalk.
Balance routing flexibility and space reduction. Closer is not always better.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 30
Impedance Target (1 of 2)
What is the impedance target of the transmission line?
Refer to the design guidelines. Usually 50 Ω nominal impedance.
Usually ±10% of variation is allowed.
Trace impedance parameters
Trace width
Trace thickness
Dielectric layer thickness (substrate height in micro-strip and stripline)
Dielectric material property
Reference ground plane continuity (voiding)
Manufacturers usually provide impedance calculation for a particular PCB stack-up.
They can provide guidance on what needs to be done to achieve 50 Ω signal trace
impedance on different signal layers in the stack-up. For differential pairs, they also provide
trace-to-trace space to achieve 100 Ω differential impedance.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 31
Impedance Target (2 of 2)
Example 1: 8-layer 2-4-2 stack up sheet from vendor
Vendor-specified trace
width and separation to
achieve Z target at each
layer.
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Impedance Parameters
Understand effects of trace impedance parameters
Trace width: Wider trace width → lower trace impedance.
– Rule of thumb: Trace width increases by 20%, impedance drops by 7%.
Trace thickness: Thicker trace → lower trace impedance.
– Rule of thumb: Trace thickness increases by 20%, impedance drops by 1 Ω.
Dielectric layer thickness (substrate height in micro-strip and stripline): Thicker dielectric layer
→ higher trace impedance
– Rule of thumb: Microstrip layer thickness increases by 20%, impedance increases by 10%.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 33
Impedance Parameters
Understand the effects of trace impedance parameters.
Dielectric material property: higher dielectric constant → lower trace impedance
– Material property is usually fixed. Work with the PCB manufacturer to choose the right
material.
Reference ground plane continuity: Continuous ground plane → better impedance uniformity.
– Use the solid ground plane close to signal trace as much as possible.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 34
Effects of Trace Impedance
Follow the design guidelines for proper trace impedance.
Transmission line
Z0 = 50 Ω
Driver Vout
Uniform 80 Ω trace
Uniform 50 Ω trace
Longer rise/fall time
No overshoot and
undershoot
Uniform 30 Ω trace
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 35
Impedance Control Summary
Trace impedance is important for achieving desired transient behavior. Engineers
need to know what the trace impedance target is.
Work with the PCB manufacturer to find design parameters to achieve the
impedance target for each signal layer.
Make sure all signal traces have the same impedance.
Free web-based impedance calculator: http://emclab.mst.edu/pcbtlc2/.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 36
Trace Space (1 of 4)
Trace-to-trace space is the same as trace space.
Trace space increases and crosstalk decreases. This is good for DDR SI performance.
Trace space increases and DDR channel routing requires a larger area on the PCB. This
makes board layout difficult.
Rule of thumb:
– 1 W space = 4% coupling
– 2 W space = 2% coupling
– 3 W space = 1% coupling
Trace width = W
1W space
2W space
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 37
Trace Space (2 of 4)
Trace space has a significant impact on signal integrity.
It is desirable to have wider trace space.
Example: 1 aggressor trace driving at 1.2 V swing. Voltage noise observed at victim trace.
W W W W
1 W space 3 W space
Noise = 62 mV Noise = 15 mV
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 38
Trace Space (3 of 4)
Ideally, trace space should be greater than or equal to 3 W everywhere.
With 3 W space, crosstalk is not a concern for PCB design.
If 3 W space is impossible, maximize the trace space in the routing area.
Evenly distribute the routing space among all traces.
Move vias and adjust their location to maximize trace space.
Before After
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Trace Space (4 of 4)
In the GSSG stack-up, layer 2 and 3 traces are close to each other. Crosstalk will be
high due to adjacent layer coupling.
To alleviate crosstalk in this situation, try spreading the traces by staggering the L3 trace
between the L2 spaces. See the example below:
G
Bad practice: S
Signal traces S
aligned
G
G
Good practice: S
Signal traces S
staggered
G
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 40
Trace Length Match (1 of 4)
Trace length match is important for improving DDR signal skew span.
Tighter trace length match → lower jitter → wider eye.
To the first order, skew span is a function of trace length match.
Crosstalk and impedance discontinuity can also affect signal skew span, but that is a
separate discussion.
Each DQ byte group (DQB0/1/2/3) and CA group signal traces should be matched within the
group.
Improve trace
Large jitter length match Small jitter
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 41
Trace Length Match (2 of 4)
Trace length match for one signal group
Rule of thumb: 1 mm of 50 Ω transmission line has 7 ps propagation delay in the FR4
material.
It is recommended that ±2.5 mm trace length match the target to start the PCB layout.
– It is a good practice to match DQ traces to DQS and match C/A traces to CLK. This
practice guarantees that the trace length difference of the entire signal group is within 5
mm.
To achieve higher performance, set ±1 mm trace length to match the target at the last stage
before PCB release.
– Tightening the trace length match range is only necessary when DDR performance needs
to be improved.
– ±1 mm trace length match is equivalent to ±7 ps in skew span analysis.
Refer to the QTI design guidelines of each chipset for the length match requirement.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 42
Trace Length Match (3 of 4)
Use the constraint manager in the CAD tool to set up the spacing and trace length
tolerance for each signal group.
Cadence Allegro
Constraint Manager
Mentor Graphics
Expedition
Constraint Editor
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 43
Trace Length Match (4 of 4)
Trace length match techniques by Serpentine routing and Trombone routing**
Both methods increase propagation delay by increasing routing length.
The effective propagation delay is similar between the two methods if trace-to-trace space is
larger than 3 W.
If trace space is less than 3 W, the effective delay due to the delay tuning will be reduced.
3 W space
3 W space
**Note: Reference: T. Michalka and J. Shin, “Comprehensive, Scalable Design Guidance for Serpentine Time
Delay Variation in Digital System”, Electronic Components and Technology Conference, 2012.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 44
Trace Space and Trace Length Match Summary
Larger trace space → lower crosstalk → PCB routing may become more difficult.
Use 3 W or more trace space whenever possible.
3 W → 1% coupling
Match trace length for each signal group to ±2.5 mm of DQS/CLK.
Tighten it to ±1 mm if necessary at the last stage of PCB design to improve DDR SI
performance.
Use serpentine and trombone delay tuning to match the trace length.
Keep trace space at 3 W for the most effective propagation delay tuning.
Sec. 3 Confidential and Proprietary – Qualcomm Technologies, Inc. | MAY CONTAIN U.S. AND INTERNATIONAL EXPORT CONTROLLED INFORMATION | 80-VT310-10 Rev. A 45
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Et puis nous sommes rentrés, las de banalités et d’efforts.
Dans le salon, Bernard, son cigare éteint, la mine discrète et ravie, était
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rapprochait de moi et me demandait nettement, faisant allusion cette fois à
la cause de notre rencontre:
—Me permettez-vous, mademoiselle, d’accepter l’offre de votre frère, et
d’aller visiter Valcreux?
Et moi lui répondre de ma bouche:
—Oui, monsieur, je vous le permets.
Il est parti après ça, et comme mon pauvre Bernard, demeuré là dans sa
stupeur, ouvrait la bouche pour une question, je me suis jetée contre sa
poitrine, éclatant en larmes du fond de mon cœur, pendant que lui, tout
éperdu, répétait en me caressant de sa bonne façon maladroite:
—Ma petite sœur!... Ma petite sœur!... Tout s’est si bien passé
pourtant!... Tout s’est si bien passé!...
Et sans doute il avait raison.
AUX LUMIÈRES
—
ET nous arrivons à quelle heure?...
L’homme qui rangeait la collection des petits paquets, dans le filet
du wagon, s’était retourné, le bras levé, gardant au bout de ses doigts un sac
rouge qui dansait.
La question était ordinaire, le ton ne l’était nullement, et c’était à ce ton
surtout qu’il répondait malgré lui en regardant la jeune femme:
—Mais... c’est que... nous voilà seulement passant les fortifications...
—Et des fortifications jusque là-bas, il faut rouler combien de temps?...
—Vous êtes fatiguée?... Demain, à deux heures quarante!...
La seconde phrase avait suivi précipitamment la première, hâtée par le
froncement de plus en plus impérieux des sourcils qui interrogeaient.
Sans répliquer, elle s’était rejetée dans son coin, tandis que lui restait
immobile dans sa pose de statue, avec le petit sac qui sautillait et qui
semblait seul vivant.
Le fracas d’un train qui les croisait le tira de sa torpeur, et, sans rien dire
non plus, il s’assit à son tour.