Lecture Notes Mse 240521 103320

GIST TUM Asia
Institute for Technical Electronics

Technische Universität München
Lecture Notes
Mixed-Signal-Electronics
2011
PD Dr. Stephan Henzler

Dipl.-Ing. Cenk Yilmaz
Prof. Dr. Doris Schmitt-Landsiedel
2 Lehrstuhl für Technische Elektronik, TU München
Mixed-Signal IC Design 3
I Introduction 7
1 Structure of Mixed-Signal Systems . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Discrete-Time Signals, Laplace and z-transform . . . . . . . . . . . . . . . . . 9
3 Upsampling and Downsampling . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 Discrete-Time Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5 z-transform of a Step Function . . . . . . . . . . . . . . . . . . . . . . . . . . 14
II Sample and Hold Circuits 17

1 Errors in Sample and Hold Circuits . . . . . . . . . . . . . . . . . . . . . . . . 17
2 Noise Considerations with Sampled Signals . . . . . . . . . . . . . . . . . . . 19
3 Characteristic Parameters of thermal noise . . . . . . . . . . . . . . . . . . . 20
III Switched-Capacitor-(SC) Circuits 23

1 Concept of Switched-Capacitor Circuits . . . . . . . . . . . . . . . . . . . . . 23
2 Clocking of Switched-Capacitor Circuits . . . . . . . . . . . . . . . . . . . . . 25
3 Impact of Parameter Variations on RC & SC Circuits . . . . . . . . . . . . . 26
4 Realization of Integrated Capacitors . . . . . . . . . . . . . . . . . . . . . . . 26
5 Validity of the SC-Equivalence . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6 Switched-Capacitor Integrators . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.1 Operation Principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.2 Impact of Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3 Impact of Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.4 Analysis Steps for SC-Circuits . . . . . . . . . . . . . . . . . . . . . . . . 36
7 Switched-Capacitor Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.1 Principle of Operation with Offset Compensation . . . . . . . . . . . . . 37
7.2 Superposition of input signals . . . . . . . . . . . . . . . . . . . . . . . . 39
IV Analog-to-Digital and Digital-to-Analog Converter Fundamentals 41

1 Nyquist-Rate Converters and Oversampling Converters . . . . . . . . . . . . . 41
2 Ideal D/A Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3 Ideal A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4 Quantization Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5 Performance Characteristics of Data Converters . . . . . . . . . . . . . . . . . 45
5.1 Static Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.2 Transfer Behavior for Alternating Voltages and Currents . . . . . . . . . 48
5.3 Dynamic Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6 Signed Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
V Nyquist-Rate D/A Converters 53

1 Decoder-Based Converters (Parallel Operation) . . . . . . . . . . . . . . . . . 53
2 Binary-scaled Converters (Weighted Mode) . . . . . . . . . . . . . . . . . . . 55
2.1 Binary-Weighted Resistor Converters . . . . . . . . . . . . . . . . . . . . 56
2.2 Switched-Capacitor Converters . . . . . . . . . . . . . . . . . . . . . . . 57
2.3 Converters with Weighted Current Sources . . . . . . . . . . . . . . . . . 58
2.4 Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3 Thermometer-Code Converters . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.1 Hybrid Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
VI Nyquist-Rate A/D Converters 65

1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2 Integrating A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3 Successive-Approximation Converters . . . . . . . . . . . . . . . . . . . . . . 67
3.1 Charge-Redistribution Converters . . . . . . . . . . . . . . . . . . . . . 68
3.2 Hybrid Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
3.3 Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4 Algorithmic A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5 Flash Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.1 One-Step Flash Converters . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.2 Interpolating A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . 78
6 A/D Converters with Parallel Operation . . . . . . . . . . . . . . . . . . . . . 80
6.1 Two-Step Flash Converters . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2 Pipelined Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3 Parallel Operation of Multiple A/D Converters . . . . . . . . . . . . . . 82
VII Oversampling Converters 83

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
2 Oversampling without Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . 83
3 Oversampling with Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . 86
3.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.2 First-Order Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.3 Second-Order Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.4 Comparison of First- and Second-Order Modulators . . . . . . . . . . . . 90
3.5 Higher-Order Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3.5.1 Non-Cascaded Modulators with Orders > 2 . . . . . . . . . . . . 92
3.5.2 Cascaded Modulators . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.6 Stability and Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.6.1 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.6.2 Tones and Dithering . . . . . . . . . . . . . . . . . . . . . . . . . 100
4 System Architecture of ∆Σ converters . . . . . . . . . . . . . . . . . . . . . . 101
4.1 Signals and Spectra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.2 Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.2.1 Single-Stage Architectures . . . . . . . . . . . . . . . . . . . . . . 104
4.3 Multi-bit Modulator Structures . . . . . . . . . . . . . . . . . . . . . . . 104
4.3.1 Multi-bit Modulators . . . . . . . . . . . . . . . . . . . . . . . . . 104
4.3.2 Dynamic Element Matching . . . . . . . . . . . . . . . . . . . . . 105
4.3.3 Dynamic Calibration of Current Sources . . . . . . . . . . . . . . 105
4.3.4 Digital Error Correction . . . . . . . . . . . . . . . . . . . . . . . 106
5 Σ∆ - D/A - Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6 Continuous Time Σ∆ - Converters . . . . . . . . . . . . . . . . . . . . . . . . 109
7 Bandpass - Σ∆ - Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Chapter I
Introduction
It is the basic task of electronic circuits to process analog input signals and generate analog
output signals. This also applies for systems which are digital in the eyes of their users. For
example, in the reading head of a hard disk drive or a semiconductor memory, very elaborate
analog circuitry is employed to access (i.e., read and write) data. Given that the structures
used in microelectronics keep getting smaller, digital signal processing is becoming cheaper,
while at the same time more powerful. Thus, completely analog processing has moved more
and more into the background, whereas the mixed-signal parts of electrical circuitry, which
serve as connection between the analog surroundings and the digital signal processor or the
data processing unit, have increased in importance. While, with the use of CAD tools, digital
circuitry can be designed with a high degree of automation, the design of the analog and mixed-
signal parts of the electrical circuit still requires a lot of craft and expertise. Although these
parts are rather small in terms of number of transistors or area on the chip surface, they are
a highly important elements in design time and overall cost considerations. As a result of
this trend, the International Technology Road map of Semiconductors now contains a growing
section on mixed-signal systems and the technologies associated with them [2]. The special
Analog CMOS (or possibly BiCMOS) in digital processes:

⋆ Low supply voltage
⋆ No high precision, area-efficient passive elements or increased process cost
⋆ MOSFETS with high-field effects →
(µ(VG ), Vth (L, W, VDS ), in the future: IGate , IDB . . . )
Availability of high clock frequencies →
Switched-Capacitor circuits, easy realization of oversampling;
Signal corruption due to clocks and digital signals;
Some signal processing functions (e.g. filters, error correction etc.)
can be executed in the digital part of the circuit.
Table I.1: Conditions for mixed-signal circuits in a System-on-a-Chip(SoC)
7
Anti−aliasing−filter Digital code Smoothing

V V V
111
101
t 011 t t t
000
Digital
LPF S/H Discretization DAC LPF
Analog Signal Processing Analog
Input Output
Figure I.1: Typical Structure of a mixed-signal system
conditions that apply for analog circuits in system-on-a-chip(SoC) with digital technologies,
with the possibility of digital signal processing and the existence of disturbances caused by
digital signals, are summarized in table I.1.
1 Structure of Mixed-Signal Systems
Fig. I.1 shows the basic structure and the signal forms that appear in a mixed-signal system.
The input signal v(t) has to pass a low-pass anti-aliasing filter to remove high-frequency com-
ponents, which would cause corruption by aliasing.
The sampling theorem states that aliasing is avoided if
1
fg < fs (1.1)
2
where fs is the sampling frequency and fg is the bandwidth of the signal. In analog electronics,
this relation is often called Nyquist-criteria (Nyquist-Shannon sampling theorem). The sample
& hold unit (S/H) samples and holds the signal at discrete time-steps, i.e. an analog signal
which is still continuous-time, but constant for certain amounts of time, is derived from the
continuous-time input signal. The next block, the actual analog-to-digital converter, generates
a discrete-time and discrete-value digital signal. Usually, the next block is the digital signal
processing unit. In this figure, the signal is routed directly to the digital-analog converter,
which generates an analog signal. Yet, this does not have the initial sine shape, but is divided
into steps, so its harmonic content is high. This is eliminated in the subsequent low-pass filter
and the final output shows the original sine shape. Low-pass filtering the input or output sig-
nals can be omitted if the input signal is already limited in its bandwidth due to the properties
of the device generating the signal (e.g. a sensor, etc) or if the device connected to the output
implicitly provides low pass filtering (e.g. a loudspeaker), respectively.
Figs. I.2 and I.3 show a mixed-signal system with the signal forms at the corresponding nodes
according to [1]. The individual signals are explained in table I.2.
s(t) x[n] = xc(nT)

ys (t) ysh(t)
y[n]
xc(t) xs(t) Convert to Convert to Analog yc (t)
discrete−time DSP impulse Hold low−pass
sequence train filter
(a)
x sh(t) x[n] = xc(nT) ysh(t)

y[n]
xc(t) Sample D/A Analog yc (t)

A/D
and DSP converter low−pass
converter
hold with hold filter
(b)
Figure I.2: DSP-system, signals are labeled: a. conceptual structure b. typical physical
realization
2 Discrete-Time Signals, Laplace and z-transform

The value of a discrete-time function x[n] = x(t = nT ) is only defined for certain discrete
points in time t = nT . Thus, a discrete-time signal can be put in the form of a weighted series
of impulses.: X
x(t) = x[n]δ(t − nT ) (1.2)
n
The Fourier Transform re-expresses a continuous-time function x(t) one to one into a continuous
non-periodic spectrum X(ω):
Z +∞
X(ω) = x(t)e−jωt dt (1.3)
−∞
The spectrum can be transformed back into the time domain by employing the formula
Z +∞
1
x(t) = X(ω)ejωt dω (1.4)
2π −∞
The Laplace transform, which is defined by

Z ∞
X(s) := x(t)e−st dt (1.5)
−∞
is a generalization of the Fourier transform which shows improved features with regards to
convergence. In order to be able to make use of the known advantages of an analysis in
the frequency domain also for discrete-time signals, a Fourier analysis of discrete-time signals
Xc(f)
xs(t) A
xc(t)
f0 fs f
Pulse width 0 t
A Xs(f)
T
f0 fs 2f s f
x[n]
4 5 6 7 8
A X(Ω)
0 1 2 3 n
T
2π 4π Ω
(2π f0)/ fs
xsh (t)
Xsh(f)
A
t
f0 fs 2f s f
Figure I.3: Typical signal forms (curves) and corresponding frequency spectra
or sequences of values is useful. The discrete-time signal from 1.2 is inserted in the Fourier
transformation formula 1.3:
Z +∞ X ∞
X(ω) = x(nT )δ(t − nT )e−jωt dt (1.6)
−∞ n=−∞
∞
X Z +∞
= x(nT ) δ(t − nT )e−jωt dt (1.7)
n=−∞ −∞
X∞
= x(nT )e−jωnT (1.8)
n=−∞
The result of this is the Fourier transform of the discrete-time signal x(nT ) or the sequence of
values x[n] respectively. Since only the series of values x[n] is of importance in the discrete-
time domain, the frequency is often normalized to the sampling frequency fs = T1 . With the
normalized angular frequency Ω = 2πf fs
the Fourier transform is given by
∞
X
X(Ω) = x(nT )e−jΩn (1.9)
n=−∞
xc (t) analog, time continuous input signal

s(t) periodic pulse train with sample time T , T = f1s
xs (t) sampled signal with the same frequency spectrum as xc (t), but the
spectrum of the base band repeats every fs . It is assumed
that there is no oversampling.
x[n] sampled signal; the sampling frequency is normalized to 1: Ω = 2π ffs
xsh (t) input signal after sample & hold, same frequency spectrum
as xs (t) multiplied by a sinx x -function. xsh (t) is
the output signal of the sample & hold unit, while x[n] is the output signal
of the A/D converter, if effects of digitizing can be neglected.
Table I.2: Description of the signals in Fig. I.1
Thus, the spectrum of a discrete-time signal is an infinite series of weighted complex exponential
functions. It can easily be shown that the spectrum spreads infinitely and that it is periodic
with period 2π. If the discrete-time signal is seen as a sampled continuous-time signal, it
becomes clear that the resulting spectrum is generated by replicating the original spectrum at
center frequencies Ω = 2πk.
Using the formula
+π
1
Z
x[n] = X(Ω)ejΩn dΩ (1.10)
2π −π
the discrete-time signal can be recovered in the time domain. The Fourier transform of discrete
signals can be generalized similar to the way it is done for continuous-time signals (equivalent
to continuous-time Laplace transform). This generalized transform
∞
X
X(z) = x[n]z −n (1.11)
n=−∞
is commonly called z-transform and is preferred over the Fourier transform because of its better
convergence. Moreover, the compact notation makes is easier to use in more complex calcu-
lations. z-transform and Fourier transform of discrete-time signals are formally analogous for
z = ejΩ = ejωT .
Normalization of the sampling frequency results in discrete-time signals having an angular fre-
quency Ω measured in units of radians/sample, while the frequency of discrete-time signals is
measured in units of cycles/second or radians/second.
Thus, for example, a sinusoidal signal of 1 kHz sampled at 4 kHz will change by 12 π radi-
ans between samples. Therefore, the sampled discrete-time signal has a frequency of 12 π radi-
ans/sample. Further examples of sampled discrete-time sinusoidal signals are shown in Fig. I.4.
It shows that discrete-time signals are not unambiguous because adding 2π to the normalized
frequency results in the same pulse train.
Example: A discrete-time signal with an angular frequency of 41 π radians/sample is identical to
a signal with 94 π radians/sample. Thus, only the frequency components of discrete-time signals
x[n] x[n]
10 15
1 5 10 15 n 1 5 n
0 rad/sample = 0 cycles/sample π /8 rad/sample = 1/16 cycles/sample

(a) (b)
x[n] x[n]
5 15 15
1 10 n 1 5 10 n
π /4 rad/sample = 1/8 cycles/sample π /2 rad/sample = 1/4 cycles/sample

(c) (d)
Figure I.4: Sampling sinusoidal signals with different frequencies
between −π and +π radians/sample are regarded. (In the other case, the sampling theorem
would not be obeyed.)
3 Upsampling and Downsampling
Downsampling is used to decrease the sampling rate and, therewith, the amount of data that
is to be transmitted. On the contrary, upsampling means an increase in the number of samples
per time unit. In the simplest case, the sampling rate is multiplied or divided by an integer
factor, as shown in Figs. I.6 and I.5. In downsampling, certain samples are left out and the
sample rate is reduced. So, the spectrum plotted on the normalized frequency Ω = 2π ffs is
spread, while the corresponding continuous spectrum Xc (f ) remains unchanged. Note that,
although samples are discarded, there is no loss of information as long as the sampling theorem
is obeyed.
For upsampling with the factor L, L − 1 ”zero” values are added between two samples as shown
in Fig. I.6. The normalized spectrum X(Ω) is compressed.
X f [n] x s [n]
L
0 4 8 n 0 1 2 n
L=4
xs (Ω ) X f ( Ω)
π 2π Ω 4π 2π Ω
6 6
0
Figure I.5: Downsampling by an integer factor L. As long as the sampling theorem is obeyed,
there is no loss of information.
xs [n] x f [n]
L
0 1 2 n 0 4 8 n
L=4
X s ( Ω) X f (Ω )
4π 2π Ω π π 2π Ω
6 6
0
Figure I.6: Upsampling by adding zeros
4 Discrete-Time Filters
A discrete time filter generates a filtered discrete-time signal. According to the filter transfer
function, an output series of numbers is derived from an input series of numbers. The most
important parts of discrete-time filters are adders with weighted inputs and delay elements.
As continuous-time filters can be plotted on the s-plane, discrete-time filters can be described
through their transfer function in the z-plane. A simple example is given in Fig. I.7. The
transfer function of this filter is given by the following equation:
bz −1 b
H(z) = = (1.12)
1 − az −1 z−a
The Laplace-transform function of a continuous-time signal can be imagined as an area above
the s-plane. The values above the imaginary axis are the frequency spectrum. Likewise, the
z-transform of a discrete-time variable x[n] can be imagined as a three-dimensional shape above
the z-plane. The spectrum is obtained by setting z = ejΩ , i.e. regarding the values above the
unit circle, starting counterclockwise at point z = 1 on the real axis. Going around the circle
y[n+1]
b
x[n] z −1 y[n]
a
Figure I.7: Example for a simple, first-order discrete-time filter
again will repeat the resulting spectrum.

A continuous-time filter is stable if and only if its poles are on the left half of the s-plane.
Transferring this to discrete-time filters, the imaginary axis is transformed to the unit circle on
the z-plane. Here, the stable area is the area inside this circle. The simple filter from figure I.7
has one pole on the real axis for z = a. So, it is stable if |a| < 1, as it can also be seen in the
transfer function.
5 z-transform of a Step Function
The preceding section contained a description of discrete-time pulse trains that consist of a
single pulse for each point in time the signal is sampled. Naturally, this is an idealized image
because such signals cannot be generated in reality.
The idealized output of a sampling unit (for a detailed discussion, consult chapter II) can be
plotted as a step function. Therefore, the signal is rather a periodically constant continuous-
time signal with steep slopes between the individual samples than a discrete-time signal. This
signal can be related to corresponding sampled signal using the mathematical relationship
∞
X
xsh = xc (nT ) [σ(t − nT ) − σ(t − nT − T )] (1.13)
n=−∞
The step function is time-continuous and its Laplace transform is equal to
1 − esT
Xsh (s) = Xs (s) (1.14)
s
The discrete-time sampled signal and the step function are linked by the transfer function
1 − esT
Hsh (s) = (1.15)
s
This transfer function is often called ‘sample and hold response’ although it only describes the
hold time, i.e. the period during which the signal is saved at the output of the sampling unit.
By substituting s = jω in equation (1.15), the spectrum of the transfer function can be found
equal to
1 sin ωT
Hsh (jω) = T ej 2 ωT · ωT 2 (1.16)
2
The effect of this sinc-function on the spectrum can be seen in Fig. I.3. Nevertheless, it must
not be concluded from this illustration that the signal is distorted by the hold process. A/D
converters need a certain amount of time to generate a digital value from the input signal.
Therefore, the input signal is frozen at the time the signal is sampled. Still, the result of
the conversion is one single discrete-time value, so the transfer function 1.15 has no effect on
subsequent signal processing.
Chapter II
Sample and Hold Circuits
A sample & hold (S & H) circuit is used to sample the value of an analog signal at given points
in time and to store it until the following sampling time (’hold’). Its basic structure is shown
in Fig. II.1.
Vin Chld Vout
Figure II.1: Schematic structure of a sample & hold circuit
1 Errors in Sample and Hold Circuits

While the circuit is in sample mode (acquisition time), the switch is closed and the capacitance
is charged up approximately to the value of the analog input signal at the end of the acquisition
time. When the switch is opened, the sampled value is stored on the capacitor.
In CMOS circuits, the switch is usually controlled by a two-phase clock (for further information,
see chapter III on switched-capacitor circuits). The switch is closed for almost half of the clock
period; the input voltage tracks the output voltage. This S & H circuit is called a Track & Hold
(T & H) circuit. If the output of the S & H circuit is connected to a switched-capacitor circuit
clocked at the complementary frequency, there is no difference in the function of a S & H and
a T & H circuit. Only a small load can be connected to the output of a circuit according to
Fig. II.1. Therefore it is necessary that the subsequent circuit have a high input impedance and
17
φclk
Q1 V’
1
Vin Chld Vout
Figure II.2: Schematic of a Sample & Hold circuit with a voltage follower unity gain buffer
connected to the output.
an input capacitor considerably smaller than the hold capacitor. Most applications, however,
do not fulfill that requirement. For that reason, an operational amplifier (op-amp) with a gain
factor of 1 (unity gain buffer) is connected in series to the output of the S & H circuit, as
shown in Fig. II.2. The accuracy of the S & H circuit is a vital factor for speed and precision
of A/D converters. Sources of possible errors are plotted in Fig. II.3.
Overshoot and settling time S/H output

within specified
tolerance Droop
and feedthrough
vINmax
vIN
Pedestal error v OUT
Output slewing
Acquisition time Hold mode
Sample command Hold command

issued issued
Figure II.3: Sources of errors in sample-and-hold circuits
Possible errors in sample mode:

• Limited speed of the output voltage change (output slewing), determined by the slew rate
of the op-amp
• Transient response: Overshoot and settling time, determined by the characteristics of the
op-amp as well - because of strong feedback generated at unity gain, correct frequency
compensation of the amplifier is important for good transient response and short settling
time.
• Other errors may arise because of offset, a gain unequal to 1 and nonlinear amplification.
Possible errors in hold mode:
• Pedestal errors arise because of charge injection and clock-feedthrough when the switch
is opened. One way to reduce this effect is to insert dummy-transistors in series to the
switch.
• Droop: Leakage currents and capacitive feedthrough of unwanted signals may cause a
change in the output voltage while the circuit is in hold mode.
Both errors can be minimized by appropriate layout of the circuit. The accuracy of the S & H
circuit is to a high degree determined by the hold capacitor. Yet, a high capacitance limits the
bandwidth of the circuit.
Deviation from the exact sampling time (Aperture error):
The exact time at which the switch can be considered ‘open’, varies for multiple reasons: One
is that the falling edge of the clock signal may vary (Clock jitter). Furthermore, the time at
which the switch closes depends on the value of the sampled signal. The extent of the aperture
error correlates directly with the frequency of the input signal. For sinusoidal signals, the error
is greatest at a zero crossing, i.e. when dV /dt has the greatest value.
2 Noise Considerations with Sampled Signals

Inherent noise is caused by random fluctuations. In the time domain, noise is characterized by
the mean square variation of a noise variable a(t)
T
1
Z
a2 = lim |a(t)|2 dt (2.1)
T →∞ 2T −T
In the frequency domain, it is characterized by the spectral power density S(f ), i.e. the noise
power in the frequency band with a bandwidth 1 Hz. Both these characterizations are related
by the identity Z ∞
Sa (f ) df = a2 (t) (2.2)
0
so noise power in the frequency domain equals noise power in the time-domain.
Thermal noise, caused by thermal movement of charge carriers in a conductor, occurs in all
kinds of resistors, including wires and non-ideal switches. Ideal capacitances and inductances
are noiseless. Thermal noise is frequency independent up to very high frequencies (white noise).
Additionally, 1/f noise occurs in MOSFETs, which will be disregarded in this lecture.
While the switch is closed, the S & H circuit can be represented by the noise equivalent circuit
of an RC element as shown in Fig. II.4. The resistor itself is assumed to be noiseless; ther-
mal noise generated by the resistor is represented by the noise voltage source VR (drawn as a
hatched circle).
3 Characteristic Parameters of thermal noise

Spectral power density of the noise voltage
SvR = 4kT R (2.3)
Mean square fluctuation of the noise voltage within the frequency band ∆f :
vR2 = 4kT R∆f (2.4)
RMS (Root Mean Square) value of the noise voltage within the frequency band ∆f :
q p
RM S
VR = vR2 = 4kT R∆f (2.5)
A calculation of the noise at the output is possible via a power consideration: the noise power
R
Vn,out
VR2 C
Figure II.4: Noise equivalent circuit of an RC element
spectrum at the output can be derived from the noise power spectrum at the input and the
transfer function.
SvR → Svn,out (2.6)
The spectral power density Svn,out at the output is given by
Svn,out = |H(jω)|2 SvR (2.7)
where H(jω)is the transfer function of the RC element. An integration in the frequency domain
leads to the mean square variation of the output voltage:
2 kT
vn,out = (2.8)
C
RM S
p
As can be seen, the RMS value of the noise voltage at the output equals vn,out = kT /C.
This so-called kT /C noise is independent of R. Its amount is a fundamental limit for the noise
voltage at a capacitance C, if all but the thermal noise of the resistor is disregarded.
In a S & H circuit, the noise power occurring between two sample is irrelevant. The significant
value is the voltage at the hold capacitor at the time the switch opens. Owing to the noise
present
p in the closed switch, the sampled values are subject to variations with an RMS value of
kT /C. Thus, this is also the fundamental limit for the noise voltage of sampled signals using a
capacitance C. It is important to note that this noise voltage is independent of the sample rate
or the voltage of the sampled signal. This fact suggests a way to reduce the noise pof a sampled
signal: The noise voltage of the individual samples has an effective value of kT /C if the
input signal is a DC- or low-frequency signal. An improvement in measurement accuracy can
be achieved by increasing the sample rate and then calculating the average of multiple samples
in subsequent (digital) signal processing: By summing up individual sampled values, the signal
values add up linearly, whereas the noise values add as the root of the sum of squares. This
technique is called oversampling. Its application in oversampling converters will be discussed
in detail in chapter VII.
Chapter III
Switched-Capacitor-(SC) Circuits
1 Concept of Switched-Capacitor Circuits
Ohmic resistors are important components in analog integrated circuits. However, the materials
usually available in digital CMOS process have relatively low resistance. Thus resistors with
medium and large resistance require much chip area and cause considerable costs. Technologies
with analog process options provide additional process steps to realize materials with larger
specific resistivity, but this increases manufacturing cost. The large area of passive resistors
results in parasitic capacitances. Other drawbacks of integrated resistors are strong variations
of their value due to process variations (up to 30%), the temperature dependence and the ther-
mal noise introduced by the resistors.
The switched-capacitor technique replaces ohmic resistors by capacitances and switches real-
ized by field effect transistors. In principle, switched-capacitor circuits realize time-discrete,
continuous valued signal processing functions. The switched-capacitor equivalent to a time
continuous function is valid as long as the clock frequency at the switches is much larger than
the signal bandwidth. Consider the resistor R connecting the nodes N1 and N2 which is shown
in Fig. III.1. The voltage drop vR = vN 1 − vN 2 causes a current iR = (vN 1 − vN 2 ) /R through
the resistor. In an infinitesimal time interval dt, the charge dq = i dt is transfered from node
N1 to node N2 . If the system is only considered at the discrete times t[n] = nT , the charge
transfered during one time step T is equal to ∆q = iT . Of course this is only true if the node
voltages do not change considerably during the time interval T . In a discrete time system,
only the state of the circuit at discrete instances is important. The waveform of the current
i(t) between N1 and N2 does not matter, as long as the transfered charge is well defined. In
Fig. III.2 a network consisting of two switches and one capacitor replaces the ohmic resistor
R. The switches are controlled by two complementary clock signals φ1 and φ2 . At the time
t = nT , the switch S1 is closed and the capacitance is connected to the node N1 , whereas the
switch S2 is open. Half a clock period later, S1 is opened, and S2 connects the capacitor to
23
i φ2 φ1 φ2 φ1
1 R 2 Q = C (V1−V2 )
=iT
i
V1 − V2 i
i=
R
(n−1)T nT t
Figure III.1: Linear resistor between node 1 and node 2. In a discrete time system it does
not matter when and how the charge is transfered
φ1 φ2
i
v1 S1 S2 v2
C
Figure III.2: Switched-capacitor circuit equivalent to a resistor Ref f = T /C. φ1 and φ2 are
non-overlapping clocks with frequency f = 1/T.
node N2 . This results in transfer of the charge

1
q = CvN 1 [nT ] − CvN 2 (n + )T (3.1)
2
from node N1 to node N2 . In a discrete time system this charge transfer has the same result
as a constant current of
∆q C(vN 1 − vN 2 )
i= = (3.2)
T T
Thus, the switched-capacitor network in Fig. III.2 corresponds to an ohmic resistance of Ref f =
T /C. The value of this resistance is determined by the value of the capacitance and the clock
frequency of φ1 and φ2 . It is worth mentioning that a large effective resistor would require an
enormous chip area if implemented as ohmic resistance. In switched-capacitor technique, only
a small capacitance is required, and the area consumption is much smaller.
Other switched-capacitor topologies exist that can be more appropriate, depending on the
circuit topology. Table III.1 shows some implementations and their equivalent resistance values.
circuit equivalent type

resistor
Φ1 Φ2
T
parallel equivalent C transimpedance
Φ1 Φ2
C
T
series equivalent C resistance
or transimpedance
Φ1 Φ2
Φ2 Φ1
T
bilinear equivalent 4C resistance
or transimpedance
1
Table III.1: Switched-capacitor circuits and equivalent resistors; T = fs
2 Clocking of Switched-Capacitor Circuits
Switched-capacitor circuits use two groups of switches that are alternatively opened and closed.
From the operation principle of the simple switched-capacitor circuit described in the last
section it is obvious that both switches must never be closed at the same time. Otherwise the
nodes N1 and N2 would be shorted and an uncontrolled amount of charge would be transfered.
The clock signals φ1 and φ2 must guarantee that always one switch is opened before the other
one is closed. Fig. III.3 shows the principle of such non-overlapping pair of clocks as well as a
simple circuit to generate the two signals from a single phase clock. The time axis is normalized
to the clock period T. The integers n − 2, n − 1, n, n + 1 are sample numbers of the discrete
time signals sampled at the falling edge of clock φ1 . The discrete time signals sampled by φ2
are denoted with numbers n − 32 , n − 21 , etc. In CMOS circuits, often CMOS transfer gates are
used as switches. Then a 4-phase clock system is needed to control the n- and p-MOSFETS of
switches S1 and S2 .
Φ1
Von
Φ
>1 Φ1
Voff
n−2 n−1 n n+1 Delay
Φ2
1
Von Delay
Voff >1 Φ2
n−32 n−12 n+ 12
Figure III.3: Non-overlapping two-phase clock pair and a circuit for the generation of this
clock pair from a single phase input clock.
3 Impact of Parameter Variations on RC & SC Circuits

To demonstrate the impact of process variations on RC and SC circuits, respectively, a simple
first order low pass is discussed: The time constant τ is given by τ = R · C. If both the resistor
and the capacitor are subject to independent process variations, the relative error of the time
constant is given by
∆τ ∆R ∆C
= + (3.3)
τ R C
The relative errors of the resistor and the capacitor contribute directly to the error of the time
constant. If the resistor is realized with a switched-capacitor equivalent with Ref f = T /CSC
the time constant is τ = T · C/CSC .
Neglecting the error of the clock period, e.g. for a quarz based clock, the error can be written
as
∆τ ∆( CCSC )
= (3.4)
τ ( CCSC )
The relative error of the time constant is equal to the relative error of the ratio of the two ca-
pacitances. The latter is much smaller than the error of a single capacitance, as both capacitors
are mainly affected by the same process variations.
4 Realization of Integrated Capacitors

In integrated circuits capacitances can be implemented in various ways. These realizations
have different properties concerning linearity, specific capacitance (capacitance per area), and
cost. The most cost efficient capacitors in (logic) technologies are MOS capacitors (MOS-Cap).
These capacitors are normal field effect transistors where the gate is one electrode. The second
electrode is formed by the shorted drain and source electrode of the transistor. The bulk
terminal is usually shorted to the S/D-node, but it also can be used to tune the capacitance
value. The gate oxide is the thinnest available dielectric layer in a CMOS process. Hence the
specific capacitance of a MOS-Cap exceeds all other realizations. However, the gate capacitance
of a field effect transistor is highly nonlinear which causes distortion in linear signal processing
applications. Compensation techniques using a serial or parallel connection of two MOS-Caps
help to reduce these nonlinearities. If the linearity requirements for a certain application are
very strict, metal-metal capacitors (MIM-Caps) are used. These capacitors consist of two
parallel metal layers separated by a thin oxide. This causes an additional process step just for
the capacitors. The MIM-Cap dielectric is thicker than the gate oxide of the active devices.
MIM-Caps are normally realized on top of the regular metalization layers. The manufacturing
overhead as well as the smaller specific capacitance make MIM-Caps an expensive capacitor
realization. Another capacitor type are poly-poly capacitors. The linearity is much better than
a MOS-Cap but worse compared to MIM-Caps due to poly depletion effects. Other drawbacks
are the need for an additional poly layer and the large parasitic resistance especially of the
bottom poly silicon layer.
Fig. III.4 shows the cross section of a MIM-Cap. Beside the intended capacitance between the
C p1
C p2
wiring
substrate with active
Figure III.4: Cross section of a metal-insulator-metal capacitor (MIM-Cap). The top electrode
suffers from less parasitic capacitance and should be connected to critical nodes.
two plates, parasitic capacitances occur. The top plate has a larger distance from lower wiring
layers and the substrate, and is shielded by the bottom plate. Consequently, the parasitics of the
top plate are much smaller compared to the bottom plate. This fact should be considerd during
circuit design. For example, look at the simple switched-capacitor circuit shown in Fig. III.5.
The top plate of the capacitor is connected to the node N1 . Therefore, the equivalent resistance
is equal to Ref f = T /(C + CP 1 ). The much larger parasitic capacitance Cp2 does not have any
impact on the effective resistance because it is always shorted to ground.
5 Validity of the SC-Equivalence
In the introduction of the switched-capacitor resistor equivalents it was pointed out that the
node voltages must not change considerably during one switching cycle. If the signal frequency
becomes comparable to the clock frequency, the transfered charge is no longer proportional to a
φ1 φ2
v1 Cp1
C v2
Cp2
Figure III.5: The top plate of a capacitor which has a lower parasitic capacitance should be
connected to the node that is more sensitive to parasitics.
constant potential difference between the input and the output node. Consequently, switched-
capacitor circuits are an equivalent to continuous-time systems as long as the clock frequency
is sufficiently higher than the signal bandwidth. The simple RC low-pass shown in Fig. III.6
shall be analyzed to quantify the expression “sufficiently higher”: The transfer function is given
R
1
|H(ω)|
V1 C V2
0.5
0 ωp
arg[H(ω)]
jω
π/4
π/2
−ωp σ
ω
Figure III.6: Time-continuous RC low pass with Bode plot and pole zero diagram in the
complex plane.
by
1 1
H(jω) = ; ωp = (3.5)
1 + ωjωp RC
The magnitude and the phase are
1
|H(jω)| = q (3.6)
ω2
1+ ωp2

ω
arg (H(jω)) = −arctan (3.7)
ωp
Φ1 Φ2
V1 C1 C2 V2
Figure III.7: Switched-capacitor equivalent for the first order low-pass filter shown in
Fig. III.6
Using a simple parallel SC-equivalent for the resistor results in the circuit shown in Fig. III.7.
The capacitor C2 is equal to C. Let’s start the analysis of the circuit one clock period before
the actual instance t = nT . For t = (n − 1)T , S1 is closed, S2 is open and all internal transients
are completed:
t = (n − 1)T (3.8)
vC1 [n − 1] = v1 [n − 1] (3.9)
vC2 [n − 1] = v2 [n − 1] (3.10)
(3.11)
q1 [n − 1] = C1 vC1 [n − 1] = C1 v1 [n − 1] (3.12)
q2 [n − 1] = C2 vC2 [n − 1] = C2 v2 [n − 1] (3.13)
Half a clock period later, S1 is open and S2 connects the two capacitors C1 and C2 :
1
t = (n − )T (3.14)
2
1 1 1
vC1 [n − ] = vC2 [n − ] = v2 [n − ] (3.15)
2 2 2
The charge which had been stored on two independent capacitors is now shared equally:
qtot = q1 [n − 1] + q2 [n − 1] = C1 v1 [n − 1] + C2 v2 [n − 1] (3.16)
1 qtot C1 v1 [n − 1] + C2 v2 [n − 1]
⇒ v2 [n − ] = = (3.17)
2 Ctot C1 + C2
At the actual instance t = nT , S2 has separated the two capacitors again and S1 connects C1
to the input. Therefore, the voltage at the output is equal to the output voltage half a clock
cycle earlier:
1 C1 v1 [n − 1] + C2 v2 [n − 1]
v2 [n] = v2 [n − ]T = (3.18)
2 C1 + C2
Using the z-transformation results in the transfer function H(z):
C1 1 C2
H(z) = = α := (3.19)
z(C1 + C2 ) − C2 z(1 + α) − α C1
0 0
RC−stage RC−stage
SC−equivalent SC−equivalent
−10
−0.5
magnitude [dB]
magnitude [dB]
−20
−1
−30
−1.5
−40
−2
−50
−2.5
−60
−70 −3
−5 −4 −3 −2 −1 0 1 −5 −4 −3 −2 −1 0 1
10 10 10 10 10 10 10 10 10 10 10 10 10 10
normalized angular frequency normalized angular frequency
Figure III.8: Frequency response of switched-capacitor low pass shown in Fig. III.7. The
sample frequency must be significantly larger than the maximum frequency range required
during the operation of the circuit.
For technical frequencies, the transfer function is evaluated on the unit circle, i.e. z =
exp(jωT ) = cos(ωT ) + jsin(ωT ). Replacing z in eq. 3.19 yields
1
H(jω) = (3.20)
(1 + α)cos(ωT ) − α + j(1 + α)sin(ωT )
This transfer function is periodic with 2π/T , which is self-evident for a discrete time circuit.
For small frequencies (ω ≪ 1/T ) the exponential function can be approximated by a first order
Taylor series:
z = exp(jωT ) ≈ 1 + jωT (3.21)

1
⇒ H(jω) ≈ (3.22)
1 + jω(1 + α)T
1
comparing the coefficients of eq. 3.5 and eq. 3.22 results in ωs /ωp = 2π(1 + α). For ωp ≪ T
,
this can be rewritten as:
1 1 1
ωp = T
= T T
≈ (3.23)
T + C 2 · ( C1 ) C 2 · ( C2 + C1
) C2 · Ref f
The condition ωp ≪ ωs requires α ≫ 1 and C2 ≫ C1 . Figure III.8 shows that the SC cir-
cuit of Fig. III.7 is a good approximation for the RC low-pass in a range of 0 ≤ f ≤ 0.02fs .
At frequencies f ≥ 0.5fs , the Nyquist criterion is violated, and the SC concept is not useful
any longer. Figure III.8 shows the Bode plot of the switched capacitor filter circuit shown in
Fig III.7. The frequency response is periodic with 2π
T
. The switched-capacitor circuit provides
a good approximation of the RC realization as long as the sampling frequency is sufficiently
larger than the 3dB corner frequency of the low-pass.
Another condition for the clock frequency arises from transient events within the SC-circuit.
In our analysis, we have assumed ideal switches and instantaneous charging of all capacitors.
Due to the resistance of real switches and other components, the capacitances are charged to
a voltage close to the ideal value only within a time much larger than the respective RC time
constant. This sets a limit to the maximum clock frequency, depending on the circuit topology
and on the technology parameters (e.g. opamp bandwidth, slew rate). This condition fulfilled,
we do not have to care about the transient waveforms within circuitry between two switches.
Assuming that the output of the SC block is connected to another SC block whose sampling
stage is clocked with the complementary clock signal, only the voltage at the sampling capacitor
at the sampling time is relevant. For n-channel MOSFET switches, the sampling time is given
by the negative edge of the clock signal. In the subsequent S&H stage, this voltage is sampled
at the negative edge of the complementary clock. Depending on the clock (φ1 or φ2 ) used for
the output stage, the transfer function H(z) differs by a factor of z −1/2 .
In principle, all known RC circuits can be realized in SC technique simply replacing the re-
sistances by SC equivalents. However, floating nodes may arise, i.e. nodes that are never
connected to a fixed potential or virtual ground of an opamp input. They are easily disturbed
by crosstalk, leakage and other parasitic effects. Therefore, particular SC filter structures have
been developed.
6 Switched-Capacitor Integrators
6.1 Operation Principle
An important building block in filter circuits is the integrator. A time continuous RC-implementation
C2
R1
V1
V2
Figure III.9: Time continuous RC-integrator
is shown Fig. III.9. The transfer function in the Laplace plane is given by
1 1 1
H(s) = − =− ω , ω0 := (3.24)
sRC j RC
ω0
C2
Φ1 Φ2
V1 C1 V2
Figure III.10: Simple SC-integrator implementation
C2 C2
V1 C1 C1
V2 V2
Figure III.11: Equivalent circuits of the SC-integrator for the two clock phases
A simple switched-capacitor implementation can be obtained by replacing the resistor R with

the SC equivalent. The resulting circuit is depicted in Fig. III.10. The principle of SC circuit
analysis is demonstrated once again in this section for the integrator. A summary of the
particular analysis steps is given in Tab. III.3 at the end of this section: At first the polarity of
each capacitance has to be labeled. The polarity can be chosen arbitrarily and does not have
any physical relevance. However, it is important that the polarity is not changed during the
analysis to avoid sign errors in the calculation. The second step is to draw equivalent circuits
for both clock phases. Fig. III.11 shows these equivalent circuits for the clock phases φ1 = high
and φ2 = high. Now a charge balance analysis is performed, beginning one clock cycle prior to
the actual instance nT . At time t = (n − 1)T , the charges on the capacitors are:
q1 [n − 1] = C1 v1 [n − 1] (3.25)
q2 [n − 1] = C2 v2 [n − 1] (3.26)
(3.27)
The input capacitance C1 is charged to the input voltage v1 , the voltage across C2 is equal to
the output voltage. Half a clock period later, the first switch separates C1 from the input and
the second switch connects the capacitance to the inverting input of the operational amplifier.
As this node acts as a virtual ground the capacitance C1 is discharged. Due to the high input
1

impedance of the amplifier all the charge from C1 is transfered to C2 at t = n − 2
T.

1
q1 n − = 0 ⇒ ∆q = −C1 v1 [n − 1] (3.28)
2

1
q2 n − = q2 [n − 1] + ∆q = C2 v2 [n − 1] − C1 v1 [n − 1] (3.29)
2
In the next phase, the input capacitance C1 is connected back to the input node. The charge
on the capacitance C2 is not changed. Thus, at t = nT :

1
q2 [n] = q2 n − (3.30)
2

1 1 1
v2 [n] = q2 [n] = q2 n − (3.31)
C2 C2 2
C1
= v2 [n − 1] − v1 [n − 1] (3.32)
C2
The z-transformation of the last equation yields
C1 −1
V2 (z) = z −1 V2 (z) − z V1 (z) (3.33)
C2
V2 (z)
Solving for V1 (z)
gives the transfer function
V2 (z) C1 z −1
H(z) := =− (3.34)
V1 (z) C2 1 − z −1
Now the response of the circuit can be investigated for technical frequencies ω. Therefore z −1
is replaced by e( − jωT ):
C1 e(− 2 jωT )
1
H(jω) = − (3.35)
C2 2jsin ωT

2
For frequencies ω significantly smaller than the clock frequency, the transfer function can be
approximated according to
C1 1
H(jω) = − (3.36)
C2 jωT
This is the transfer function of an integrator, comparing eq. 3.24 and eq. 3.36 yields the corre-
spondence
C1 1
ω0 = · (3.37)
C2 T
The deviation of this SC transfer function from the RC integrator is given in table III.2 in
dependence of the signal frequency.
6.2 Impact of Parasitics
Now let’s consider the impact of parasitic capacitances on the behavior of the SC-integrator.
Fig. III.12 shows the SC-integrator with the parasitic capacitances of C1 and C2 . CP 1 is con-
Normalized Amplification Phase

frequency error error
f /fc ideal 90
0,00 0,00% 0
0,05 0,41% 9
0,10 1,66% 18
0,15 3,80% 27
0,20 6,90% 36
0,25 11,07% 45
0,30 16,50% 54
0,35 23,41% 63
0,40 32,13% 72
0,45 43,13% 81
0,50 57,08% 90
Table III.2: Amplification and phase error of SC integrator with clock frequency fs versus ideal
RC integrator
nected in parallel to C1 . Therefore it influences directly the transfer function of the circuit.
CP 2 is always shorted to ground and has no influence. The same situation exists for CP 3 which
is connected between ground and virtual ground. CP 4 is driven by the low impedance output of
the operational amplifier and has a negligible impact on the operation of the integrator. Only
CP 1 is critical and should be minimized. Therefore, the top plate of the capacitance C1 should
be connected to the switched node.
Choosing a slightly more complex SC topology, an integrator insensitive to parasitics is ob-
tained, Fig III.13. When φ1 is high, the capacitor C1 is charged to C1 · V1 . When φ2 is turned
on, the node previously connected to the input is grounded, and charge flows from the other
electrode of C1 to C2 . Both sides of C1 are connected to a low-ohmic node during both clock
C2
CP3 CP4
CP1 C1
CP2
Figure III.12: Simple SC-Integrator with parasitic capacitances. As the switched node is
more susceptible to additional capacitances the top plate should be connected to this node.
C2
Φ1 C1 Φ2
V1 Φ2 Φ1 V2
Figure III.13: Non-inverting SC-integrator which is less susceptible to parasitic capacitances
phases and are not sensitive to parasitics. The transfer function is now
C1 z −1
H(z) = (3.38)
C2 1 − z −1
By changing the clocks of the switches at the input, the sign of the integrator transfer function
can be changed. The integrator in Fig. III.14 is inverting, but has no delay, as charge is
transfered during φ2 = high directly from V1 to C1 and from C2 to C1 . Its transfer function is
C1 1
H(z) = − (3.39)
C2 1 − z −1
The low frequency behavior is again given by 3.35, 3.36.
C2
C1
Φ2 Φ2
V1 Φ1 Φ1
V2
Figure III.14: Inverting SC-integrator
6.3 Impact of Offset Voltage

Operational amplifiers often suffer from a finite offset voltage. As shown in Fig. III.15, the
offset voltage can be modeled as a voltage source V0 in series to the positive amplifier input.
An analysis of the circuit with this offset voltage results in the output voltage
C1 C1
v2 [n] = v2 [n − 1] − v1 [n − 1] + V0 (3.40)
C2 C2
The offset voltage disturbs the function of the integrator by adding an output offset term. One
benefit of switched-capacitor circuits is the ability to cancel out offset voltages of the operational
amplifier. This is done by sampling the offset voltage in one phase and subtracting it in the
following phase.
C2
Φ1 Φ2
V1 C1
V2
V0
Figure III.15: Simple SC-integrator implementation with offset voltage model of the opera-
tional amplifier
6.4 Analysis Steps for SC-Circuits
1. Mark polarity of each capacitance arbitrarily.

Do not change the polarity during the analysis.
2. Draw equivalent circuit for both clock phases.
3. Do a charge balance analysis for a complete clock cycle. Start one clock period
in the past, i.e. at (n−1)T if the system is considered at nT . Derive a relation
in the form vout [n] = a · vout [n − 1] + b · vin [n − 1] + c · vin [n].
4. Make a z-transformation of the equation resulting from step 3.

Vout (z)
5. Calculate the transfer function H(z) = Vin (z)
.
6. Evaluate the transfer function on the unit circle of the z-plane, i.e. for z =
exp(jωT ).
Table III.3: Analysis steps for Switched-Capacitor Circuits

7 Switched-Capacitor Amplifier
7.1 Principle of Operation with Offset Compensation

A switched-capacitor amplifier with offset compensation is shown in Fig. III.16, the equivalent
Φ2
C2
Φ2 Φ1
Φ1
vin [n] C1
Φ2
vout [n] = − C1 vin [n]
( )C2
Figure III.16: Offset compensated SC-amplifier with programmable gain.
Voff
VC2
Voff C2 VC1
C2
C1 C1
Voff vin [n]

Voff Voff
vout [n] = − ( CC12 ) vin[n]
Figure III.17: Equivalent circuits for the SC-amplifier shown in Fig. III.16
circuits for the two clock phases are shown in Fig. III.17. The operation principle is as follows:
During the φ2 phase all capacitances are discharged and the operational amplifier is reset, i.e.
it is in linear mode of operation and its output is zero. During the φ1 phase the capacitance C1
is charged to the input voltage. The charge C1 vin [n] is transfered directly to the capacitance
C2 . The voltage drop across this capacitance is equal to the output voltage. A detailed analysis
of the circuit which is recommended to the reader yields the transfer function:
Vout (z) C1
H(z) := =− (3.41)
Vin (z) C2
This transfer function is valid also in the presence of an offset voltage.
A positive transfer function is achieved by swapping the clocks of the input devices, Fig. III.18.
The transfer function is now positive, but contains a delay of half a clock cycle:
C1 −1/2
H(z) = ·z (3.42)
C2
Φ2
C2
Φ2 Φ1
Φ2
vin [n] C1
Φ1 −1/2
vout [n] = C1 vin [n] . z
( )
C2
Figure III.18: Noninverting SC amplifier with delayed output
Φ1
C3
Φ2 Φ2
C2
Φ 1(Φ2 )
vin [n] Φ1
C1
Φ 2 (Φ 1)
( )
C2
C4
Figure III.19: SC-amplifier with capacitive reset and de-glitching capacitor. The sign of the
amplification can be set by choosing the clock phase of the input transistors, i.e. inverting for
the regular clocks and non-inverting for the clocks in brackets.
The inverting and non-inverting function have been shown already for the SC integrator. One
drawback of the circuit is the reset phase in each clock cycle. This reset causes stringent slew
rate requirements on the amplifier, because the output must settle during half a clock period.
An implementation which avoids the large voltage steps and thus enables a faster operation of
the circuit is shown in Fig. III.19. The capacitance C3 is charged to the output voltage during
the φ1 phase and put into the feedback loop of the opamp during the reset phase. Thus the
output voltage is held and only the difference between two samples has to be charged in the φ1
phase.
The shown SC-amplifier is insensitive to offset errors of the operational amplifier. This is
achieved by sampling the offset voltage during φ2 and subtraction during φ1 . This so-called
double sampling technique can be used also in sample&hold circuits. An example for an offset
compensated sample&hold circuit is shown in Fig. III.20. It is recommended to the reader to
analyze the circuit in detail.
Clock feedthrough can cause errors as was described in chapter II. In Fig III.21 we see a
structure where the clock signals of the switch connected to virtual ground, φ2a and the clock
Φ1 Φ2
Φ1
CH
Vin
Vout
Figure III.20: Offset-compensated SC-S&H-circuit
Φ 1a
C3
Φ 2a Φ2
C2
Φ 1(Φ2 )
vin [n] Φ1
C1
Φ 2 (Φ 1)
( )
C2
Figure III.21: SC-amplifier robust against clock feedthrough
signal connecting the storage capacitance C3 to GND, φ1a , are turned off slightly earlier than
the clocks at all other switches. Thus, only clock feedthrough of these two switches causes
errors. This error signal is independent of input the signal and is compensated like a DC-offset.
7.2 Superposition of input signals
The virtual ground node of an operational amplifier in linear mode of operation collects all
injected currents according to the Kirchhoff current law. This enables the superposition of
multiple transfer function with a single operational amplifier. In Fig III.22, multiple input
stages are connected to the inverting input of the opamp. The output is given by the sum of
the transfered input signals:
C1 −1/2 C2 −1/2 C3
Vout (z) = V1 (z) · ·z + V2 (z) · ·z − V3 (z) · (3.43)
C C C
The superposition of input signals can be applied to SC integrators in a similar way.
Φ2
Φ2
C1 C
v1[n] Φ1
Φ2 Φ1
Φ2
C2
v2[n]
Φ1 vout [n]
Φ1
C3
v3[n] Φ2
Figure III.22: SC amplifier with multiple input signals

Chapter IV
Analog-to-Digital and
Digital-to-Analog Converter
Fundamentals
1 Nyquist-Rate Converters and Oversampling Convert-

ers
The Nyquist criteria (equation 1.1) states that, to avoid loss or corruption of data, the sample
rate has to be at least twice the maximum signal frequency. A higher sample rate results in
lower requirements for the anti-aliasing filter at the input or, respectively, the low-pass filter at
the output of a mixed-signal system.
Converters that generate a series of output values in which each one has a one-to-one correspon-
dence with a single input value are loosely defined as Nyquist-rate converters. A Nyquist-rate
D/A converter, for example, can generate a certain number of analog output levels; each of
which, be it voltage or current, is directly correlated to a digital B-bit signal (or word).
For some reasons, it may be advisable to operate converters at sampling rates far greater than
the Nyquist rate, but in return, with a lower resolution. Such converters are called oversam-
pling converters. Due to the higher sampling frequency (typically 8 - 64 times the Nyquist
frequency), the standards for the filters are considerably lower. Furthermore, noise-shaping
can be used to shift much of the quantization noise outside the signal bandwidth into higher
frequency bands. However, with oversampling converters, there is no direct correspondence
between individual input and output values. Moreover, the speed of analog components has to
increase manifold for oversampling converters.
The following descriptions apply to Nyquist-rate converters, oversampling converters are dis-
cussed in chapter VII.
41
2 Ideal D/A Converters
B in D/A Vout
Vref
Figure IV.1: Block diagram of an ideal D/A converter
An ideal D/A converter has two inputs: an analog one, the so-called reference voltage Vref and
a digital word Bin that is to be converted. If Bin is interpreted as an unsigned binary number
with the decimal point left of the most significant digit, its decimal representation is
Bin = b1 2−1 + b2 2−2 + . . . + bN 2−N (4.1)

The relationship between Vref and the output voltage Vout is given by

Vout = Vref b1 2−1 + b2 2−2 + . . . + bN 2−N = Vref Bin (4.2)
An ideal D/A converter has a discrete-valued, continuous-time output signal. The transfer
characteristics for a 2bit converter is given in Fig. IV.2. The smallest possible voltage change
at the output is given by
Vref
VLSB = N (4.3)
2
Correspondingly, the smallest possible change of Vout relative to the reference voltage is here
defined as one LSB (least significant bit):
1
1 LSB = (4.4)
2N
The maximum value of Vout is

Vout,max = Vref (2−1 + 2−2 + ... + 2−N ) = Vref 1 − 2−N = Vref − VLSB (4.5)
3 Ideal A/D Converters

The block diagram of an ideal A/D converter is shown in Fig. IV.3. The following relationship
applies:

Vref b1 2−1 + b2 2−2 + . . . + bN 2−N = Vin + Vx
1 1
− VLSB ≤ Vx < VLSB (4.6)
2 2
Vout
Vref
1
3/4
1/2
VLSB
Vref
1/4
0
00 01 10 11 (100) B
in
Figure IV.2: Input-output transfer curve of an ideal 2-bit D/A converter
The digital output word multiplied by the reference voltage equals the input voltage except for
a small ambiguity which is called quantization error. The input-output transfer curve of an
ideal A/D converter is shown in Fig. IV.4. The transfer curve in Fig. IV.4 is defined such that
the transition between two digital values occurs exactly in the middle of the interval between
the respective analog values. At the midpoints of the staircase function, the normalized digital
value is exactly equal to the analog input signal as fraction of the reference voltage. For all
other analog values, a quantization error occurs, which grows with increasing distance to the
nearest midpoint.
Equation 4.6 only applies where
1 Vin 1
− ≤ ≤ 1 − N +1 (4.7)
2N +1 Vref 2
If the input voltage is out of this range, the converter is overdriven or out of range; in that
case, the quantization error will be larger than VLSB /2.
4 Quantization Noise
A quantization error in the range 0 to 21 VLSB occurs even in ideal A/D converters, due to the
transition from continuous to discrete voltage levels. Although this error depends determinis-
tically on the value of the input signal, it can be treated as a noise source regarding its effect
Vin A/D Bout
Vref
Figure IV.3: Block diagram of an ideal A/D converter
on the accuracy of the converter, provided that the input signal frequency is high enough so
that the quantization error can be treated like a uniformly distributed random variable.
Additional noise is present in real-world converters because of physical effects. The idealized
circuit shown in Fig. IV.5 outputs only the quantization error present in the converted signal
B. The equation
V1 = Vin + VQ (4.8)
can be interpreted in a way that V1 is the (noiseless) input signal with an additive noise voltage
VQ , i.e. the quantization error. The actual value of the noise voltage and, accordingly, the
respective noise power, depends on the waveform of the input signal. If a ramp signal over the
complete allowable voltage range is input to an A/D converter, i.e. without overdriving it, the
curve shown in Fig. IV.6 is generated. The maximum quantization error for all non-overdriving
signals is limited to ± 12 VLSB . The average of the quantization error VQ is zero, but its RMS
value and, accordingly, the noise power, are different from zero.
" Z T # 12
1 VLSB
q 2
VQrms := VQ2 = VQ2 dt = √ (4.9)
T − T2 12
The assumption of the quantization error as a uniformly distributed random variable within
the allowable voltage range produces the same result. The quantization error is directly linked
to the resolution of the converter via VLSB . As long as the reference voltage remains constant,
the noise power is reduced by 6 dB for each additional bit in the A/D converter.
Assuming that the quantization error is the main noise source in the converter and that the
input signal is randomly distributed over the input voltage range, the maximum signal-to-noise
ratio (SNR) is given by
!
2
Vin,max
= 20 log 2N = 6, 02N dB

SN R|max = 10 log (4.10)
VQ2
For sinusoidal input signals, the SNR is better, as sinusoidal signals have a higher AC power.
SN R|max == 6, 02N dB + 1.76 dB (4.11)
For smaller input signal magnitudes, the SNR decreases as shown in Fig. IV.7.
B out VLSB
= 1/4 = LSB
Vref
11
10
01
00
0 1/4 1/2 3/4 1 Vin
Vref
V01 V11
Vref Vref
Figure IV.4: Input-output transfer curve of an ideal 2-bit A/D converter
5 Performance Characteristics of Data Converters

In the following section, parameters describing the transfer function of a data converter are
explained.
5.1 Static Transfer Function
Resolution
The resolution of a converter is the ratio of the largest possible value to the smallest one.
Specification in number of bits: N -bit resolution declares that the converter can resolve 2N
distinct analog levels.
Specification in percent or ppm: Declares the ratio of the quantization unit VLSB to the reference
voltage:
VLSB
= 2−N (4.12)
VRef
Thus, an 8-Bit converter has a resolution of
1
= 0, 3906% (4.13)
256
Resolution is not necessarily an indication of the accuracy of the data converter, which can be
smaller than the resolution.
B V1
Vin A/D D/A
VQ
Figure IV.5: Idealized circuit to determine the quantization error ratio in a converted signal
V VQ
V in 1
2 V LSB
V1
−1 V
2 LSB
t T
Figure IV.6: Exemplary input signal and its quantization error
Offset error
For D/A converters, the offset error is the output voltage or current for the digital input code
00 . . . 0. It is specified in units of LSBs, i.e. in fractions of VLSB .
Vout
Eof f set(D/A) = (4.14)
VLSB 0...0
For A/D converters, the offset error is the deviation of V00...01 , at which the output word changes
from 00 . . . 0 to 00 . . . 01, from 12 LSB
V0...01 1
Eof f set(A/D) = − LSB (4.15)
VLSB 2
Gain error
The gain error is the deviation of the actual full-scale values from the ideal ones after offset
error has been removed. It is specified either in fractions of VLSB , percentage of the full-scale
value or in mV . Like the offset error, it is defined differently for D/A converters:

Vout Vout
− 2N − 1

Egain(D/A) = − (4.16)
VLSB 1...1 VLSB 0...0
and A/D converters:

V1...1 V0...01
− 2N − 2

Egain(A/D) = − (4.17)
VLSB VLSB
60
Best possible SNR

SNR
(dB) 50
40
30
20
10
( Vpp = Vref )
Vin (dB)
−60 −50 −40 −30 −20 −10 0
Figure IV.7: Idealized SNR versus sinusoidal input signal amplitude for a 10-bit A/D con-
verter.
Fig. IV.8 shows an example of offset and gain error for D/A converters.
Accuracy
The absolute inaccuracy is defined as the maximum deviation of the actual analog value from
the ideal one. It includes offset, gain and linearity errors and may be different for every indi-
vidual quantization value.
The relative accuracy is defined as the deviation that remains after offset and gain error have
been removed.
Integral Nonlinearity (INL) Error

The INL error is defined as the deviation of each analog value from a straight line as demon-
strated in Fig. IV.9. If the straight line through the endpoints of the converter’s transfer curve
is chosen as reference, the INL equals the before mentioned relative inaccuracy. Alternatively,
a regression line can be used as reference. It depends on the application which definition should
be applied.
Differential Nonlinearity (DNL) Error

Deviation of the analog step sizes from 1 · VLSB (after removal of gain and offset errors). Like
the INL, the DNL value is defined individually for each digital word.
Monotonicity
The output signal of a monotonic D/A converter increases or remains at least unchanged as
the input signal increases. A converter with a maximum DNL smaller than 1 LSB is certainly
Vout
Vref
Ideal
1
3/4
Gain error
1/2
1/4
Offset error
0 00 01 10 11 (100) B in
Figure IV.8: Offset and gain error for a 2-bit D/A converter
monotonic, as is one with an INL smaller than 12 LSB.
Missing codes
Missing codes of an A/D converter is the equivalent term for a non-monotonic D/A converter.
If the DNL of a converter is smaller than 1 LSB and its INL smaller than 12 LSB, missing codes
can be ruled out. In this case, all possible digital values may appear as output.
5.2 Transfer Behavior for Alternating Voltages and Currents
In applications with alternating voltages or currents, performance characteristics measuring the

linearity of a converter are based on the distortion of a sinusoidal signal.
Total harmonic distortion (THD) and Second harmonic distortion (SHD)

If the digitized values of a sinusoidal function with the frequency f1 are applied to a D/A
converter, harmonics of the original waveform may appear in the output signal because of the
nonlinearity of the transfer function. The Total Harmonic Distortion is defined as follows:
p
V22 + V32 + V42 + . . .
T HD := 20 log (4.18)
V1
where Vi is the amplitude of the ith harmonic, i.e. those frequency components with the fre-
quency fi = i · f1 . Typically, only the components V1 up to V5 are included, whereas for the
calculation of the SHD only the second harmonic is considered. This definition also applies
for the output signal of an A/D converter after passing an ideal D/A converter/low-pass filter
Vout Integral nonlinearity error (best−fit)

Vref
1
3/4
1/2 Integral nonlinearity error (endpoint)
1/4
0 00 01 10 11 (100) B in
Figure IV.9: Integral Nonlinearity of a 2-bit D/A converter. A reference line has to be chosen
for lack of a unambiguous definition.
combination.
Signal-to-Noise ratio (SNR), signal to noise and distortion ratio (SNDR or

SINAD)
The SNR is defined by the ratio of signal power to noise power. It is typically specified in dB.
Psignal
SN R = 10 log (4.19)
Pnoise
Thus, the SNR depends on the actual value of the wanted signal, as can be seen in Fig. IV.7.
The best SNR is achieved for full-scale values. The noise power is calculated by integrating the
noise power density spectrum over the bandwidth as limited by the output filter. Fig. IV.10
shows the output spectrum of a 8192 point FFT with a signal at 2MHz, its harmonics and
noise. Note that the “noise floor” visible in the plot has to be summed up over the signal
bandwidth to obtain the total noise power for calculation of the SNR. If physical noise sources
are not present or negligible, the SNR can be calculated according to 4.10. For separation
between the influence of nonlinearities and that of quantization noise, the SNR, which does not
include the power components of the harmonics, can be distinguished from the signal to noise
and distortion ratio (SNDR or SINAD). The value obtained for the SNR without harmonic
distortion depends on the method that is employed to subtract harmonic distortion noise. This
is mostly useful when comparing converters measured and analyzed using the same procedure.
Effective number of bits (ENOB)

Another way to describe the accuracy of a converter is the effective number of bits (ENOB),
Figure IV.10: Exemplary spectrum of a sinusoidal signal, its harmonics and noise
which is given by the number of bits of an ideal converter with the actual SNR obtained by the
real converter under consideration.
It is related to SINAD
SIN AD − 1.76
EN OB =
6.02
Dynamic range (DR), spurious-free dynamic range (SFDR)

The dynamic range of a converter is the ratio of the sinusoidal signal with maximum SNR to
the rms value of noise and harmonic distortion within the signal bandwidth. It corresponds to
the maximum value of SINAD.
The SFDR is the ratio of the power of the converted signal and that of the greatest “spur”,
where a spur is a harmonic or any other undesired signal in the output spectrum.
5.3 Dynamic Behavior

The following specifications are used to characterize the speed of a converter:
D/A converters: Settling Time and Sampling Rate

The settling time of a D/A converter is defined as the time it takes for the converter to settle
within a range of typically ± 12 LSB around the final signal value. The maximum sample rate
is the inverse of the settling time.
A/D converters: Conversion Time and Sampling Rate

The conversion time is the time needed for a single conversion, from the sampling time until
the time the digital output value is available. The sampling rate may be considerably higher
than the inverse of the conversion time if internal pipelining or multiplexing is implemented in
the converter.
Aperture Jitter
If the actual sampling time of an A/D converter differs from the desired time by ∆ t, this will
result in a measurement error of ∆ V , the value of which depends on the slope of the signal in
the time domain or, alternatively, its frequency. If the measurement error is to be kept smaller
than 1 LSB, the following relation has to apply:
VLSB 1
∆t < = N (4.20)
πfin Vref 2 πfin
Most A/D converters have a S & H circuit, as described in chapter II, connected to the input.
The aperture jitter is then determined by the specifications of the S & H.
6 Signed Codes
In many applications, analog input signals may be both positive and negative. The input
voltages are then related to the analog ground potential VAGN D defined by
1
VAGN D = (VDD − VSS ) (4.21)
2
Typically, the maximum input signal range is ± 12 VRef , which covers an input voltage range
equal to that for unipolar signals.
Some common digital representations of bipolar analog values are shown in tab. IV.1.
There are some advantages to the 2’s complement representation, the main one being that
addition can be performed the same way for positive and negative numbers, so the sign can be
neglected. For the subtraction A − B, each bit of B has to be inverted (i.e. forming the 1’s
complement equivalent). This number has to be added to A. At the same time, a single LSB
has to be added to form the 2’s complement of B. As long as the final result is within the digital
code range, intermediate results of the operation may exceed it. Offset binary corresponds to
shifting the signal values by + 12 VRef to unipolar signal range of 0 to VRef .
Table IV.1: Some 4-bit signed digital representations

Chapter V
Nyquist-Rate D/A Converters
Integrated Nyquist-rate D/A converters (DACs) can be subdivided into four categories:
• Decoder-Based Converters
• Binary-Scaled Converters
• Thermometer-Code Converters
• Hybrid Converters
Oversampling converters (counting operation) will be discussed separately.
D/A converters need a highly stable reference voltage to operate, usually provided by a reference
voltage source. In multiplying DACs, the reference voltage is used as a second input signal,
which provides the option of amplitude modulation or acts as a digitally controllable variable
(attenuation cell). DACs in which voltages are related to analog ground (AGND) are four-
quadrant multipliers.
1 Decoder-Based Converters (Parallel Operation)

The basic principle of an N -bit decoder-based DAC is that 2N reference voltage levels are cre-
ated and the one appropriate to the digital input word is routed to the output.
In the resistor-string converter circuit shown in Fig. V.1 the n channel pass transistors can
be exchanged for CMOS transmission gates to enable the use of the full supply voltage range.
However, the reduction of switch resistance is offset by higher capacitances.
Resistor-string converters are always monotonic if the offset of the output buffer is independent
of the input signal. Main factor for their accuracy is the matching precision in the resistor
string. If polysilicon resistors are used, approximately 10-bit accuracy can be attained. The
delay time through the switch network may limit the conversion speed at high sampling rates.
53
Vref
R b3
R b3 b2
R b3
R b3 b2 b1
N Vout
2 resistors
(Buffer)
R b3
R b3 b2
R b3
R b3 b2 b1
−1 −2 −3
Bin = b1 2 + b2 2 + b 3 2
Figure V.1: 3-Bit resistor-string D/A converter with a tree-like pass-transistor decoder
Especially in multiplying DACs, the RC-time of the resistor string is a limitation.

The circuit with digital decoding shown in Fig. V.2 has only one switch between any reference
voltage node of the resistor string and the buffer, but the capacitance of the bus at the output
buffer is very high (2N drain nodes).
Folded resistor-string converters use a decoder that is divided into two address ranges, similar
to the one of a digital memory. So, lines and columns in the resistor matrix can be individually
√
addressed. Here, the total number of drain nodes connected to the output buffer is only 2 2N .
However, when a word line changes its state, all bit lines have to be pulled to new voltage levels
now.
Converters with multiple resistor strings (R-strings) divide MSBs and LSBs into two sections
with different reference voltages. In the 6-bit converter shown in Fig. V.4, the three MSBs
define which two adjacent reference voltage nodes of the first R-string are connected to the
Vref
3 to 1 of 8 decoder
R
R b1
N
2 resistors R b2
(all equal sizes)
R b3
R
Vout
Figure V.2: 3-Bit resistor-string D/A with digital decoding
upper and lower end of the second string via a buffer each. The second R-string does a linear
interpolation between those two voltages as defined by the three LSBs. The decoding logic has
to take into account whether the upper or the lower end of the string has a higher voltage level.
N
For this kind of circuit only 2 · 2 2 resistors are needed, but three buffers are required.
Given that the op-amps have matched offset voltages, monotonicity is guaranteed independent
of the input voltage. The resistors in the second string need not be as precisely matched as those
in the first chain, as errors only appear with the weight of the LSBs in an overall calculation.
2 Binary-scaled Converters (Weighted Mode)
In binary-scaled converters, a binary array of reference currents is created and added at the
inverting input of an op-amp according to the digital input word.
Vref
Word lines
2 to 1 of 4 decoder
N
2
b1 Resistor
(all equal size)
b2
Bit lines
Vout
Output line
2 to 1 of 4 decoder
b3 b4
Figure V.3: 4-Bit folded resistor-string D/A converter
2.1 Binary-Weighted Resistor Converters

Fig. V.5 shows the structure of a converter with binary weighted resistors.
The output value, depending on the digital input word, is given by

b1 b2 b3 RF
Vout = −RF Vref − − − − ... = Vref Bin (5.1)
2R 4R 8R R
where Bin is the decimal representation of the input word:
Bin = b1 2−1 + b2 2−2 + b3 2−3 + . . . (5.2)
The disadvantage of this simple structure is the large range of resistor values and, accordingly,
widely varying currents through the switches. The transistor widths of the transfer gates have
to be scaled in a way that equal voltage drops appear across them. Also, monotonicity is not
guaranteed, and the circuit is prone to glitches (short pulses of over- or under-voltage).
In the circuit shown in Fig. V.6, the resistance ratio is reduced. By inserting a series resistor
of value 3R, the reference voltage in the right part of the resistor network is reduced to 14 Vref .
An additional resistor of value 4R was inserted on the right to obtain this smaller voltage ratio.
Nevertheless, the current ratio remains unchanged at 2N .
Further improvement of the circuit shown in Fig. V.6 leads to a commonly used structure
referred to as an R-2R ladder. In the R-2R ladder network shown in Fig. V.7, Ri′ is equal to
2R for all i. Consequently, current ratios are:
Vref
Ii = (5.3)
2i R
An R-2R ladder network can be designed using only standard resistors with one single value
Vref
2 × 2N/2 unit resistors
Vout
Figure V.4: 6-bit D/A converter with multiple resistor strings
R to improve area consumption and precision.

Fig. V.8 shows a complete R-2R-based converter. The output voltage is given by
N N
X bi I r RF X bi
Vout = RF i−1
= Vref (5.4)
i=1
2 R i=1 2i
2.2 Switched-Capacitor Converters
The switched-capacitor (SC) technology allows the replacement of resistors by networks of

switches and capacitors for the processing of discrete-time analog signals. In D/A converters
with bipolar input signals, i.e. where the input word is signed, amplifier circuits as shown in
Fig. V.9 are used, which operate either in inverting or non-inverting mode depending on the
M SB b1 . The input voltage is generated according to bits b2 to bN by a unipolar D/A converter
which only requires one reference voltage.
The concept of a charge-redistribution converter is to replace the input capacitor of an SC
amplifier with a programmable array of binary weighted capacitors. Like the SC amplifier,
this circuit is insensitive to amplifier offset and f1 -noise. To avoid glitches, the input word
should only be changed when the input side of the capacitors is connected to ground. Thus,
the switching time and the period in which the digital input signal has to be valid depend on
the sign bit. This has to be considered for the design of digital controller circuits.
RF
b1 b2 b3 b4
Vout
2R 4R 8R 16R
−Vref
Figure V.5: 4-bit converter with binary-weighted resistors
RF
b1 b2 b3 b4
Vout
2R 4R 2R 4R 4R
3R VA = 1/4 (−Vref )
−Vref R
Figure V.6: 4-bit D/A converter with modified resistor network: The maximum resistor ratio
is reduced by inserting a series resistor.
2.3 Converters with Weighted Current Sources
The basic concept of current-mode converters is that binary weighted currents are switched to
the inverting input of an op-amp as shown in Fig. V.11. The sum output current is converted
to a voltage via the feedback resistor Rf . The inverting input always remains at ground poten-
tial. The RC delays that have been shown for the preceding types of converters do not apply
here. This converter is suitable for hig speeds, although, correspondingly, the probability of
switching errors increases.
2.4 Glitches
If a change in a converter’s input signal requires multiple bits to change, slightly different
delays of lines that should switch simultaneously may lead to a momentarily erroneous output
value. These so-called glitches occur especially in high-speed converters with fast op-amps.
R1 R’1 R2 R’2 R3 R’3 R4 R’4
R R R 2R
Vref
2R 2R 2R 2R
I1 I2 I3 I4
Figure V.7: R-2R resistance ladder
RF
b1 b2 b3 b4
Vout
2R 2R 2R 2R
Ir R I r /2 R I r /4 R I r /8 2R
−Vref
Ir I r /2 I r /4 I r /8
Figure V.8: 4-Bit D/A converter based on an R-2R resistance ladder
This disturbance can be reduced by placing a capacitor across Rf in Fig. V.11 (Deglitching
capacitor); however, bandwidth must not be curtailed too much so as not to interfere with the
operation of the circuit.
Another way glitches can be suppressed is adding a S & H circuit subsequent to the output.
Furthermore, they can be avoided by converting the binary code to thermometer code.
3 Thermometer-Code Converters
Thermometer code needs 2N − 1 digital inputs to represent 2N values whereas binary code only
needs N digital inputs. Thus, thermometer code is not a minimal representation. It contains
redundancy.
Thermometer code is generated from a binary input word with standard CMOS gates. A 3-bit
thermometer-code D/A can be designed with an array of 8 resistors of equal value as shown
in Fig. V.13. Monotonicity of this converter is guaranteed and its DNL is very low. At an
increase or decrease of the input signal of one LSB, one parallel resistor is added to or removed
from the string. Thus, the sign of the output voltage change is clearly defined. This monotonic
behavior is not guaranteed for the converters with binary weighted resistors discussed before.
Especially when the MSB changes (011 . . . → 100. . . ), DNL may be high and, if resistors are
Output line Φ1
from DAC
b1 Φ2
Φ2
Φ1
b1
Φ1
Vout
b1 or
−Vout
Φ2
b1
Figure V.9: Switched-capacitor amplifier used to derive a signed output signal from an un-
signed DAC output (output valid while φ2 = 1)
16C
Φ1
Φ2
Vout
8C 4C 2C C Φ1a
b1 b2 b3 b4
C2
Vref
Φ1(Φ2 )
Φ 2a
Φ2(Φ1 )
Figure V.10: D/A converter with charge redistribution
mismatched to a certain extent, the transfer function may not be monotonic. Thermometer-
code converters also have reduced probability for glitching errors since an input signal change
of ± 1 LSB results in an alteration in just one switch.
The sum of the resistor values in a thermometer code D/A is not greater than the one in a
binary weighted resistor network, assuming that the smallest input resistors are equal (i.e. 2R
in Fig. V.5 is equal to a unit resistor R in Fig. V.13). Since resistor values are the main
factor for area consumption, whereas controller logic is not as relevant in this regard, total
area consumption of a thermometer-code converter is not significantly higher. The switches are
usually scaled according to the current through them, so their area consumption is similar as
well. This also applies for thermometer-code converters with charge redistribution, as shown
in Fig. V.14.
RF
b1 b2 b3 b4 Vout
I I/2 I/4 I/8
Vss
Figure V.11: Converter with binary-weighted current sources
Figure V.12: Thermometer-code representation of a 3-bit word
3.1 Hybrid Converters
Hybrid designs are the result of the combination of the different converter structures discussed
before. One of these designs that is used frequently is the segmented converter. High-resolution
converters require high precision of the resistors or capacitors controlled by the top few MSBs.
As these precision requirements are difficult to meet, MSBs are often segmented in high-
precision D/As, as shown in Fig. V.15. Thermometer coding is used for the MSB segment;
the LSB segment is a binary-weighted converter design. So, glitching errors are minimized and
area consumption is smaller than that of a design using only thermometer code.
The 2 MSBs of the segmented converter in Fig. V.15 are converted to thermometer code and
control the switching of 3 equal current sources. The lower bits control a R-2R array that is
fed by another identical current source. This lower segment is not guaranteed to be monotonic,
but here the precision requirements are far more relaxed than in the MSB segment.
b1 b2 b3
Binary − to − thermometer code conversion

Rf
d1 d2 d3 d4 d5 d6 d7
Vout
d1 d2 d3 d4 d5 d6 d7
R R R R R R R
−Vref
Figure V.13: 3-bit D/A with 8 resistors of equal values and digital code conversion of the
input signal
N
2 C Φ1
Φ1 C Φ2
Vref
Vout
Φ2 Φ1
C
C2
Φ2
Top capacitors are
connected to ground
C
Bottom capacitors are
connected to Vref
Figure V.14: D/A converter with charge redistribution. Thermometer code is used for the
capacitance network.
R/2
Vout
2R 2R 2R 2R
R R R 2R
Vref
Current driver
VSS Vref
2R
2R 2R 2R 2R 2R
VSS 2MSBs 4−bit binary LSB segment
Figure V.15: 6-bit hybrid converter with 2-bit MSB segment

Chapter VI
Nyquist-Rate A/D Converters
1 Overview
Table VI.1 lists common A/D conversion architectures as well as their their precision and speed.
Architecture Variant Speed Precision

Counting operation single / dual slope integration low to medium high
Integration with oversampling Σ∆-modulation with noise- low to medium high
shaping
Weighted operation Successive approximation medium medium
Algorithmic A/D converter medium medium
Direct (Flash)
Two-step flash low
Flash operation Interpolating high to
Folding medium
Pipeline
Time-interleaved
Table VI.1: Comparison of different A/D converter architectures
Oversampling converters are discussed separately in chapter VII.
2 Integrating A/D Converters

Integrating converters use counting operation. Their structure is simple, yet they can be used
for high-precision measurements as nonlinearity, offset and gain errors are small. Integration
allows for good noise suppression. As only low speeds are possible, integrating converters are
65
S2
−Vin
( SS )
1
2
S1 R1 C1
− Vx
Comparator b1
b2
Vref b3
+
Control Counter
logic
bn
Clock
B out
f clk = 1
Tclk
Figure VI.1: Block diagram of an integrating dual-slope converter
mostly used in measurement instruments.

The op-amp input of the dual-slope converter shown in Fig. VI.1 is connected to −Vin during
phase I for 2N clock cycles. At the end of that time, the voltage at the output has reached the
value defined by
Z T1
−Vin Vin
Vx (T1 ) = − dt = T1 where T1 = 2N Tclk (6.1)
0 R1 C 1 R1 C 1
During phase II, the input is connected to the reference voltage VRef , the polarity of which is
opposite to that of Vin . The integrator counts downwards starting from Vx (T1 ) until the output
voltage has reached 0V . The duration of this process is measured by a digital counter and can
be defined as
Z T1 +T2
Vref
Vx (T1 + T2 ) = Vx (T1 ) − dt = 0 (6.2)
T1 R1 C 1
Vin
⇒ T2 = T1 · (6.3)
VRef
Vin
⇒ Bout = 2N (6.4)
Vref
The initial value of the counter is zero for both phase I and II. At the end of phase II, the
counter reading is exactly the N -bit digitized value of the input voltage. As the same analog
loop is used for the integration of −Vin and that of VRef , variations of gain or of the time
constant R1 C1 have no effect on the output. Offset errors can be avoided by using quad-slope
conversion or by auto-zeroing, similar to the way it has been shown for SC-circuits.
A careful choice of T1 can result in significant attenuation of unwanted frequency components
of the input signal if the integration time T1 is an integer multiple of the cycle time of the noise
frequency fn :
1
T1 ≈ m mit m ∈ IN (6.5)
fn
3 Successive-Approximation Converters
This type of converter is based on the so-called binary-search algorithm. Fig. VI.2 shows the
flow graph of this algorithm for a bipolar input signal within the voltage range ±0.5VRef and
binary offset coding of the output. (The limitation of the range of values to VRef · (1 − 2−N )
will be disregarded in this section).
Start
Signed input
Sample Vin, VD/A = 0, i = 1
No
Vin > VD/A
Yes
bi = 1 bi = 0
Yes Yes
i≥N i≥N
No Stop No
i=i+1 i=i+1
VD/A = VD/A + Vref /2i VD/A = VD/A − Vref /2i
Figure VI.2: Flow diagram of successive approximation
The basic structure of this type of A/D converter is sketched in Fig. VI.3.
Vin S/H
Successive−approximation register
(SAR) and control logic
b1 b2 bn
VD/A B out
D/A converter Vref
Figure VI.3: Block diagram of a successive approximation converter
At the end of the conversion process, the D/A output voltage is within an interval of ±0.5VLSB
around the input voltage. The SAR register and the controller logic are digital circuits control-
ling the operation of the algorithm. The S&H circuit at the input is necessary to keep the input
value of the comparator constant during the conversion. Main factor for speed and accuracy of
the converter is the D/A converter as shown in Fig.VI.3.
3.1 Charge-Redistribution Converters
Multiple architectures were designed to implement the successive-approximation conversion

approach, among them resistor-string circuits, circuits with capacitance networks for charge
redistribution and hybrid architectures. No explicit D/A converter is needed for a charge-
redistribution converter. Its conversion function is implemented within the capacitance net-
work. Its operation runs according to Fig. VI.4.
Start unsigned input
Sample Vin
Vx=−Vin, i=0
i+1
Vx=Vx+Vref/2
Yes
i>N
No
i+1
Vx=Vx−Vref/2
bi=1 bi=0
i=i+1
No
i>N
Yes
Stop
Figure VI.4: Flow diagram of successive approximation, modified for a charge-redistribution

converter
Here, a voltage corresponding to the output value of the SAR is subtracted from the input volt-
age so that the voltage Vx equals the remaining difference. Vx is compared to analog ground,
and approaches Vx = 0 to less than VLSB . Fig. VI.5 shows a unipolar converter in the three
stages of one approximation step:
Vx ~ S2
~0
SAR
16C 8C 4C 2C C C
b1 b2 b3 b4 b5 S3
1. Sample mode
S1
Vin Vref
Vx = −Vin S2
SAR
16C 8C 4C 2C C C
b1 b2 b3 b4 b5 S3
2. Hold mode
S1
Vin Vref
Vref S2
Vx = −Vin +
2
SAR
16C 8C 4C 2C C C
b1 b2 b3 b4 b5 S3
3. Bit cycling
S1
Vin Vref
Figure VI.5: Unipolar successive approximation A/D converter with charge redistribution
1. Sample Mode
The comparator is reset to its switching threshold voltage, so that Vx = 0, if there is no
offset. All capacitances are charged to Vin . This corresponds to the S&H function.
2. Hold Mode
The comparator is activated by opening the switch S2 , and all capacitances are sub-
sequently switched to ground. Thus, the voltage at the comparator input changes to
Vx = −Vin , while the input voltage is stored in the capacitance network. Finally, switch
S1 is connected to VRef . (It is important to note that op-amps are usually out of their
linear range at this point so that the term ‘virtual ground’ should not be used.)
3. Sequential determination of bit values (Bit cycling)

The largest capacitor, 16C in Fig. VI.5, is connected to VRef . As this is half the total
capacitance in the network, the node voltage Vx becomes
1
Vx = −Vin + Vref (6.6)
2
Now, the state of the comparator output indicates the MSB b1 . If b1 = 0, the controller
logic connects the capacitance to ground again, if b1 = 1, it remains connected to VRef .
This operation is repeated for the less significant bits and the smaller capacitances.
To obtain exact divisions VRef /2, VRef /4 . . ., an additional capacitor of the smallest value
C is needed in the binary weighted capacitance network. It is charged to Vin as well as
the other capacitors during stage 2. The bottom plates of the capacitors, which usually
exhibit larger parasitic capacitances, should be connected to the reference voltage, not to
the comparator input.
This design can be expanded to handle bipolar input signals by adding a second reference
voltage source −VRef as it is shown in Fig. VI.6. In this case, the sign of the input signal, i.e.
the sign bit is determined in the first cycle of the algorithm. If Vx < 0, the operation proceeds
as described above. If Vx > 0, the negative reference voltage is used for the following stages.
The capacitance is then switched to −VRef if Vx is positive. The resulting output value is given
in ‘sign magnitude’ representation.
The attainable accuracy of an A/D converter with successive approximation is limited by the
matching accuracy of resistors and capacitors. If they are matched to 0.1%, 10 bit accuracy is
possible. As matching errors originate in the fabrication process and do not change afterwards,
a calibration sequence can be implemented in a start-up routine that runs each time the supply
voltage is turned on. The error values needed for correction can be stored in an SRAM register.
Start
Signed input
Sample V = V in , i = 1
No
V>0
Yes
bi= 1 bi= 0
V = V − Vref /2 i+1 V = V + Vref /2

i+1
i =i+1
No
i >N
Yes
Stop
Figure VI.6: Flow diagram of successive approximation for bipolar input signals
3.2 Hybrid Architecture
In a hybrid architecture like the one shown in Fig. VI.7, the upper bits are determined using
a resistor string D/A converter, the lower ones with charge redistribution. The first step is
to sample Vin and charge all capacitors to −Vin . The conversion stage for the three MSBs
corresponds to the one described in section 3.1, but nodes are connected alternatively to two
buses leading to the capacitance network. With all capacitances connected in parallel, successive
approximation is used to find the nodes of the resistor string next to Vin . All capacitances are
then connected to the node with the lower voltage, and the lower bits are found with the bit-
cycling method as described above. As the resistor string is monotonic, this hybrid converter
is certainly monotonic at least in the higher bits.
3.3 Error Correction
Figure VI.8 shows a m+n bits successive approximation A/D converter with error correction.
Here, the MSBs are obtained using capacitors, whereas a resistor string, referred to as sub-
DAC, is used for the LSBs. In this arrangement, the MSBs are not necessarily monotonic, but
errors can be determined in a auto-calibration routine during start-up.
This auto calibration sequence proceeds as follows (see Fig. VI.8): The largest capacitor Cn
is connected to ground, all others to Vref . The comparator is first reset, then activated in the
next step, where all capacitances except Cn are switched to Vgnd and Cn is switched to Vref .
Vref
k−1
2 C 2C C C
SA
SB
Vin
Figure VI.7: Successive approximation A/D converter, hybrid architecture
The nominal value of Cn is exactly half of the total value of the n + 1 capacitors, which is equal
to Cn + Cn−1 + ... + C2 + C1a + C1b . With ∆Cn being the matching error, Cn can be written as

Ctotal
Cn = + ∆Cn . (6.7)
2
The voltage at the comparator input Vx is twice the error voltage Ve[n] caused by the matching
error of Cn during normal operation. This error voltage is digitized in a successive approxi-
mation sequence with the resistor string type calibration DAC. The obtained digital correction
codes are stored in the data register. To determine the matching error of Cn−1 , Cn is con-
nected to Vgnd and the procedure described above is performed for Cn−2 , Cn−3 , ... to C1a . This
procedure is then repeated for all other capacitances.
The digital correction terms are calculated using the formula
i−1
!
1 X
DVe[i] = DVxi − DVe[j] (6.8)
2 j=1
Cn−2
Cn−1
Ccal
Reset
C1a
C1b
Cn
Voltage
Comparator
Vref
Vref Vref
Vgnd
m bits Sub-DAC
Cal-DAC
Data Register
Ve[n]
Ve[n−1]
Ve[n−2]
Dout Successive Approximation Register Control

Logic Ve[2]
Ve[1]
Figure VI.8: Successive-approximation A/D controller with error correction
During a regular conversion, the stored correction values for each MSB are added to the con-
version result if the corresponding bit is set to 1.
4 Algorithmic A/D converters

This type of converter uses the successive approximation algorithm as well, but, in this ar-
chitecture, not the reference voltage VRef or V at the comparator input is bisected in each
approximation step, but the remaining error voltage is doubled. Since a resistor or capacitor
string is not needed, this type of converter is especially advantageous in terms of area consump-
tion. Here, the critical point is the amplifier, the gain of which has to be exactly two.
out
Vin
S/H Cmp Shift register
V ref /4
X2 S/H
Gain amp −Vref /4
Figure VI.9: Schematic structure of an algorithmic A/D converter

A flow diagram of a signed algorithmic conversion with offset-coded output voltage is shown in
Fig. VI.10. Fig. VI.11 shows a SC amplifier with a constant gain of 2 which is auto-zeroing
Start
Signed input
Sample V = Vin , i = 1
No
V>0
Yes
bi = 1 bi = 0
V = 2( V −Vref /4 ) V = 2( V+ Vref /4 )
i =i+1
No
i >N
Yes
Stop
Figure VI.10: Flow diagram of an algorithmic A/D conversion
and independent of component matching. The error voltage is sampled (1) and the charge
Verr · C1 is stored on a second capacitor C2 (2). In the next step, Verr is sampled again (3),
so it has to be sufficiently stable during that period. Therefore, in Fig. VI.9 a S&H stage is
inserted before the amplifier. In step (4), the charge stored in C2 is transferred back to C1 , so
that the voltage over C1 equals 2 · Vin . Then, C1 is connected in between input and output of
the op-amp.
This multiply-by-two process needs 2 clock cycles. So, this space-saving architecture can be
implemented only at the cost of higher conversion time.
C2
C1
Verr −
+ − Cmp
Q1
+
1. Sample remainder and cancel input−offset voltage.

C2
− +
Q1
C1
Verr −
Cmp
+
2. Transfer charge Q1 and C1 to C 2 .

C2
− +
Q1
C1
Verr −
+ − Cmp
Q2
+
3. Sample input signal with C1 again, after storing charge Q 1 on C2 .

C2
C1
Verr −
+ − Cmp
Q1 + Q2 + Vout = 2Verr
4. Combine Q 1 and Q 2 on C1 and connect C1 to output.
Figure VI.11: SC-voltage amplifier for an algorithmic A/D converter independent of the
matching of the capacitances
5 Flash Converters
5.1 One-Step Flash Converters

As shown in Fig. VI.12, in a one-step flash converter the input signal is compared to the 2N
nodes of a resistor string in 2N comparators.
Vref
Vin
R
2
Over range
R
&
Vr7 1
R
&
Vr6 1
R
&
Vr5 1
R (2N − 1) to N N digital
& encoder outputs
Vr4 1
R
&
Vr3 1
R
&
Vr2 1
R
&
Vr1 1
Comparators
R
2
Figure VI.12: 3-Bit Flash A/D Converter
At the output of the comparators, the sampled input value can be read in thermometer-code
representation. One of the subsequent NAND-gates is connected to two neighboring nodes, the
lower of which is set to 1 and the upper one to 0. This NAND-gate has a 0 output, whereas
all others have a 1. This intermediate step facilitates the following 2N − 1-to-N encoding.
Furthermore, the appearance of more than one 0, which is characteristic for the ’bubble error’
described later in this chapter, is easy to detect.
Flash A/D converters are fast because of their high degree of parallel operation, but they require
a large number of comparators and, thus, large amounts of area and power.
For the design of fast flash converters, the following issues have to be observed:
• Input Capacitive Loading:

The capacitive load of 2N comparator inputs at the converter input may limit conversion
speed. This implies the need for a fast and strong input buffer and high power con-
sumption. Loading is reduced in architectures with more than one step, see following
sections 6.1 - 6.3 for more details.
• Comparator Latch-to-Track Delay:

The comparators are usually clocked to operate alternately in track and latch mode.
If the input signal of a comparator varies only slightly from the reference signal, the
transition from latch to track mode is exceptionally slow, in particular so at a change of
sign (comparator meta-stability). For this reason, the time constants of the internal nodes
of the latch have to be kept low. A reset after each latch-mode operation can provide
equalization and precharge, i.e. predefined internal comparator nodes are shorted and set
to specified potentials.
• Signal and Clock Delay :

No extra S&H circuit is needed at the converter input since the clocked comparators
perform this function. Slight variations of the sample time cause the clock jitter error
described in chapter II. Delays between clock and signal inputs of particular comparators
may lead to further errors. The error caused by delays on interconnects can be minimized
by appropriate symmetrical design.
• Substrate and Power-Supply Noise:

Peak currents and voltage fluctuations may be caused by steep slopes of clock signals
and fast switching operations on the supply lines. Feed-through leads to fluctuations
of the substrate voltage and thus of the threshold voltage of the transistors. These
phenomena can be countered by using separate power supplies for the analog and digital
parts of the circuit, the latter including clock signal generation and the latch stages of the
comparator. Further measures are stabilization of the analog supply voltage by integrated
capacitances, shielding the clock signal from analog signals and low-resistance well and
substrate contacts.
• Bubble Errors and Error Correction:

Incorrect comparator output signals caused by comparator metastability, noise, feed-
through etc. lead to faulty thermometer-code representations. This phenomenon, a 1
appearing between zeros or a 0 appearing between ones close to the transition between 0
and 1 is called bubble error. Most of these bubbles can be removed by using three-input
NAND gates (see Fig. VI.13) instead of two-input NAND gates in Fig. VI.12.
• Accuracy of the Comparator Voltages:

Flash A/D converters are often built in bipolar technology. For this reason, the differences
in the voltage drops because of base currents into the comparator inputs have to be
regarded in addition to resistor matching. The currents through the resistors should be
about a 100 times greater than the base currents. Therefore, it is advisable to partition the
resistor string and force the center tap voltage, where the error is greatest, to a predefined
value (Resistor-String Bowing). 1) A similar problem arises in CMOS implementations
where voltage taps do not have to provide DC currents; 2) but capacitive loading can
cause currents in the resistor string during comparator switching.
• Flashback:
Simple latched comparators generate current pulses at the comparator inputs during the
transitions between track and latch mode. Because of the different impedances at the
inputs – one is connected to the resistor string node, the other to the output of an op-
amp – unwanted voltage pulses of different height appear at the inputs, which may falsify
the comparator result. Multistage comparators with a differential amplifier followed by a
latch avoid this problem.
Vin
&
1
&
Vri 1
N
(2 − 1) to N N digital
outputs
encoder
&
1
&
1
Figure VI.13: Using three-input NAND gates to remove bubble errors
5.2 Interpolating A/D Converters
So-called ’folding’-architectures provide a possibility of reducing the complexity of flash con-

verters with relatively high resolution. In this type of architecture the comparator elements are
replaced by op-amps which operate linearly in the range of one quantization step of the input
voltage, but go into saturation for higher voltage differences.
A 4-bit interpolating A/D converter with an interpolation factor of 4 is shown in Fig. VI.14,
an appropriate transfer function of the comparators in Fig. VI.15.
Vref = 1V
Vin (Overflow)
V4 16
latch
R 15
latch
R 14
R latch
R 13
latch
V3 R 12
latch
0.75V
R 11
latch
R 10 b1
R latch
R 9 b2
latch
V2 R 8 Digital b3
latch
0.5V
R 7 Logic b4
V2c latch
R 6
R V2b latch
R 5
V2a latch
V1 R 4
latch
0.25V
R 3
latch
Input
amplifiers R 2
R latch
R 1
latch
R
Latch
comparators
Figure VI.14: 4-bit interpolating A/D converter
V1,V2a,V2b,V2c ,V2
5.0 V2
V2b
V1 V2c
Latch threshold
(Volts)
V2a
Vin
0
0 0.25 0.5 0.75 1.0 (Volts)
Figure VI.15: Transfer functions for the two lower input-comparators of the converter shown
in Fig. VI.14, and their interpolated signals
The delay times of the latches should be identical to ensure high-speed operation. This can be
done by inserting additional series resistors as shown in Fig. VI.16.
Vin
V2 R
8
latch
0.5V R R/4
7
latch
R
6
latch
R R/4 5
latch
V1 R R 4
latch
0.25V
Figure VI.16: Adding series resistors to equalize the delay times of the latches in Fig. VI.14
The main advantage of the interpolating method is the decrease in the number of comparators
connected to the input. This reduces capacitive loading of the input, power dissipation and the
number of different reference voltages. The interpolating approach can be realized with current
mirrors or capacitances in exchange for resistors as well ([1], chapter 13.6).
6 A/D Converters with Parallel Operation
6.1 Two-Step Flash Converters
Two-step flash or subranging converters employ a two-stage conversion approach as shown in

Fig. VI.17.
Vin
4−bit 4−bit
Vin 4−bit 16 LSB
MSB D/A V
A/D 1 Vq A/D
Gain amp
First 4 bits Lower 4 bits

(b 1 , b 2 , b 3 , b 4 ) (b 5 , b 6 , b 7 , b 8 )
Figure VI.17: 8-bit two-step Flash A/D converter
1. A/D flash conversion of the MSBs (4 MSBs in Fig. VI.17)
2. Multiplication of the difference between the analog input value and the reconverted value
of the first conversion by 16
3. Determination of the LSBs in another flash conversion step

The number of comparators necessary for this architecture is reduced drastically in comparison
with a one-step approach, e.g. from 256 to 32 in the example shown in Fig. VI.17. On the other
hand, the conversion time increases. An S&H circuit between the two steps allows pipelined
operation, i.e. the first stage can process a new value while the preceding sample is still being
processed in the second stage.
8-bit accuracy is required for all components on either stage of a 2 · 4 two-step flash converter.
This can be reduced to 4-bit accuracy for the first converter if digital error correction as well as a
5-bit converter in the second stage are implemented. ([1], chapter 13.5). However, requirements
placed on the D/A converter, the subtraction circuit and the S&H circuits remain unchanged.
6.2 Pipelined Converters
We know that an algorithmic A/D converter needs N cycles to generate one effective digital
output. This conversion style can be regarded as serial conversion. This serial conversion is
very slow in terms of total conversion time, but if an S&H is inserted after each step, transfer
rate can still be high. In many applications the transfer rate is the decisive value, while the
latency of N clock cycles is irrelevant. Every converter stage includes an S&H, a comparator,
b1
QN
DN
b2
N − 1 bit shift register
QN−1 QN−1
D N−2 D N−2
bN−1
Q1 Q1 Q1
D1 D1 D1
bN
CP
Vin 1−bit 1−bit 1−bit 1−bit

DAPRX DAPRX DAPRX DAPRX
(DAPRX − digital approximator)

Analog pipeline
Figure VI.18: Schematic block diagram of a pipelined A/D converter
an adder and an op-amp with a gain of 2. The conversion algorithm is equal to that of the
algorithmic converter discussed in section 4. The MSBs are delayed in shift registers so that
all bits belonging to one sample appear at the output simultaneously.

N comparators are needed for a pipelined converter as shown in Fig. VI.18, whereas a flash
converter would require 2N comparators working at equal speed to achieve the same transfer
rate.
So, space and power consumption can be reduced by using a pipelined converter design if total
conversion time is not an issue. Also, more than one bit can be converted in a pipeline stage
to reduce latency or to enable digital error correction.
6.3 Parallel Operation of Multiple A/D Converters

A simple but space- and power-consuming way to increase the transfer rate of an A/D con-
verter is to send successive samples of a signal to different converters (Time-interleaved A/D
converter). In the time-interleaved architecture shown in Fig. VI.19, the input voltage is sam-
Φ1
S/H N−bit A/D
Φ2
Φ0
S/H N−bit A/D
Φ3 Digital
Vin S/H Dig−
mux output
S/H N−bit A/D
Φ4
S/H N−bit A/D
Figure VI.19: Block diagram of a time-interleaved A/D converter
pled by a high-speed S&H with the clock signal Φ0 at the clock frequency fs . The sampled
values are distributed to 4 S&H stages clocked at clocks Φ1 to Φ4 , each at a frequency of fs /4
and delayed with respect to each other by the period of Φ0 . Thus, the speed required of the
A/D converters and the precision of the clocks Φ1 to Φ4 are reduced by a factor of 4. The
digitized output values are recombined to a stream with frequency fs by a digital multiplexer.
Good matching of the parallel channels is crucial for this architecture, since periodical unwanted
signals may appear otherwise, generating a tone with the frequency fms where m is the number
of channels.
Chapter VII
Oversampling Converters
1 Introduction
Oversampling converter designs trade in resolution in the frequency domain for resolution in
the time domain at the transfer from an analog to a digital signal. So, the requirements placed
on the accuracy of the analog components (matching, amplifier gain) are relaxed, while the
share of digital signal processing and its required speed increase. Since sampling frequencies
are significantly higher than signal frequencies, specifications of anti-aliasing filters in D/A
converters or low-pass filters in D/A converters are uncritical.
Oversampling A/D converters consist of two function blocks. Firstly, the modulator converts
the analog input signal to a series of coarsely quantized values. Usually, a 1-bit quantization is
performed. Then the digital filter, the so-called decimation filter, generates a series of digital
values with high resolution and low frequency from the oversampled digital signal. In Σ∆
converters, the principle of oversampling conversion is combined with noise shaping through
the use of feedback. Within the family of Σ∆ converters, high oversampling ratios can be
discarded in favor of more complex modulator structures with multiple stages.
2 Oversampling without Noise Shaping

When oversampling is used, the total noise power of the quantization noise is spread over a
larger frequency spectrum than if the Nyquist rate were used. Nevertheless, only the noise
power within the frequency spectrum counts for the calculation of the SNR.
In a linear model the quantizer adds the signal e[n], representing the quantization error or
quantization noise, to the input signal x[n], which sums up to the output signal y[n].
This linear model is accurate if the dependency of the error e[n] of the input signal is taken
into consideration. Under the common assumption of e[n] being ’white noise’ independent
of frequency, this model is only approximately exact. However, it is suitable to explain the
operation of an oversampling converter.
83
e[n]
x[n] y[n] x[n] y[n]
e[n] = y[n] − x[n]

Quantizer Model
Figure VII.1: Quantizer and its linear model
Se(f)
∆ 1
Height k x =
( )
12 fs
f
− fs 0
fs
2 2
Figure VII.2: Spectrum of the quantization noise at a sampling frequency of fs , assuming

that quantization errors are uniformly distributed.
2
As has been shown in chapter IV, the noise power of the quantization noise equals ∆12 , with ∆
being the difference between two subsequent quantization values VLSB (see equation 4.9). The
quantization noise spectrum, shown in VII.2, can be derived from
fs fs
∆2
Z Z
2 2
Se2 (f ) df = kx2 df = kx2 fs = (7.1)
− f2s − f2s 12
so that
fs fs
Se (f ) = kx σ f + −σ f − (7.2)
2 2
where r
∆ 1
kx = √ (7.3)
12 fs
Oversampling a signal with a bandwidth of f0 means that the sampling rate is (considerably)
higher than the Nyquist frequency, so fs >> 2f0 . The oversampling ratio (OSR) is defined as
fs
OSR = (7.4)
2f0
After quantization, the signal y1 [n] is limited to the signal bandwidth with a low-pass filter
according to Fig. VII.3. So, a large part of the quantization noise (as well as other unwanted
signals) is removed.
y1 [n]
u[n] H(z) y2 [n]
M−bit quantizer
(a)
|H(f)|
−f 0 f f
− fs fs
2 2
(b)
Figure VII.3: a) Schematic Structure of an oversampling A/D converter without noise shaping
b) transfer function of a low-pass filter to remove quantization outside the signal bandwidth
The power of a sinusoidal signal with maximum amplitude is equal to

M 2
∆2 ∆2 22M
Ps = √ = (7.5)
2 2 8
The signal power remains the same in the filtered output signal y2 [n], whereas the quantization
1
noise is reduced by OSR in comparison with the operation of an ideal Nyquist-rate converter.
Thus, quantization noise is reduced by 3 dB every time the OSR is doubled. Correspondingly,
the SNR increases by 0.5 bits. So, the following identity applies for sinusoidal signals:
SN Rmax = 6.02M + 1.76 + 10lg(OSR) (7.6)
Oversampling can be used both in A/D and D/A converters.

In oversampling D/A converters, a roughly quantized series of analog values is transformed into
a low-bandwidth, high-resolution signal by the use of a low-pass filter. The extreme case of a 1-
bit D/A is especially advantageous, since linearity requirements are not an issue. Oversampling
improves the SNR of the converted signal, but the requirement of integral linearity with an ac-
curacy of 21N remains, where N is the number of bits obtained after the LP filtering. Therefore,
converters with very high resolutions of > 10 . . . 12 Bit are not feasible without calibration.
Yet, 1-bit converters are inherently linear. There are only 2 output values and the connection
between the two output values is per se a straight line. If offset errors can be neglected, as for
example in audio applications, linearity requirements are ideally fulfilled. Other error sources,
like fluctuations of the supply voltage or the reference voltage depending on the input signal ,
parasitic capacitances etc. are disregarded here.
The advantage of inherent linearity makes 1-bit D/A converters a common choice for audio
applications, where, with noise shaping, 16 to 18 bits of resolution are reached. Furthermore,
the realization of the low-pass filter is simplified as mixing products of signal frequency and
sampling frequency appear outside the signal bandwidth and can easily be filtered.
3 Oversampling with Noise Shaping
3.1 Concept
The concept of oversampling with noise shaping can be applied in both A/D and D/A convert-
ers. Firstly, it will be explained for the A/D converter. Fig. VII.4 shows the block diagram,
Fig. VII.5 shows the modulator block and its linear model corresponding to Fig. VII.1.
xin (t) xc(t) x sh(t) x dsm[n] xlp [n] xs[n]
Anti− Sample− Digital

aliasing and− Σ∆ low−pass OSR
f0 fs mod fs fs 2f 0
filter hold filter
Decimation filter
Analog Digital
Figure VII.4: Block diagram of an oversampling A/D converter
x[n]
u[n] H(z) y[n]
Quantizer
(a)
e[n]
x[n]
u[n] H(z) y[n]
(b)
Figure VII.5: a) Σ∆ modulator, b) linear model of the modulator showing injected quanti-
zation noise e[n]
If the OSR is sufficiently high, a simple RC-element can be used for the anti-aliasing filter.
After being sampled, the signal is coarsely quantized in the Σ∆ modulator. Noise Shaping is
then performed by using a low-pass filter on the signal and a high-pass filter on the noise. Two
tasks are carried out in the digital filter stage of the decimation filter: Noise filtering and deci-
mation, i.e. transforming a 1-bit (or in general M-bit) data stream with a data rate of fs into
a data stream with higher resolution (N > M ) at a considerably lower data rate. Decimation
is simultaneously both an averaging function and a reduction of the word rate. The modulator
in Fig. VII.5.a is comprised of a summing stage, a filter with the transfer function H(z) and
a quantizer. The quantizer produces the quantized signal y[n]. This signal with low resolution
and high sample rate is routed back to the input in a feedback loop.
The realization of 1-bit modulators is especially simple. For example, a D-flipflop can be used
as quantizer. However, multi-bit oversampling converters are feasible as well.
If the input signals in the linear model VII.5.b are assumed to be independent, the following
signal transfer function STF and noise transfer function NTF can be derived:
Y (z) H(z)
ST F (z) ≡ = (7.7)
U (z) E(z)=0 1 + H(z)
Y (z) 1
N T F (z) ≡ = (7.8)
E(z) U (z)=0 1 + H(z)
The total output signal adds up to
Y (z) = ST F (z)U (z) + N T F (z)E(z) (7.9)
To achieve the desired noise shaping effect without falsifying the wanted signal, the magnitude
of H(z) has to be high within the frequency band of interest. In this range, STF will be
approximately unity. In the same range, NTF is near zero, and quantization noise is greatly
reduced while remaining large at higher frequencies. This so-called interpolating modulator
structure is similar to an op-amp operating in a unity-gain feedback configuration. The op-
amp gain is high for low frequencies, where noise generated by the op-amp is attenuated by
feedback. At higher frequencies, op-amp gain decreases and noise is left largely unchanged.
3.2 First-Order Noise Shaping
For the desired noise shaping effect, H(f ) should have a pole at (or near) f = 0, i.e. z = 1.
Poles of H(f ) produce zeros of NTF and ST F ≈ 1. The simplest function H(z) with the
required property is given by
1
H(z) = (7.10)
z−1
This is a discrete-time integrator function (explicit Euler method). Fig. VII.6 shows the block
diagram of a first-order Σ∆ modulator with this transfer function.
Equations 7.7 to 7.9 describe the operation of the linear model in Fig. VII.5.b for small input
x[n]
u(n) −1 y[n]
z
Quantizer
Figure VII.6: First-order Σ∆ modulator
signals. For larger input signals, it must be observed that the input signal u[n] has to remain
within the maximum levels of the feedback signal, as the signal x[n] will saturate otherwise. If,
for example, a 1-bit quantizer with feedback values of ± 14 Vref is used, the input signal has to
be limited to ± 41 Vref in the bandwidth in which H(z) is large, i.e. within the signal bandwidth.
The input voltage range is further reduced by constraints ensuring stability of the modulator.
In the time domain, this requirement for stability has the following effect: If the feedback is
operating correctly and the system is stable, the signal x[n] is bounded. As the integrator gain
is infinite for f = 0 (Fig. VII.6), the average value of the discrete-time integrator’s input must
be zero. Hence, the average value of u[n] equals that of y[n]. Again, this shows the similarity
of the interpolating modulator structure to an op-amp with unity gain.
In the z-domain, STF and NTF of a first-order modulator are
1
Y (z) z−1
ST F (z) = = 1 = z −1 (7.11)
U (z) E(z)=0 1+ z−1
Y (z) 1 −1

N T F (z) = = 1 = 1 − z (7.12)
E(z) U (z)=0 1 + z−1
The STF is simply a delay, the NTF is a discrete-time differentiation, i.e. a high-pass filter.
The magnitude of the transfer function for the quantization noise in the frequency domain is

πf f ≪fs 2π
|N T F (f )| = 2sin = |f | (7.13)
fs fs
The noise power of the unfiltered quantization noise is given in equation 7.1. Its noise power
in the signal bandwidth from 0 to f0 with first-order noise shaping is given by
2 2 3 2 2
3
∆ π 2f ∆ π 1
Pe ∼
0
= = (7.14)
12 3 fs 36 OSR
For the same signal power as in equation 7.5, the maximum SNR is now given by
SN Rmax = 6.02M + 1.76 − 5.17 + 30lg(OSR) (7.15)
With first-order noise shaping, doubling the OSR results in an SNR increase of 9dB or, equiv-
alently, a gain of 1.5 bit/octave, as compared to 0.5 bit/octave for oversampling without noise
shaping.
An SC-architecture of a first-order modulator with a 1-bit quantizer is shown in Fig. VII.7,
VII.8.
Comparator
u[n] z−1 B[n]
H(z)
1−bit D/A
y[n]
(a) Analog Digital
C
Φ1 C Φ2
Vin Comparator
Φ2 Φ1
Vout
Φ2, (Φ1) C
Vref /4
Φ1, (Φ2) Latch on Φ2 falling
(b) Φ1 , Φ2 Vout high

(Φ1),(Φ2) Vout low
Figure VII.7: First-order Σ∆ modulator a) Block diagram, b) Analog SC implementation
3.3 Second-Order Noise Shaping
Fig. VII.9 shows a second-order modulator. The first integrator is free of delays (implicit Euler
method). STF and NTF are given by
ST F (f ) = z −1 (7.16)
2
N T F (f ) = 1 − z −1 (7.17)
The magnitude of the NTF is given by

2
πf
|N T F (f )| = 2sin (7.18)
fs
The noise power in the signal bandwidth amounts to

5
∆2 π 4

1
Pe ∼
= (7.19)
60 OSR
and, corresponding to equations 7.5 and 7.15, the maximum SNR for a sinusoidal input signal
is given by
SN Rmax = 6.02M + 1.76 − 12.9 + 50lg(OSR) (7.20)
Φ1 C Φ2
Vin Comparator
Φ2 Φ1
Vout
Latch on Φ2 falling
Vref −Vref
2 2
Figure VII.8: First-order Σ∆ modulator - Analog SC implementation II
u(n) z−1 y[n]
z−1 Quantizer
Figure VII.9: Second-order Σ∆ modulator
Thus, doubling the OSR results in a 15 dB increase of the SNR of a second-order modulator,
or, equivalently, a gain of 2.5bit/octave. Fig. VII.10 shows the NTF of modulators of dif-
ferent noise-shaping orders. With higher orders, noise attenuation decreases within the signal
bandwidth, whereas noise power at higher frequencies increases.
3.4 Comparison of First- and Second-Order Modulators
The modulator architecture that is most commonly used is the second-order modulator. This
structure requires two integrators, whereas first-order modulators require only one. Yet, this
more complex circuit design has a number of advantages: Besides the fact that SNR is improved,
one of the main advantages in comparison to first-order modulators is a drastic reduction of
certain repeating patterns in the output signal of the modulator for DC input signals. These
patterns are highly autocorrelated and result in so-called ’tones’ in the spectrum. Tones are
discussed in chapter 3.6.2. These spectral components cause a reduction of the resolution of a
Application Baseband Resolution Sampling Frequency

Voice 8 kHz 13 4.1 MHz
Hi-Fi Audio 40 kHz 16 82 MHz
ISDN data transmission 300 kHz 13 154 MHz
Table VII.1: Sampling frequency of a first-order modulator for different applications

Second−order
|NTF|
First−order
No noise shaping
0 f
fs fs
f0
2
Figure VII.10: Transfer functions of converters of different noise-shaping orders
Application Baseband Resolution Sampling Frequency

Voice 8 kHz 13 446 kHz
Hi-Fi Audio 40 kHz 16 5.2 MHz
ISDN data transmission 300 kHz 13 16.71 MHz
Table VII.2: Sampling frequency of a second-order modulator for the applications listed in
VII.1
Σ∆ A/D converter.
Single-bit second-order modulators are more stable than higher order structures, and they place
low requirements on gain and bandwidth of the op-amps used in the integrators. Requirements
of the internal A/D and D/A converters are low as well. Therefore, a simple comparator can
be used for internal A/D conversion. In contrast to ’multi-bit’ converters, no linearity errors
will occur in this structure. Offset and hysteresis characteristics of the comparator used in
a second-order modulator are uncritical. Moreover, this architecture is not very sensitive to
variations of the modulator coefficients. A deviation of these coefficients from the default values
of 10% caused no deterioration in the resolution of a second-order modulator with OSR =32
and SN R =58 dB (J. Sauerbrey, al.: ESSCIRC 2002).
3.5 Higher-Order Modulators
There are a number of factors influencing the resolution attainable with a Σ∆ modulator.
Important characteristics are:
PCM Output Bit Stream
t (Ts)
Figure VII.11: Bit-stream at the output of a first-order Σ∆ modulators for a sinusoidal input
signal
• oversampling ratio
• (noise-shaping) order of the modulator
• type of filter function
• topology
• number of discrete quantization values of the internal A/D and D/A converters
Basic topologies for Σ∆ modulators are non-cascaded modulators that are also called ’single
loop’ modulators, and cascaded modulators. Cascaded modulators are mostly comprised of
non-cascaded modulators of either first or second order.
It is common to all modulators that the attainable resolution increases with the oversampling
rate. The order of a modulator is equal to the order of the noise filter function. Therefore,
the higher the order of the modulator is, the higher the attainable resolution. A comparison
of the attainable resolutions of different modulators of the same order shows that not only the
noise-shaping order, but also the filter transfer function greatly influences the overall transfer
function. Modulator topology and number M of quantization values of internal A/D and D/A
converters are of particular influence when realizing higher-order modulators, i.e. modulators
of an order greater than two.
3.5.1 Non-Cascaded Modulators with Orders > 2
In general, an L-th order noise-shaping modulator improves the SNR by (6L + 3)dB/octave,
or equivalently (L + 0.5) bit/octave, see Fig. VII.14. For a reduction of the clock frequency
of an M bit modulator, its noise shaping order has to be increased. The easiest way to do so
Normalized Power (dB)

−50
−100
40dB/dec
−150
1 10 100 1000
Frequency (kHz)
Figure VII.12: Output spectrum of a second-order modulator

0 0
−50 −50
−100 −100
−150
0 200 400 600 800 −150 6 8 10 12 14 16 18
Frequency (kHz) Frequency (kHz)
Figure VII.13: Baseband of the output spectrum
is adding additional integrators to a second-order modulator. The ideal noise transfer function
of this third-order modulator would then show triple differentiating behavior. However, this
type of modulator structure is not stable if a 1-bit quantizer is used. Therefore, a noise transfer
function has to be chosen that brings maximum improvements in comparison to a second-order
converter, but does not jeopardize modulator stability. Furthermore, when designing non-
cascaded, higher-order modulators it has to be taken into account that sensitivity to variations
of the modulator coefficients increases with the attainable resolution. Thus, the choice of
suitable coefficients for a modulator structure is always influenced by the tolerable amount of
coefficient mismatch.
For the determination of the filter function, commonly a filter design method combining a
system simulator and an optimization tool is used. Usually, a high-pass filter function with
Butterworth behavior forms the basis of the noise transfer function. The modulator transfer
200
180 1
2
160 3
140
SNRmax 120
100
80
60
40
20
16 32 64 128 256
OSR
Figure VII.14: Maximum SNR of single-bit Σ∆ modulators versus noise shaping order
function is then derived from the noise transfer function and simulated with the system simula-
tor. The attainable resolution can be calculated from the output bit stream. The coefficients of
the noise transfer function can then be tuned with the optimization tool to maximize converter
resolution. Stability of the modulator as well as input magnitude decrease with rising loop
gain. The optimization tool determines the coefficient values such that a margin in stability
exists to account for coefficient mismatch. Fig. VII.16 shows a third-order Σ∆ modulator,
z−1 Comp
u[n] 0.136
z−1
1−z−1 z−1 y[n]
1−z−1 1−z−1
0.136
0.618
1.22
Figure VII.15: Architecture of a third-order modulator, including three integrators, one com-
parator and three feedback loops.
the coefficients of which were determined in the way described above. Its STF and NTF were
found to be:
0.136z −3
ST F = (7.21)
1 − 1.78z −1 + 1.178z −2 − 0.262z −3
(1 − z −1 )3
NT F = (7.22)
1 − 1.78z −1 + 1.178z −2 − 0.262z −3
It is important to note that the signal is not only delayed, but also filtered to a small extent,
as shown in Fig. VII.17.
z−1 Comp
u[n] 0.136
z−1
1−z−1 z−1
1−z−1 y[n]
1−z−1
0.136
0.618
1.22
Figure VII.16: Architecture of a third-order modulator, including three integrators, one com-
parator and three feedback loops.
20
Normierte Amplitude (dB)
−20
−40
−60
−80
0 0.2 0.4 0.6 0.8 1
Normierte Frequenz
Figure VII.17: STF of the modulator shown in Fig. VII.16; normalization to ST F (z = 1)

and 12 fs
Different transfer functions can be realized by choosing the summation coefficients and the gain
of the individual integrator stages accordingly. The fifth-order filter shown as second example
in Fig. VII.18 contains two resonance loops, the resonating frequencies of which are determined
by the internal feedback factors f1 and f2 . By choosing the resonating frequencies adequately,
the zeros of the NTF can be distributed over the signal bandwidth instead of positioning them
at f = 0 as in the first example.
3.5.2 Cascaded Modulators
In cascaded or MASH-Architectures (Multi-StAge noise SHaping), higher-order modulators are

designed by interconnecting first- and second-order modulators, which are inherently stable as
has been shown before. A simple example is illustrated in Fig. VII.19: The quantization error
u[n]
c1 c2 c3 c4 c5
f1 f2
y[n]
a1 a2 a3 a4 a5
Figure VII.18: Block diagram of a fifth-order modulator
u(t) z −1
z −1 · U + (1 − z −1)e1
e1
1-bit D/A z −1
y[n]
e1 e2
z −1
z −1
1-bit D/A
Analog Digital z −1 · e1 + (1 − z −1) · e2
Figure VII.19: Second-order cascaded modulator composed of two first-order modulators
of the first modulator, e1 [n], is digitized, filtered and subtracted in a digital adder stage from
the output signal signal of the first modulator. The remaining quantization noise has been
filtered twice:
Y (z) = z −2 U (z) − (1 − z −1 )2 E2 (z) (7.23)
As second-order modulators show good stability anyway, cascaded architectures are only use-
ful for orders higher than two. A third-order converter can be designed by cascading three
first-order modulators or a second-order modulator and a first-order one. The latter solution
combining a second-order modulator for the first stage and a first-order one for the second
stage is advantageous because of its smaller sensitivity to variation of coefficients. The noise
at the input of the second stage has already undergone second order high-pass filtering and
non-idealities in the second stage are less present in overall behavior of the modulator.
Fig. VII.20 shows the architecture of a cascaded third-order modulator. Its signal transfer
function ST F (z) and its noise transfer function N T F (z) are
ST F = z −3 (7.24)
−1 3
N T F = (1 − z ) (7.25)
The output signal of this cascaded modulator is only delayed, not filtered. It contains triple
differentiated quantization noise. As two delaying integrators are used in the second-order filter
(explicit Euler method), the feedback to the second integrator is amplified by 2 for operation in
accordance with STF and NTF defined in equations 7.16 and 7.17. The cascaded third-order
modulator consists of three integrators, two comparators and three summing stages. Hence, the
circuit structure is slightly more complex than that of the non-cascaded third-order modulator.
The digital 2bit output signal y is generated by combining the 1bit signals y1 and y2 in a simple
digital filter block. The filter function appropriate to generate the modulator output signal is
specified in Fig. VII.20.
Comparator
z −1 z −1
u(t) 1 1−z −1 1−z −1 y1[n]
2
1
Comparator
z −1
1 1−z −1 y2[n]
1
Y (z) = z −1Y1(z) − (1 − z −1)2Y2(z)
Figure VII.20: Architecture of a cascaded third-order modulator
Requirements placed upon op-amps regarding gain and bandwidth by a cascaded third-order
modulator are only slightly greater than those of non-cascaded modulators. The requirements
placed upon the comparators are comparable to those of a second-order modulator. Cascaded
modulators tolerate variations of their coefficients of about 3%, which is considerably less than
the tolerance of second-order modulators. If variations are greater, the attainable resolution
will decrease, mostly due to insufficient cancellation of quantization error generated in the first
stage. In contrast to non-cascaded modulators, coefficient variations do not affect stability of
third-order modulators.
Fig. VII.21 shows the NTF of three modulators. The NTF of the cascaded modulator is the
transfer function of the quantization noise generated in the second quantizer, as the quantiza-
tion noise generated in the first quantizer is eliminated by the first-oder modulator in the second
stage. The second-order non-cascaded modulator and the third-order cascaded modulator show
20
0 nichtkaskadierter
Amplitude (dB)
Modulator
2. Ordnung
−20
nichtkaskadierter
−40 Modulator
3. Ordnung
−60 kaskadierter
Modulator
3. Ordnung
−80
0 0.2 0.4 0.6 0.8 1
Normierte Frequenz
Figure VII.21: Comparing the noise transfer functions of the modulators from figs. VII.9,
VII.16 and VII.20.
differentiating high-pass filtering behavior. The behavior of the non-cascaded third-order mod-
ulator shown in Fig. VII.16 is similar to that of a cascaded third-order modulator in lower
frequency bands. For higher frequencies, the noise transfer function rises faster than that of a
cascaded third-order modulator. For high frequencies it drops off slightly.
3.6 Stability and Scaling

3.6.1 Scaling
The modulator architectures described in section 3 have signal and noise transfer functions
adequate for Σ∆ modulators. For the design of such a transfer function, magnitudes at the
intermediate nodes of the architecture are not an issue; they are, however, relevant in the
design of the analog circuit: The magnitude of the input signal u[n] of a first-order modulator
must not be greater than that of the feedback signal y[n] for correct operation. Otherwise, the
internal node x[n] will go into saturation due to the high gain of H(z). Thus, in the modulator
design shown in Fig. VII.7, Vin must remain within the voltage range ±Vref /4. The average
magnitude at the node x[n] is then zero, but maximum magnitude may be as high as ±VRef /2.
The input voltage range is more difficult to specify for higher-order modulators.
Additionally, stability is an issue. As the quantizer, an inherently nonlinear element, forms
part of the feedback loop, default methods for the design of stable systems, e.g. controlling the
position of the poles in the z-plane, are insufficient. Systems can be stable for wide ranges of
input signals, yet go unstable at certain signals. One example for this are tones, see section 3.6.2.
A limitation of the NTF to a factor of 1.5 for 1-bit quantizers may serve as a rule of thumb.
For some architectures, especially simple single-loop structures, necessary and sufficient sta-
bility criteria have been specified. Yet, their application results in very small tolerable signal
magnitudes, so that thermal noise increases. So, a pragmatic method to design a stable system
would be to simulate the system using sinusoidal input signals and ideal integrator models.
The voltages at the integrator outputs are plotted in histograms. Generally, this method can
be used to adjust signal magnitudes by scaling coefficients in a way that the maximum magni-
tudes appearing at a node equal the boundaries of the permitted voltage ranges of the analog
circuit. This, however, leads to big differences between the magnitudes at the different nodes of
a modulator and therefore leaves a large fraction of the available dynamic range unused. Yet,
as the available dynamic range is small anyway due to low supply voltages, it should be used
to maximum extent nowadays. This can be done by employing a linear scaling method.
The modulator, exempting the comparator, can be seen as a linear time-invariant (LTI) system.
Thus, the linear parts of the modulator can be scaled according to the principles of LTI sys-
tems. This way, the maximum amplitudes at the integrator outputs can be scaled to adequate
voltages.
in 0.375 z−1 z−1

0.6
1−z−1 out 1
1−z−1
Comp 1
0.225
0.275
0.1
z−1
0.727 out 2
1−z−1
Comp 2
0.2
out(z) = z −1out1(z) + 2 out2(z) (1 − z−1 )2
Figure VII.22: Architecture of the third-order modulator from Fig. VII.20, scaled for low
supply voltages
In Fig. VII.22, the modulator shown in Fig. VII.20 has been scaled in a way that the maximum
amplitudes of the input signal do not exceed the 0.7-fold of the reference voltage. So, the out-
put signals of the integrators are adapted to the operating range of the op-amps. Furthermore,
the input section of the modulator is scaled to reach maximum amplitudes of roughly 0.3 Vref .
Thus, the tolerable input voltage range is adapted to the operating range of the switches at
the input. Linear scaling does not influence the modulator transfer function. Its only aim is to
adapt the voltage amplitudes to the requirements of the analog circuitry.
3.6.2 Tones and Dithering
Modeling quantization errors as statistically uniformly distributed noise is an idealization only

appropriate for input signals that vary quickly. If the input signal is a DC voltage, the output
signal will be a periodic series of bits. For example, if u[n] = 1/3 is the input signal of a
first-order modulator, the repetition rate will be fs /3. Other DC voltages will produce lower
repetition rates, leading to noise power peaks at certain frequencies within the signal bandwidth
that will not be eliminated by the low-pass filter subsequent to the modulator. The noise power
Figure VII.23: Formation of tones dependent on the value of a DC input voltage in a first-
order Σ∆ modulator with OSR = 128
of such tones at low frequencies (idle tones) is lower for second-order modulators because of
their stronger noise-shaping. Nevertheless, filter structures in higher-order converters may as
well be favorable for tones at certain frequencies.
If tones are a source of errors in a system, a so-called dithering signal can be used for their
prevention. Such a signal with ’white’ spectrum is added to the output signal of the last
integrator. The dithering signal can be generated by a random number generator with only a
few bits of resolution. An additional D/A converter is needed for dithering in an A/D converter,
whereas only a digital adder is required in a D/A converter.
Dither signal
u[n] H(z) y[n]
Quantizer
Figure VII.24: Adding a dithering signal in a Σ∆ modulator
The effect of the dithering signal is a perturbation of the periodic data series. Its noise power,
which would generate a tone of a certain frequency, is spread over a broader range of frequencies.
The noise power of the dithering signal should be similar to that of the quantization noise,
which is made possible by noise shaping being performed both on quantization noise and the
dithering signal. The dithering signal adds about 3 dB to the total noise power within the
signal bandwidth. Besides, noise power in higher frequency ranges increases, which has to be
observed for stability considerations and the design of the decimation filter (see below).
4 System Architecture of ∆Σ converters
4.1 Signals and Spectra
The block diagram of a complete converter system, see Fig. VII.4, shows analog and digital
components, the output signals of which are plotted in Fig. VII.25.
The S & H circuit is often comprised in the modulator input, so the signal xsh (t) may not
be physically present in the circuit. The modulator output is a 1-bit signal xdsm [n] which has
spectral components at low frequencies that depend on the input signal with N bits of resolution.
In addition, it contains a large proportion of noise power outside the signal bandwidth which
has to be removed by the decimation filter. Basically, this can be done in two steps: A digital
low-pass filter removes the quantization noise at frequencies higher than f0 . The multi-bit, high-
frequency signal xlp [n] is the result. 1 This low-pass filter removes other high-frequency spectral
components as well and therefore also serves as anti-aliasing filter for the cut-off frequency f0
(The anti-aliasing filter at the input only has to remove spectral components with frequencies
higher than fs /2 from xc (t) ). xlp [n] is then sub-sampled with the sub-sampling ratio L = OSR;
thus, in Fig. VII.25, only 1 out of 6 sampled values is used. The output signal xs [n] contains
the same information as xlp [n], but it is spread over the complete bandwidth of the normalized
sampling frequency ranging from 0 to π.
Word length and data rate of the signal xlp [n] are both high. The processing of such a signal
1
Digital filters consist of delay elements, multipliers and adders. The gain of resolution results from the
multivalued signals created during data processing, the representation of which requires a larger number of
bits
xc(t) x sh(t) X c(f)
t f0 fs f
Xsh(f)
x dsm[n]
f0 fs f
3
1 2 4... n X dsm (Ω)
xlp (n) 2πf 0 /f s 2π Ω
X lp(Ω)
1 2 3 4... n
2πf 0 /f s 2π Ω
xs(n) X s (Ω)
2 3...
1 n π 2π 4π 6π 8π 10 π 12 π Ω
Time Frequency
Figure VII.25: Signals in a Σ∆ A/D converter and their spectra; OSR = 6 for better demon-
stration, typically, OSR = 32 . . . 128
requires complex digital circuits with high power dissipation. For this reason, the functions of
low-pass filter and sub-sampling are combined in the design of the decimation filter.
The resolution attainable with a Σ∆ A/D converter depends on two main factors. One is that
thermal noise must not be greater than quantization noise. The input capacitors of the first
integrator are the decisive elements here. They also serve as S & H capacitors for xc (t). The
following relation has to apply:
4kT (SN R)2
Cs > (7.26)
OSR A2
Here, A is the signal amplitude the SNR is specified for. As the capacitors limit the input
bandwidth and increase area consumption as well as power dissipation, their values should not
be chosen larger than required.
The other main factor determining resolution is the linearity of the D/A converter in the
feedback loop. Nonlinearity of the A/D converter is not as relevant since it is compensated by
large gain.
4.2 Decimation Filter
Two common structures for decimation filters are a multi-stage architecture made up of a
SINC-filter (sinc x = sinx
x
) and an IIR-filter or multiple half-band filters, and single-stage
architectures.
i+1
sinc
Lth−order Rate = fs Rate = 8f 0 Rate = 2f 0
∆Σ Tsinc (z) TIIR (z)
modulator
FIR filter IIR filter
(a)
Rate = fs Rate = 8f 0 Rate = 4f 0 Rate = 2f 0

Lth−order Rate = 2f 0
∆Σ Tsinc (z) H1(z) H2(z) H3(z)
modulator
Halfband FIR filters
Sinc L + 1 FIR filter Sinc compensation
FIR filter
(b)
Figure VII.26: Multi-stage decimation filters
In Fig. VII.26, the first stage of a multi-stage filter is a FIR filter Tsinc (z). A large portion
of the quantization noise is removed here already so that the signal can be sampled down to
the quadruple Nyquist rate, i.e. 8 · f0 . This output signal with low data rate (already with the
final word length) is further reduced to bandwidth f0 in the second filter stage. The SINC-filter
ought to be one order higher than the noise-shaping function of the modulator, i.e. sincL+1 , so
that the slope of the low-pass filter’s transfer function is greater than the slope of the increase
of the quantization noise outside f0 . This way the remaining noise is reduced at frequencies
only slightly higher than f0 .
The SINC-filter can be composed of a cascade of L+1 averaging filters with the individual
transfer functions
M −1
Y (z) 1 X −i
Tavg (z) = = z (7.27)
U (z) M i=0
where M = fs /8f0 . On the unit cycle in the z-plane, the transfer function (7.27) is given by
sinc ωM

jω 2
Tavg e = (7.28)
sinc ω2
The transfer function of the sincL+1 filter is

L+1
1 1
Tsinc (z) = (1 − z −M )L+1 L+1 (7.29)
1−z −1 M
which points out different possibilities for implementation. A favorable realization of the sinc-
filter is shown in Fig. VII.27.
in out
fs
z−1 z−1 z−M z−M M
(Integrators) (Differentiators)
(a)
in out
fs
z−1 z−1 M z−1 z−1
fs fs f s /M f s /M
(b)
(Operate at high clock rate) (Operate at low clock rate)
Figure VII.27: sincL+1 -Filter: a) Downsampling just before the output, b) Downsampling
between integrators and differentiators
4.2.1 Single-Stage Architectures
Alternatively, decimation can be performed by a single FIR filter, the order of which is suffi-
ciently high. For instance, an FIR filter with 2048 filter nodes can be used for decimation of 2
audio channels (Nyquist frequency 48 kHz) with an OSR of 64 per channel ([1], chap. 14.4.).
One advantage of single-stage architectures is that no multi-bit multiplications are required, as
the input signal is a 1-bit stream. In this example, 2048 additions have to be performed during
1
one cycle of the Nyquist frequency fN yquist . If necessary, pipelined or parallel operation can be
used to reduce the required operating speed of the digital unit.
4.3 Multi-bit Modulator Structures
4.3.1 Multi-bit Modulators
Depending on the number of quantization stages M of the internal A/D and D/A converter,
’single-bit’ modulators are distinguished from ’multi-bit’ ones. The resolution of the converter
increases by 6.02dB for every additional bit in the quantizer. For architectures with given
resolution the OSR may be lower which reduces the requirements on circuit speed and power
dissipation. This applies especially for the slew rate of the first amplifier because the maximum
step size of the D/A converter output voltage decreases proportionally to 2M . Because of the
quantization process, nonlinearity errors are less prominent in multi-stage converters than in
single-bit modulators. Better stability, less pronounced formation of tones as well as attenuation
of unwanted signals in the supply lines are the result.
A drawback of multi-stage solutions is that, unlike inherently linear 1-bit quantization, non-
linearity of the D/A converter causes nonlinearity of the modulator, the consequence of which
is harmonic distortion in the output signal. Resolution of the D/A converter required in this
context may only be a few bits, but its accuracy has to equal the resolution of the NF-signal at
the converter output with a clock frequency considerably higher than that of the output. For
this reason, thermometer-code converters with 2M similar units are often used in conjunction
with error-shaping techniques to reduce nonlinearity of the D/A converter.
4.3.2 Dynamic Element Matching
As the sample rate of a Σ∆ converter is considerably higher than the signal bandwidth f0 ,
one linearization method is especially advantageous for oversampling converters: Possibly mis-
matched elements are continually exchanged at random. On average, the effective value of an
element of a thermometer-code DA/converter is then the average value of the 2M nominally
equal elements.
C
C
Thermometer−type decoder
Eight−line randomizer
b1 C
b2 C
Analog
output
b3 C
Figure VII.28: Dynamic Element Matching in a 3-Bit-D/A converter
Static mismatch is thus converted to a broadband error signal which can be removed in the
decimation filter to a large extent.
4.3.3 Dynamic Calibration of Current Sources
Each of these 2M nominally equal elements is cyclically matched to a reference element. The
calibration value is stored as a voltage on a capacitor. This ”dynamic matching of current
sources” is shown by the example of a 6-Bit thermometer-code converter in Fig. VII.29. This
method can be used both for oversampling and Nyquist-rate converters.
Shift register
0 0 1 0 0 0 I ref
I d1 I d2 I d3 I d4 I d5 I 64
Switch network
To D/A
Figure VII.29: Dynamic matching of current sources
4.3.4 Digital Error Correction
M bit
x 2 [n]
u[n] H(z) NL y[n]
Digital correction
NL
x1[n]
Nonlinear D/A
Figure VII.30: Multi-bit A/D modulator with digital error correction
Even if the D/A converter of a multi-bit modulator shows nonlinearity, the feedback loop
provides that its output signal x1 [n] equals the input signal u[n] within the signal bandwidth.
The quantizer output signal x2 [n] deviates from the correct value in a way that the feedback
condition is fulfilled at the input. If the value of the nonlinearity error is known for each
of the 2M possible input values, it can be compensated for by a digital correction unit. A
simple implementation for this would be a RAM where x2 [n] is a register address and y[n] the
corresponding data word. The word width of y[n]is 2N , similar to the NF resolution of the
converter; its data rate is fs . Nevertheless, this would greatly increase complexity and power
dissipation of the decimation filter. Therefore, y[n] is converted to a smaller word width in a
digital Σ∆ stage.
While the unit is in calibration mode, the 2M different digital output words are fed to the input
of the A/D converter during at least 2M clock cycles each. The M-bit modulator is then used
in 1-bit operation, i.e. only the MSB is used for feedback and its transfer function is inherently
linear. After low-pass filtering, the output signal deviates from the predefined input value by
the nonlinearity error of the D/A converter.
Digital calibration can also be used for cascaded modulators with multi-bit quantizers.
5 Σ∆ - D/A - Converters
The principle of oversampling with noise shaping can also be applied to D/A converters, yielding
similar improvement of the SNR (equations 7.15, 7.20). The series of digital values xs [n]
xs[n] x s2[n] xlp [n] x dsm[n] x da(t) xc(t)

Interpolation ∆Σ 1−bit Analog
OSR (low pass) low pass
2f 0 fs filter fs Mod fs D/A filter
fs
OSR
2f 0
Digital Analog
Figure VII.31: Block diagram of a 1-bit Σ∆ D/A converter
represents a signal sampled at 2f0 with N bits resolution. f0 is chosen slightly higher than
the highest wanted frequency present in the signal (For example: Digital Audio Processing:
Sampling Frequency 20 MHz, Signal Bandwidth 2f0 = 44 kHz). Spectra plotted over the
normalized sampling frequency Ω = 2πf 2f0
(sampling at Nyquist rate) are shown in Fig. VII.32.
Zeros are inserted into the data stream to create a series of values xs2 [n], similar to an signal
oversampled at the sampling rate fs . The corresponding spectrum is derived by normalizing
the frequency axis to Ω = 2π fs
.
Large portions of xs2 [n] outside the signal bandwidth f0 are removed in a digital interpolation
filter. This low-pass filtering generates the data series xlp [n], which is then fed to a digital Σ∆
modulator. It creates the 1-bit stream xdsm [n], which is converted to the analog signal xda (t)
in a 1-bit D/A converter. The resulting signal contains xlp [n] within the bandwidth f0 , yet,
additionally, it contains high quantization noise power. Corresponding to the noise shaping
transfer function of the modulator, most of its power is outside the signal bandwidth f0 . A
low-pass smoothing filter finally creates the output signal xc (t).
The output filter can be made up of a combination of SC filter elements and analog filter
stages. In addition to the before mentioned advantage of 1-bit converters being highly linear,
the principle of oversampling is also favorable in respect to the realization of the smoothing
filter. Whereas Nyquist-rate converters require steep filter characteristics to eliminate periodic
spectral patterns at high frequencies, oversampling converters generate these periodic patterns
far outside the signal bandwidth. The required narrow-band filter function is implemented
digitally in the generation of xlp [n]. The order of the analog smoothing filter’s transfer function
xs[n] x s2[n] X s (Ω)
(2) (3)
1 2 3...
(1) n π 2π 4π 6π 8π 10 π 12 π Ω
X s2 (Ω)
xlp [n]
2πf 0 /f s 2π Ω
X lp(Ω)
1 2 3 4... n
2πf 0 /f s 2π Ω
x dsm[n] x da(t)
X dsm (Ω)
n,t
2πf 0 /f s 2π Ω
X da(f)
xs(t)
f0 fs f
t
X c (f)
f0 fs f
Time Frequency
Figure VII.32: Signals and their spectra in a Σ∆ D/A converter
should be one higher than that of the noise shaping filter of the modulator to overcompensate
the slope of the quantization noise in xdsm at the boundaries of f0 .
Quantization noise is prevalent in the range of frequencies around 21 fs . The low-pass filter
has to be highly linear so as not to generate products of frequency mixing inside the signal
bandwidth.
Multi-bit modulators can be used for Σ∆ D/A converters with the advantages mentioned above
as well. Moreover, noise power in the HF-range will decrease. This relaxes requirements placed
upon analog low-pass filters even more.
φs
u(t) H(s) y[n]
Quantizer
DAC
Continuous time Discrete time
circuitry circuitry
Figure VII.33: Block diagram of a CT Σ∆ modulator
u(t) H1(s) S/H H2(z) y[n]
Quantizer
DAC
Continuous time circuitry Discrete time circuitry
Figure VII.34: Continues time filter plus discrete time filter to implement a CT Σ∆ modulator
6 Continuous Time Σ∆ - Converters
SC filters impose high requirements on the bandwidth of the operational amplifiers within the
integrator stages. This can be circumvented by performing the filtering in the continuous time
(CT) domain. The S&H stage is inserted between the filter and the comparator as shown in
Fig. VII.33 or may be realized within the comparator input.
By pushing the sampling operation into the noise shaping loop, S&H errors are noise shaped
as well. The DAC is now the most critical part of the loop, as it must produce continuous time
signals with high precision. E.g. clock jitter will enter directly into the transfer function, which
is not the case for the discrete time realization. Consequently, continuous time sigma delta
converters allow for a very high sampling frequency but cause additional analog implementation
challenges which are summarized in Table VII.3 which compares discrete time and continuous
time implementations of a sigma delta converter.
Mixed implementations are also possible, where the first and most critical filter stages are CT
and the last ones are SC filters, i.e. the S&H as a border between CT and discrete time
signals is situated within the filter block. Fig. VII.34 show another implementation of CT Σ∆
modulator with 2 stages of filters. The first stage is a continues time filter and the second stage
is a switch capacitor filter to further filter out the high frequency components.
Discrete Time Continuous Time

Anti-Aliasing Fil- Explicit anti-aliasing filter re- Implicit filtering → AAF may be
ter quired obsolete for some applications
Sampling Sampling at input → low jitter & Sampling at comparator, i.e.
full linearity required for sampler within Σ∆-loop → sampling er-
ror subject to noise shaping
Max. frequency All transients must settle within Continuous time waveforms → 5-
and bandwidth of half of clock cycle, quickly chang- 10x relaxed bandwidth require-
opamps ing pulses everywhere in circuit ments → higher clock frequency
→ high bandwidth requirements possible
limit max. frequency
Jitter Only critical for sampler but not Very sensitive to timing varia-
for rest of sigma delta modulator tions of clock
Loopdelay Not an issue Very sensitive to loop delay
Switches Signal dependant on resistance No switches
Signal dependant Not an issue Very sensitive → causes harmonic
comparator delay distortion
Feedback-DAC Low sensitivity to waveform set- Very sensitive to waveform and
tling not critical settling, limits linearity of mod-
ulator
Process variations Filter transfer function based on Filter transfer function depends
capacitor ratios → very robust on RC constants, i.e. very sen-
sitive to variations
Noise generation Switching generates noise Reduced supply and ground noise
Table VII.3: Comparison of Discrete Time and Continuous Time Σ∆ - Converters
CT implementations are particularly suited for bandpass Σ∆ modulators, where signals with
high center frequency and small bandwidth are processed.
7 Bandpass - Σ∆ - Converters
In addition to being useful for NF-range conversion, the principle of noise shaping can be applied
to the conversion of high-frequency, narrow-band signals. For this application, a bandpass
transfer function is chosen for the filter H(z) in Fig. VII.5. In simple systems, its function can
be performed by a resonance circuit operating at the center frequency fc of the input signal.
Typical applications are the processing of RF-signals for broadcasting and communication with
typical center frequencies of some 10 MHz as well as spectral analysis and other measurement
applications.
Quantization noise is shifted from the range around the carrier frequency fc to other frequencies
z−plane z−plane
fs/4 = 1 MHz −zero fs/4 = 1 MHz −zero
dc f∆ dc
2f0
fs = 4 MHz fs = 4 MHz
fs/2 fs/2
f0 = 10 kHz f∆ = 10 kHz
fs fs
(a) OSR = = 200 (b) OSR = = 200
2f0 2f∆
Figure VII.35: Zeros of the NTF of Σ∆ modulators:

a) first-order low-pass modulator
b) second-order bandpass modulator
H(z)
u(n) z−1 y(n)
z−1 Quantizer
Figure VII.36: Second-order bandpass modulator; quantization noise is attenuated at 14 fs
where it can be eliminated using a bandpass filter. For example, the poles of H(z) are positioned
at z = ±j in a bandpass Σ∆ modulator where fs = 4 fc (Fig. VII.35). The bandpass modulator
shown in Fig. VII.36 realizes this transfer function. It is defined as follows:
z
H(z) = (7.30)
z2 +1
with poles at ±j.
The two zeros of the NTF are a complex conjugate pair. The SNR is improved by 1.5Bit/octave,
i.e. 9 dB/octave, like in a first-order low-pass modulator. A fourth-order bandpass modulator
would have to be used to attain noise shaping comparable to that of a second-order low-pass
modulator, i.e. 15dB/octave. For bandpass Σ∆ modulators, not the carrier frequency is the
value relevant for the sampling theorem, but the signal bandwidth: fs > 2∆f . The factor 2 is
important to avoid aliasing with spectral components in the negative frequency range.
References
[1] D.A. Johns; K. Martin. Analog Integrated Circuit Design. Wiley, 1997.
[2] S.I.A. ITRS, International Technology Roadmap for Semiconductors. 2001.
[3] R.J. Baker; H.W. Li; D.E. Boyce. CMOS, Circuit Design, Layout and Simulation. Wiley,
1997.
[4] R. Gregorian; G.C. Temes. Analog MOS Integrated Circuits For Signal Processing. Wiley,
1986.
[5] U. Tietze; Ch. Schenk. Electronic Circuits. Handbook for Design and Application. Springer,
2002.
[6] A.V. Oppenheim; R.W. Schafer. Zeitdiskrete Signalverarbeitung. Oldenbourg, 1999.
[7] S.R. Norsworthy; R. Schreier; G.C. Temes. Delta-Sigma Data Converters. IEEE Press,
1997.
[8] R. Schreier; G.C. Temes. Understanding Delta-Sigma Data Converters. IEEE Press, 2005.

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GIST TUM Asia

Institute for Technical Electronics

PD Dr. Stephan Henzler

II Sample and Hold Circuits 17

III Switched-Capacitor-(SC) Circuits 23

IV Analog-to-Digital and Digital-to-Analog Converter Fundamentals 41

5.1 Static Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

V Nyquist-Rate D/A Converters 53

VI Nyquist-Rate A/D Converters 65

VII Oversampling Converters 83

Analog CMOS (or possibly BiCMOS) in digital processes:

Table I.1: Conditions for mixed-signal circuits in a System-on-a-Chip(SoC)

Anti−aliasing−filter Digital code Smoothing

Figure I.1: Typical Structure of a mixed-signal system

1 Structure of Mixed-Signal Systems

s(t) x[n] = xc(nT)

x sh(t) x[n] = xc(nT) ysh(t)

xc(t) Sample D/A Analog yc (t)

2 Discrete-Time Signals, Laplace and z-transform

The Laplace transform, which is defined by

xc (t) analog, time continuous input signal

Table I.2: Description of the signals in Fig. I.1

0 rad/sample = 0 cycles/sample π /8 rad/sample = 1/16 cycles/sample

π /4 rad/sample = 1/8 cycles/sample π /2 rad/sample = 1/4 cycles/sample

Figure I.4: Sampling sinusoidal signals with different frequencies

3 Upsampling and Downsampling

Figure I.6: Upsampling by adding zeros

again will repeat the resulting spectrum.

5 z-transform of a Step Function

The step function is time-continuous and its Laplace transform is equal to

Sample and Hold Circuits

Vin Chld Vout

Figure II.1: Schematic structure of a sample & hold circuit

1 Errors in Sample and Hold Circuits

Vin Chld Vout

Overshoot and settling time S/H output

Acquisition time Hold mode

Sample command Hold command

Figure II.3: Sources of errors in sample-and-hold circuits

Possible errors in sample mode:

Possible errors in hold mode:

2 Noise Considerations with Sampled Signals

3 Characteristic Parameters of thermal noise

SvR = 4kT R (2.3)

vR2 = 4kT R∆f (2.4)

Figure II.4: Noise equivalent circuit of an RC element

The spectral power density Svn,out at the output is given by

Svn,out = |H(jω)|2 SvR (2.7)

1 Concept of Switched-Capacitor Circuits

node N2 . This results in transfer of the charge

circuit equivalent type

2 Clocking of Switched-Capacitor Circuits

3 Impact of Parameter Variations on RC & SC Circuits

4 Realization of Integrated Capacitors

substrate with active

5 Validity of the SC-Equivalence

z = exp(jωT ) ≈ 1 + jωT (3.21)

6.1 Operation Principle

and A/D converters: