AN532

APPENDIX B:
Combination quadrature decoder and input synchronizer. This design
allows 1x decoding or 4x decoding based on the X4 pin.

* Ver 1.0 - November 8, 1991

}
MODULE QuadDivider;
TITLE QuadDivider V1.0;
COMMENT Device: 16R8;

TYPE MMI 16R8;

INPUTS;
RESET NODE[PIN2] INVERTED;
X4 NODE[PIN3];
P0 NODE[PIN4]; { Phi0 }
P90 NODE[PIN5]; { Phi90 }
INDX NODE[PIN6];
{ Feedback pins }
S2 NODE[PIN12];
S4 NODE[PIN13];
P0D NODE[PIN14];
P90D NODE[PIN15];
CntUp NODE[PIN18];
CntDn NODE[PIN19];
UP NODE[PIN16];
COUNT NODE[PIN17] INVERTED;
OUTPUTS;
S2 NODE[PIN12];
S4 NODE[PIN13];
P0D NODE[PIN14];
P90D NODE[PIN15];
CntUp NODE[PIN18];
CntDn NODE[PIN19];
UP NODE[PIN16];
COUNT NODE[PIN17] INVERTED;
TABLE;
S2 := P0D & !RESET;
S4 := P90D & !RESET;
P0D := P0 & !RESET;
P90D := P90 & !RESET;

CntUp := COUNT & UP;

CntDn := COUNT & !UP;

COUNT :=
( P0D & S2 & !P90D & S4 & X4{ C1 }
+!P0D & !S2 & P90D & !S4 { C2 }
+!P0D & S2 & !P90D & !S4 & X4{ C3 }
+ P0D & !S2 & P90D & S4 & X4{ C4 }
+ P0D & S2 & P90D & !S4 & X4{ C5 }
+ P0D & S2 & P90D & S4 { C6 }
+!P0D & S2 & P90D & S4 & X4{ C7 }
+ P0D & !S2 & !P90D & !S4 & X4{ C8 }
) & !RESET;
UP :=
(
!P0D & S2 & !P90D & S4
+!P0D & S2 & P90D & S4
+!P0D & S2 & P90D & !S4
+ P0D & S2 & P90D & !S4
+ P0D & !S2 & P90D & !S4
+ P0D & !S2 & !P90D & !S4
+ P0D & !S2 & !P90D & S4
+!P0D & !S2 & !P90D & S4
) & !RESET;
END;

END QuadDivider;

DS00532C-page 14 1997 Microchip Technology Inc.