module b8_4bit_dec_assign_logic(in,out,enable);

input enable;
input [3:0] in;
output [15:0] out;

assign out[0] = !in[0] & !in[1] & !in[2] & !in[3] & enable;
assign out[1] = in[0] & !in[1] & !in[2] & !in[3] & enable;
assign out[2] = !in[0] & in[1] & !in[2] & !in[3] & enable;
assign out[3] = in[0] & in[1] & !in[2] & !in[3] & enable;
assign out[4] = !in[0] & !in[1] & in[2] & !in[3] & enable;
assign out[5] = in[0] & !in[1] & in[2] & !in[3] & enable;
assign out[6] = !in[0] & in[1] & in[2] & !in[3] & enable;
assign out[7] = in[0] & in[1] & in[2] & !in[3] & enable;
assign out[8] = !in[0] & !in[1] & !in[2] & in[3] & enable;
assign out[9] = in[0] & !in[1] & !in[2] & in[3] & enable;
assign out[10] = !in[0] & in[1] & !in[2] & in[3] & enable;
assign out[11] = in[0] & in[1] & !in[2] & in[3] & enable;
assign out[12] = !in[0] & !in[1] & in[2] & in[3] & enable;
assign out[13] = in[0] & !in[1] & in[2] & in[3] & enable;
assign out[14] = !in[0] & in[1] & in[2] & in[3] & enable;
assign out[15] = in[0] & in[1] & in[2] & in[3] & enable;

endmodule

module testbench;
reg enable;
reg [3:0] binary;

wire [15:0] binary_out_logic;

b8_4bit_dec_assign_logic b8_4bit_dec_assign_logic(
.in(binary),
.out(binary_out_logic),
.enable(enable)
);

initial
begin
enable = 1;
binary = 0;
end

always #10 binary=binary+1;

initial
$monitor("enable=%b, binary=%b, binary_out_logic=%b",
enable, binary, binary_out_logic);

endmodule