DMAC: Direct Memory Access

Controller

INSAT – A.U 2018/19

 Data Transfers
Code Memory Processor Data memory Periph Periph Periph
(Instructions) (Données) USART Ethernet ADC
Code
Bus
3

2
1 Brid
ge
Data bus Peripheral Bus

Data Transfers are done frequently:

1- From Periphs Interfaces To Memory
2- From memory to perihs Interfaces
3- From Memory To Memory
 Data Transfers
Instructions for transfering Data:
Mémoire Code Processeur Memory Periph Periph Periph
(Instructions) (Registres) USART Réseau ADC
dataBuf[DataSize] ; Code
Bus
Data
for (i = 0; i<=DataSize; i++) {
2 1
Data[i] = *Periph_addr;
} Brid
ge
Data bus Periphera Bus
Mov Ri, *Periph_addr ;

Mov Data[i] , Ri

Each Transfer Instruction involves 2 Bus Access from processor (Read + Write) :Time
consuming instructions.

For Etherent, USB Interfaces (Mbytes)  Processor Performances strongly degraded

 Data Transfers
A task (with repetitive instructions) consuming a large amount of the processing resources

Is replaced by a Hardwired Circuit : a SPP (Single Purpose Processor)

The SPP Data Transfers are ensured by the DMAC : Direct Memort Access Controller

Transfer Requests to DMAC (Channels)

Processor DMAC
(Master) (Master)

USART ADC Ethernet

(Slave) (Slave) (Slave)

Bridge
Data Bus (with Access Arbitration) Peripheral Bus
 DMAC Strcuture
• A DMAC is a Control Peripheral containing
DMA
registers that can ba accessed by the processor.
Channel N
• A DMAC manages many channels.
Channel.
Transfer Requests
From Peripherals to
Channel. • Each Channel accepts Transfer Requests from a
channels Channel 1
limited number of peripherals
@source

@destination
• When active, a Channel ensures a transfer from a
Processor Taille source to a destination. The registers contents
Etat transfert
indicate:
Buffer
- Source Address.
Reg Config Arbitrage - Destination Address.
Bus
- Data Size to be transfered.
Data Bus (with Arbitration) - etc ……
 Data Transfer with DMAC
all the processor should do is to configure the DMAC Channels (Src, Dest, Size, etc …)

Code Memory Processor Memory DMAC (Chan i)

(Instructions)

Code
Bus @src Periph

@dest

Taille

Bridge
Data Bus (with Arbitration) Peripheral Bus

The DMAC is responsible for the configured Data Transfer(s)

At the same time, the processor can process the instructions

DMAC in STM32F1
SOCs
BUS MATRIX
DMA Controller 1: 7 Channels

Peripheral

memory
STM32F1 : DMAC Registers
 DMAC Channel Configuration
DMA_InitTypedef DMA_InitStructure;

DMA_InitStructure.

DMA_InitStructure.

DMA_InitStructure.
 DMAC Channel Configuration

DMA_InitStructure.

DMA_InitStructure.

DMA_InitStructure.

DMA_InitStructure.

DMA_InitStructure.

DMA_InitStructure.

DMA_InitStructure.
DMA_InitStructure.
DMAC Channel Configuration
DMAC Channel Configuration
DMAC Channel Configuration
DMAC Channel Configuration
DMAC Channel Configuration
DMA Interrupts
 DMAC Register Addresses

• Adresse de base DMA1: 0x 40020000 Adresse de base DMA2: 0x40020400

Canal x 1 2 3 4 5 6 7
Offset d’un canal x : 0x08 + (x-1)*0x14
Offset 0x08 0x1C 0x30 0x44 0x58 0x6C 0x80

Registre CCRx CNDTRx CPARx CMARx

Offset d’un registre
Offset 0x00 0x04 0x08 0x0C

Adresse du registre d’un canal x du DMAy = Adr de base du DMAy + offset canal x + offset du registre

Exemple: @ du registre CPAR du canal 5 du DMA 2 = 0x40020400 + 0x58 + 0x08 = 0x40020460

 DMAC Interupts : Use case

Periph
Data
(Src)

Memory
(Dest)

Data from peripheral must be transfered from peripheral to Memory and processed (N Bytes) by the
Cortex-M3.

Memory Buffer Size = ?

Interrupts to be used ?
 DMAC Interrupts : TC only

Ressources du processeur gaspillées Periph

Data
(Src)

processor
Memory
TC TC

DMA (Dest) TC

Lancer Transfert (mode Normal) Transfert DMA Traitement (processeur Cortex)

TC: Transfer Complete

 DMAC Interrupts : TC & HT

Periph
Utilisation optimale des ressources du processeur Data
(Src)

1 2 1 2 1 2
processor
Memory

HT HT HT HT
TC 1
TC TC

DMA 2 1 2
2
1 1 2

TC

Lancer Transfert (mode Normal) Transfert DMA Traitement (processeur Cortex)

TC: Transfer Complete HT: Half Transfer

 DMAC HAL Functions (Mem2Mem)

HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, Start Mem to mem DMA

Transfer
uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength )

HAL_StatusTypeDef HAL_DMA_Start _IT (DMA_HandleTypeDef *hdma, Start Mem to mem DMA

Transfer and enable DMAC
uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength ) interrupts generation

Example:
RxBuffer[N]=‘’………………….’’;
TxBuffer[N]=‘’………………….’’;
HAL_DMA_Start (&hdma_memtomem_dma1_channely, TxBuffer, RxBuffer, 20); //y : can be 1 to 7
 DMAC HAL Functions (Mem / Periph)
HAL_StatusTypeDef HAL_PPP_Receive_DMA (PPP_HandleTypeDef *hppp,
uint8_t *pData ,
Start DMA Transfer :The periph PPP
generates a Transfer Request when
it receives Data.
uint16_t Size) Interrupts are enabled

Start DMA Transfer :The periph PPP

HAL_StatusTypeDef HAL_PPP_Transmit_DMA (PPP_HandleTypeDef *hppp, generates a Transfer Request when
the Transmit Buffer is empty
uint8_t *pData , uint16_t Size) Interrupts are enabled.

Example: Receiving 20 characters using DMA Transfer From UART2

Char RxBuffer[20]; ppp : can be UART, SPI, I2C, etc ….
HAL_UART_Receive_DMA(&huart2, RxBuffer, 20)
 DMA HAL Functions – Mem2Mem Interrupts
1 - DMA Interrupts Callback Functions prototypes must be declared by user

void Callback_Function_Name (DMA_HandleTypeDef *DmaHandle);

2 - Register The Callback Function « just after initialization (HAL_DMA_Init) » :

HAL_StatusTypeDef HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma,

HAL_DMA_CallbackIDTypeDef CallbackID,
void (* pCallback) ( DMA_HandleTypeDef * _hdma))

CallbackID: HAL_DMA_XFER_CPLT_CB_ID /* Full transfer */

HAL_DMA_XFER_HALFCPLT_CB_ID /*!< Half transfer */
HAL_DMA_XFER_ERROR_CB_ID /*!< Error */
Example :
HAL_DMA_RegisterCallback( &hdma……., HAL_DMA_XFER_CPLT_CB_ID , CallBackFunction_Name);

3 - Add the Callback Function code.

DMAC programming with
Cube MX
Memory To Memory DMA Transfers

DMA Channel Configuration

 Memory To Memory DMA Transfers

DMA Interrupt Configurtation

(NVIC)
UART DMA Transfers