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ZCU208 Dds Ila 2020p2 RevA Released
ZCU208 Dds Ila 2020p2 RevA Released
ZCU208 Dds Ila 2020p2 RevA Released
John Lantz
RF and System IO Specialist
john.Lantz@xilinx.com
06/23/2021
XILINX CONFIDENTIAL
Introduction
˃ This is an example starter design for the RFSoC
˃ It will utilize the ZCU208 board
˃ Uses a DAC and ADC sample rate of 1.47456 GHz
˃ The DAC will continuously play 10 MHz sine wave from the DDS Compiler IP.
˃ The ADC output will be sent to a System ILA to be displayed in the Hardware Manager.
˃ DAC Tile228(0) Ch0 will be used (LF balun)
˃ ADC Tile226(2) Ch0 will be used (LF balun)
˃ 2020.2 Xilinx tools (Vivado and Vitis)
˃ Design tested in the directory c:\rfsoc\ex_des\zcu208\v3\
˃ This kit comes with the Vivado HW project and SW source files.
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Demo Block Diagram
ARM PS
External Coax
AXI Streaming DAC to ADC
DDS 184.32 MHz DAC Tile0 Ch0 10MHz-1GHz
Loopback
Fs = 1.47456GHz SMA
Compiler IP Interpolation x8
Balun
Laptop
Vivado
Vitis
JTAG Interface to ZCU208
AXI Streaming
184.32 MHz ADC Tile2 Ch0 10MHz-1GHz
System ILA Fs = 1.47456GHz Balun
SMA
Decimation x8
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CLK104 Block Diagram
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Data Converter Clocking
CLK104/ZCU208
184.32 MHz DAC AXIS Clock
clk_dac0
ADC AXIS Clock
LMK04828B
184.32 MHz
DCLK_OUT6 DAC228
184.32 MHz
DCLK_OUT12 ADC226
184.32 MHz
DCLK_OUT4 LMX2594
184.32 MHz
DCLK_OUT0 LMX2594
LMX2594 outputs are
powered down but
there is a reference
clock to the inputs
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DAC Setup
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ADC Setup
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Data Converter Clocking
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Board setup for the upcoming designs
˃ Connect DAC Tile 228 Ch0 output to ADC Tile 226 Ch0 input on XM655 (low frequency balun
connections)
˃ Set SW2 to on,on,on,on (JTAG boot mode)
˃ Connect USB to host for JTAG, PS UART and System Controller UART access
SW2
1. Extract the design kit to an appropriate folder, be mindful of the Windows path length requirement.
2. Extract vv.xpr.zip which is the Vivado project.
3. Software source files in the “src” folder.
4. Design documentation in the .pdf file.
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Open Hardware Design and Generate the Bitstream
Extract vv.xpr.zip, open the design in Vivado and generate the bitstream.
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DAC Sine Wave Generator (DDS Compiler IP)
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Export Hardware
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Export Hardware Con’t
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Open Vitis
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Create Platform Project
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Create Platform Project Con’t
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Create Platform Project Con’t
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Create Platform Project Con’t
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Create Platform Project Con’t
Modify BSP
settings
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Enable libmetal
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Build Project This may take
a few minutes
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Build Complete
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Create Application
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Create Application Con’t
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Create Application Con’t
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Create Application Con’t
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Create Application Con’t
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Create Application Con’t
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Import Sources
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Build Application
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Build Complete
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Run Design
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Open a terminal window
Open the COM port on the compute
and set the rate to 115200.
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Setup Run Configuration
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Run Configuration Con’t
Double
Click
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Run Configuration Con’t
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Run Design
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Application Startup
The application…
1. Programs the clocks
2. Issues the data converters
master reset.
3. Displays the Power-on
Sequence Step of the data
converters.
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Open Hardware Manager
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Open New Target
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Open Hardware Target
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Open Hardware Target Con’t
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Convert Data to the Analog Waveform Style
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Analog Settings
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Radix
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System ILA Capture
Automatically retrigger Trigger ILA capture
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Boot Image
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Create Boot Image
To run the
application from
the SD card rather
than directly from
Vitis create the
boot.bin file
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Create boot.bin file
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Boot from SD card
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