LAB 5

DATA ANALYSIS

For Table 4-1, the configuration is a half-adder circuit and has the concept of addition of binary wherein
the value of ‘S’ (sum) will get a HIGH value when the inputs are different from each other, else 0. While
the value of ‘C’ carry will get a HIGH value when both inputs are HIGH, else 0. For table 4-2, the
configuration is a full-adder circuit which has 3 inputs and has the same concept of addition of binary is
applied here in Table 4-2. For table 4-3, a 2 half -adder circuit is the same as full-adder configuration
therefore the values are the same with Table 4-2. For table 4-4, the circuitry displays BCD value from 0 -
9. As bit increases, the bit values are placed in 8 4 2 1 BCD Code.

CONCLUSION

Combinational circuits are composed of adder circuits: half adder which means 2 inputs and 2 outputs.
While a full adder has 2 or more input signals are combined to give a certain output. Encoder's main
purpose is for bits to bits digital code conversions. Decoder means for a given binary input, only 1 output
is specific compared to others. Parity generator is a method of error detection for transmitting data
using even or odd parity. Multiplexers allow multiple input signals to a single output. The student
successfully completed the experiment. Combinational circuits are the fundamentals to more complex
digital systems. The student appreciated the different categories as these will be used in the future
lessons in Digital circuits.

RECOMMENDATION

The students recommend testing the IC’s voltage continuity as these gates were used multiple times in
previous experiments. The students also recommend to research on the internet about the manual as it
have defects that result in confusions and misunderstandings about the experiment.

LAB 6

DATA ANALYSIS

For table 5-1, For the RS Flip flop using NAND logic gate the reset state requires an input of 0(S) and 1(R)
that results to an output of O(C) and 1(C'), while the set for the said latch requires an input of 1(S) and
0(R) that results to an output of 1(C) and 0(C’). For high inputs For both S and R however, the output
only copies the present state it was in before changing it to 1-1 inputs. 0-0 inputs on the other hand is
invalid considering that C= C’ is not true. In Table 5-2, for this flip flop using NOR gate, inputs 0-1 (S-R) is
the reset state and inputs 1-0 (S-R) is the set state. It looks similar to table 5-1 because the C and C' for
the said table is not the same output for D and D' in this table. Additionally, inputs 0-0 is the hold or no
change state for NOR gate, while 1-1 inputs is invalid or not used.
CONCLUSION

SR flip- flops are basically SR latches with NAND gates. It is the fundamental circuit and used in
sequential logic circuits. It has two inputs: Set (S) and Reset (R), and two outputs: Q and Q'. The
students successfully performed the experiment as the concepts were understood. Truth table were
also analyzed and applied to the actual experiment. It is also used in digital circuits for memory storage,
latch circuits, and basic sequential logic.

RECOMMENDATION

The students recommend testing the IC’s voltage continuity as these gates were used multiple times in
previous experiments. The students also recommend to research on the internet about the manual as it
has defects that result in confusions and misunderstandings about the experiment. The students also
recommend to practice compact wiring of circuitry since as technology evolves, electronics become
smaller as well.

LAB 7 D FLIPFLOPS

DATA ANALYSIS

In this laboratory exercise with the D FLIPFLOPS, it is examined with different combinations of inputs of
D and T. With the outputs of Q and Qnot are observed for each combinations. In table 6-1 when both D
and T are 0 the outputs HOLDS the previous state. When inputs are both 1 the outputs became 1 also
and wgen D is 1 and T is 0 , the outputs hold their previous state . And lastly when inputs are both 1 the
Q becomes 1 and Qnot 0. For table 6-2 when D is 0 and T is 1 , Q becomes 0 amd Qnot is 1. When D is 1
and T is 0 , q becomes 1 and qnot becomes 0. The remaining combination will hild the previous state.
And fir table 6-3 the outputs are based on momentary application of sw A, indicating more detailed
explanation of D flip-flops behavior.

Conclusion

This laboratory exercise allows the students to demonstrate the behavior and characteristics of an D flip-
flops in any possible input combinations.this behavior is consistent with the operation of D flip-flops
which stores the data and output datawhen triggered by inputs combinations.

In this hands-on laboratory exercise, students have the opportunity to explore and illustrate the
behavior and features of a D flip-flop under various input scenarios. Think of a D flip-flop as a tiny
electronic memory cell that can store information. The exercise involves observing how this flip-flop
responds to different combinations of inputs.
A D flip-flop operates in a way that aligns with its intended function – storing data until it's prompted to
release that information based on specific input combinations. Picture it as a tiny storage box that holds
onto a piece of data until someone presses the right buttons to retrieve it. This experiment provides a
practical demonstration of how the D flip-flop holds and outputs data in a manner consistent with its
design and intended operation. It serves as a valuable hands-on experience for students to understand
the inner workings of digital circuits and memory elements.

Recommendations

This laboratory exercise is done by simulating it online , i suggest that this kinds of laboratory exercise
are simulated actual amd physically. And some contents of this laboratory mabual has faulty letters and
information.

LAB 8 JK

Analysis of data

For table 7-1-1 the jk flip-flops with j and k are set both 1 . In this combination, the flip-flop operates as a
toggle switch. When clk is 1 the Q output toggles between 1 and 0 with each rising edge of clk signal.
This is toggle mode where the outputs changes it states in response to each clk pulse.

In table 7-1-2 the J and k are set in 0 both inputs , the flip-flop function has no changes . Regardless of
the clk input, the outputs remain in their present state. This is expected behavior of a jk flip-flops with j
and k set to 0as it retains its current state when not toggles.

For table 7-2 the jk flipflops separates the j and k inputs. When j is 0 and k is 0 the output will hold the
state. When j is 0 and k is 1 the flipflops resets to 0 on the rising edge of clk. Conversely when j is 1 and k
is 0 the flipflops sets to 1 on the rising edge of clock. And when both j and k are 1 the flipflop toggles its
states with each rising edge of clock.

Conclusion

This laboratory exercise allows the students to simulate and demonstrates the unique behavior of jk
flipflops based on different possible combinations of j and k and the clk inputs the flippflop can operate
as a toggle switch, hold state , set function and reset function.

Lab 9
The student observed the operation of 7493 binary counter as a synchronous 4 bit binary counter.
systematically