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Embedded Processer - Merged PDF
Embedded Processer - Merged PDF
Embedded Processer - Merged PDF
Q.1 Features of UART in LPC2148 UART0 Divisor Latch holds the value by
• 16 byte Receive and Transmit FIFOs • which the PCLK(Peripheral Clock) will be
Register locations conform to ‘550 industry divided. This value must be 1/16 times the
standard. • Receiver FIFO trigger points at 1, desired baud rate.
4, 8, and 14 bytes. • Built-in fractional baud A 0x0000 value is treated like a 0x0001 value
rate generator with autobauding capabilities. as division by zero is not allowed.
• Mechanism that enables software and The Divisor Latch Access Bit (DLAB) in
hardware flow control implementation. U0LCR must be one in order to access the
UART0 Registers- UART0 Divisor Latches. (DLAB = 1)
1.U0RBR (UART0 Receive Buffer
Register)
1. It is an 8-bit read only register.
2. This register contains the received data.
3. It contains the “oldest” received byte in
the receive FIFO.
4. If the character received is less than 8 4. U0FDR (UART0 Fractional Divider
bits, the unused MSBs are padded with Register)
zeroes. It is a 32-bit read write register.
5. The Divisor Latch Access Bit (DLAB) in It decides the clock pre-scalar for baud rate
U0LCR must be zero in order to access generation.
the U0RBR. (DLAB = 0) If fractional divider is active (i.e.
DIVADDVAL>0) and DLM = 0, DLL must
be greater than 3.
U0FDR (UART0 Fractional Divider
Register)
2. U0THR (UART0 Transmit Holding U0FDR (UART0 Fractional Divider
Register) Register)
1. It is an 8-bit write only register. If DIVADDVAL is 0, the fractional baudrate
2. Data to be transmitted is written to this generator will not impact the UART0
register. baudrate.
3. It contains the “newest” received byte in Reset value of DIVADDVAL is 0.
the transmit FIFO. MULVAL must be greater than or equal to 1
4. The Divisor Latch Access Bit (DLAB) in for UART0 to operate properly, regardless of
U0LCR must be zero in order to access whether the fractional baudrate generator is
theU0THR. (DLAB = 0) used or not.
Reset value of MULVAL is 1.
The formula for UART0 baudrate is given
below
3. U0DLL and U0DLM (UART0 Divisor MULVAL and DIVADDVAL should have
Latch Registers) values in the range of 0 to 15. If this is not
U0DLL is the Divisor Latch LSB. ensured, the output of the fractional divider is
U0DLM is the Divisor Latch MSB. undefined.
The value of the U0FDR should not be Bit 0 - Interrupt Pending
modified while transmitting/receiving data. 0 = At least one interrupt is pending
This may result in corruption of data. 1 = No interrupts pending
Bit 3:1 - Interrupt Identification
Identifies an interrupt corresponding to
theUART0 Rx FIFO.
5. U0IER (UART0 Interrupt Enable 011 = Receive Line Status (RLS) Interrupt
Register) 010 = Receive Data Available (RDA)
It is a 32-bit read-write register. Interrupt
It is used to enable UART0 interrupt sources. 110 = Character Time-out Indicator (CTI)
DLAB should be zero (DLAB = 0). Interrupt
U0IER (UART0 Interrupt Enable Register) 001 = THRE Interrupt
U0IER (UART0 Interrupt Enable Register) Bit 7:6 - FIFO Enable These bits are
Bit 0 - RBR Interrupt Enable. It also controls equivalent to FIFO enable bit in FIFO
the Character Receive Time-Out interrupt. Control Register,
0 = Disable Receive Data Available interrupt 0 = If FIFOs are disabled
1 = Enable Receive Data Available interrupt 1 = FIFOs are enabled
Bit 1 - THRE Interrupt Enable Bit 8 - ABEO Interrupt
0 = Disable THRE interrupt If interrupt is enabled,
1 = Enable THRE interrupt 0 = No ABEO interrupt
Bit 2 - RX Line Interrupt Enable 1 = Auto-baud has finished successfully
0 = Disable UART0 RX line status interrupts Bit 9 - ABTO Interrupt
1 = EnableUART0 RX line status interrupts If interrupt is enabled,
Bit 8 - ABEO Interrupt Enable 0 = No ABTO interrupt
0 = Disable auto-baud time-out interrupt 1 = Auto-baud has timed out
1 = Enable auto-baud time-out interrupt
Bit 9 - ABTO Interrupt Enable
0 = Disable end of auto-baud interrupt
1 = Enable the end of auto-baud interrupt 7. U0LCR (UART0 Line Control
Register)
It is an 8-bit read-write register.
It determines the format of the data character
that is to be transmitted or received.
6. U0IIR (UART0 Interrupt
U0LCR (UART0 Line Control Register)
Identification Register)
U0LCR (UART0 Line Control Register)
It is a 32-bit read only register.
Bit 1:0 - Word Length Select
U0IIR (UART0 Interrupt Identification
00 = 5-bit character length
Register)
01 = 6-bit character length
U0IIR (UART0 Interrupt Identification
10 = 7-bit character length
Register)
11 = 8-bit character length
It provides a status code that denotes the
Bit 2 - Number of Stop Bits
priority and source of a pending interrupt.
0 = 1 stop bit
It must be read before exiting the Interrupt
1 = 2 stop bits
Service Routine to clear the interrupt.
Bit 3 - Parity Enable 0 = Break interrupt status inactive
0 = Disable parity generation and checking 1 = Break interrupt status active
1 = Enable parity generation and checking This bit is cleared when U0LSR is read.
Bit 5:4 - Parity Select Bit 5 - Transmitter Holding Register
00 = Odd Parity Empty
01 = Even Parity 0 = U0THR has valid data
10 = Forced “1” Stick Parity 1 = U0THR empty
11 = Forced “0” Stick Parity Bit 6 - Transmitter Empty
Bit 6 - Break Control 0 = U0THR and/or U0TSR contains valid
0= Disable break transmission data
1 = Enable break transmission 1 = U0THR and U0TSR empty
Bit 7 - Divisor Latch Access Bit (DLAB) Bit 7 - Error in RX FIFO (RXFE)
0 = Disable access to Divisor Latches 0 = U0RBR contains no UART0 RX errors
1 = Enable access to Divisor Latches 1 = U0RBR contains at least one UART0 RX
error
This bit is cleared when U0LSR is read.
9. U0TER (UART0 Transmit Enable
Register)
8. U0LSR (UART0 Line Status Register)
Operation modes
Handler mode: When executing an exception
handler such as an Interrupt Service Routine
(ISR). When in handler mode, the processor
always has privileged access level.
Thread mode: When executing normal
application code, the processor can be either in
privileged access level or unprivileged access
level. This is controlled by a special register
The 4GB address space of the Cortex-M called “CONTROL.”
processors is partitioned into a number of Programmer’s model : Registers
memory regions . The partitioning is based on
typical usages so that different areas are
designed to be used primarily for: Program
code accesses (e.g., CODE region) Data
accesses (e.g., SRAM region) Peripherals (e.g.,
Peripheral region) Processor’s internal control
and debug components (e.g., Private Peripheral
Bus) The architecture also allows high
flexibility to allow memory regions to be used for
other purposes. For example, programs can be
executed from the CODE as well as the SRAM
region, and a microcontroller can also integrate
SRAM blocks in CODE region.
The register bank in the Cortex-M4 processors (e.g., using data transfer/processing
has 16 registers. Thirteen of them Parikrama instructions) causes a branch operation. Since
COE are purpose general 32-bit registers, and the instructions must be aligned to half-word or
the other three have special uses. word addresses, the Least Significant Bit (LSB) of
R0 - R12 Registers R0 to R12 are general the PC is zero.
purpose registers. The first eight (R0 - R7) are Programmer’s model : Special registers
also called low registers. Due to the limited Program status registers The Program Status
available space in the instruction set, many 16- Register is composed of three status registers:
bit instructions can only access the low registers. Application PSR (APSR) Execution PSR (EPSR)
The high registers (R8 - R12) can be used with Interrupt PSR (IPSR)
32-bit instructions, and a few with 16-bit
instructions, like MOV (move). The initial values
of R0 to R12 are undefined.
R13, stack pointer (SP) It is used for
accessing the stack memory via PUSH and POP
operations. Physically there are two different
Stack Pointers: the Main Stack Pointer (MSP, or
SP_main in some ARM documentation) is the
default Stack Pointer. It is selected after reset, or
when the processor is in Handler Mode. The
other Stack Pointer is called the Process Stack
Pointer (PSP, or SP_process in some ARM
documentation). The PSP can only be used in
Thread Mode. The selection of Stack Pointer is
determined by a special register called
Q.6 What are different exceptions and nested
CONTROL.
Vector interrupt Controller in STM32F4xx
R14, link register (LR) R14 is also called the controller?
Link Register (LR). This is used for holding the
return address when calling a function or
subroutine. At the end of the function or
subroutine, the program control can return to
the calling program and resume by loading the
value of LR into the Program Counter (PC).
When a function or subroutine call is made, the
value of LR is updated automatically. If a
function needs to call another function or
subroutine, it needs to save the value of LR in the Exceptions—
stack first. Otherwise, the current value in LR In Cortex-M processors, there are a number of
will be lost when the function call is made. exception sources: Exceptions are processed
R15, program counter (PC) It is readable and by the NVIC. The NVIC can handle a number of
writeable: a read returns the current instruction Interrupt Requests (IRQs) and a Non-Maskable
address plus 4 (this is due to the pipeline nature Interrupt (NMI) request. Usually IRQs are
of the design, and compatibility requirement generated by on-chip peripherals or from
with theARM7TDMI processor). Writing to PC external interrupt inputs though I/O ports. The
NMI could be used by a watchdog timer or Vectored exception/interrupt entry Interrupt
brownout detector (a voltage monitoring unit masking.
that warns the processor when the supply Q. 7 Reset and resetsequence
voltage drops below a certain level). Inside the In typical Cortex-M microcontrollers, there can
processor there is also a timer called SysTick, be three types of reset: Power on reset - reset
which can generate a periodic timer interrupt everything in the microcontroller. This includes
request, which can be used by embedded OSs for the processor and its debug support component
timekeeping, or for simple timing control in and peripherals. System reset - reset just the
applications that don’t require an OS. processor and peripherals, but not the debug
The processor itself is also a source of support component of the processor.
exception events. These could be fault events Processor reset - reset the processor only. The
that indicate system error conditions, or duration of Power on reset and System reset
exceptions generated by software to support depends on the microcontroller design. In
embedded OS operations. As opposed to some cases the reset lasts a number of milli
classic ARM processors such as the ARM7TDMI, seconds as the reset controller needs to wait for
there is no FIQ (Fast Interrupt) in the Cortex-M a clock source such as a crystal oscillator to
processor. However, the interrupt latency of stabilize.
Corex-M4 is very low, only 12 clock cycles, so this
does not cause problems.
Vector interrupt Controller—
Nested exception/interrupt support Each
exception has a priority level. Some exceptions,
such as interrupts, have programmable priority
levels and some others (e.g., NMI) have a fixed
priority level. When an exception occurs, the
The setup of the MSP is necessary because
NVIC will compare the priority level of this
some exceptions such as the NMI or HardFault
exception to the current level. If the new
handler could potentially occur shortly after the
exception has a higher priority, the current
reset, and the stack memory and hence the MSP
running task will be suspended. Some of the
will then be needed to push some of the
registers will be stored on the stack memory, and
processor status to the stack before exception
the processor will start executing the exception
handling.
handler of the new exception. This process is
Q.8 What are advantages & disadvantages of
called “preemption.” When the higher priority
ARM Cortex over ARM Processor?
exception handler is complete, it is terminated
Advantages:
with an exception return operation and the
Higher performance: ARM Cortex processors
processor automatically restores the registers
typically have a higher clock speed than ARM
from stack and resumes the task that was
processors, which can lead to improved
running previously. This mechanism allows
performance in applications that are CPU-
nesting of exception services without any
intensive.
software overhead.
More features: ARM Cortex processors typically
The NVIC has the following features:
have more features than ARM processors, such
Flexible exception and interrupt management as a floating-point unit (FPU), which can be used
Nested exception/interrupt support for high-precision mathematical operations.
Lower power consumption: ARM Cortex redundancy check) calculation unit The CRC
processors typically have lower power (cyclic redundancy check) calculation unit is used
consumption than ARM processors, which can to get a CRC code from a 32-bit data word and a
extend the battery life of devices that use them. fixed generator polynomial.
Smaller size: ARM Cortex processors typically Embedded SRAM
have smaller size and silicon footprint than ARM All STM32F40xxx products embed: Up to 192
processors, which can make them suitable for Kbytes of system SRAM including 64 Kbytes of
use in devices with limited space, such as CCM (core coupled memory) data RAM RAM
wearables and Internet of Things (IoT) devices memory is accessed (read/write) at CPU clock
Disadvantages: speed with 0 wait states.
More expensive: ARM Cortex processors Multi-AHB bus matrix
typically cost more than ARM processors. The 32-bit multi-AHB bus matrix interconnects
Less compatibility: ARM Cortex processors may all the masters (CPU, DMAs, Ethernet, USB HS)
not be compatible with some older ARM and the slaves (Flash memory, RAM, FSMC, AHB
processors or software. and APB peripherals) and ensures a seamless
Higher learning curve: ARM Cortex processors and efficient operation even when several high-
may have a higher learning curve than ARM speed peripherals work simultaneously
processors, due to their more complex features. DMAcontroller (DMA)
Q.9 With the block diagram explain the The devices feature two general-purpose dual-
STM32F4xx Architecture. port DMAs (DMA1 and DMA2) with 8 streams
Adaptivereal each. They are able to manage memory-to-
timememoryaccelerator(ARTAccelerator™) memory, peripheral-to-memory and memory-
The ART Accelerator™ is a memory accelerator to-peripheral transfers. They feature dedicated
which is optimized for STM32 industry-standard FIFOs for APB/AHB peripherals, support burst
ARM® Cortex®-M4 with FPU processors. It transfer and are designed to provide the
balances the inherent performance advantage of maximum peripheral bandwidth (AHB/APB)
the ARM Cortex-M4 with FPU over Flash memory DMAcontroller (DMA)
technologies, which normally requires the Each stream is connected to dedicated hardware
processor to wait for the Flash memory at higher DMA requests, with support for software trigger
frequencies. on each stream. Configuration is made by
Memory protection unit software and transfer sizes between source and
The memory protection unit (MPU) is used to destination are independent.
manage the CPU accesses to memory to prevent Clocks and startup
one task to accidentally corrupt the memory or On reset the 16 MHz internal RC oscillator is
resources used by any other active task. This selected as the default CPU clock. The 16 MHz
memory area is organized into up to 8 protected internal RC oscillator is factorytrimmed to offer
areas that can in turn be divided up into 8 1% accuracy over the full temperature range.
subareas. The protection area sizes are between The application can then select as system clock
32 bytes and the whole 4 gigabytes of either the RC oscillator or an external 4-26 MHz
addressable memory clock source. Boot modes
Embedded Flash memory At startup, boot pins are used to select one out
The STM32F40xxx devices embed a Flash of three boot options: Boot from user Flash
memory of 512 Kbytes or 1 Mbytes available for Boot from system memory Boot from
storing programs and data. CRC (cyclic embedded SRAM
Q.10 ARM Processor Families data, while the RAM is used to store temporary
Cortex-A series (Application) – High data and variables.
performance processors capable of full I/O ports: The STM32F4xx has 16 general-
Operating System (OS) support; – Applications purpose I/O ports, which can be used to control
include smartphones, digital TV, smart books, a variety of external devices. The I/O ports can
home gateways etc. be configured to operate in a variety of modes,
Cortex-R series (Real-time) – High performance including digital input, digital output, analog
for real-time applications; – High reliability – input, and analog output.
Applications include automotive braking system, Serial communication peripherals: The
powertrains etc. STM32F4xx has a variety of serial
Cortex-M series (Microcontroller) – Cost- communication peripherals, including:
sensitive solutions for deterministic UARTs: The STM32F4xx has up to 10 UARTs,
microcontroller applications; – Applications which can be used for serial communication with
include microcontrollers, mixed signal devices, other devices. UARTs are a simple and efficient
smart sensors, automotive body electronics and way to transmit and receive data between
airbags; devices.
Q.11 features of ARM cortex Series SPI: The STM32F4xx has up to 3 SPI peripherals,
1) Advanced three stage pipeline. which can be used for high-speed serial
2) harvard Architecture communication with external devices. SPI is
3)Two operating modes (thread & handler) often used for communication with devices such
4) single cycle multiply & hardware divide as memory cards, sensors, and displays.
5) Thumb-2 instruction set. I2C: The STM32F4xx has up to 2 I2C peripherals,
6) Nested vectored interrup controller (NVIC) which can be used for low-speed serial
7) integrated debug & trace communication with external devices. I2C is
8) MPU (Memory protection Unit) often used for communication with devices such
9) working smarter to sleep longer. as sensors and displays.
10) power management through NVIC USB: The STM32F4xx has a USB 2.0 Full Speed
Q.12 Explain different peripherals in controller, which can be used to connect the
STM32F4XX. device to a host computer or other USB device.
CPU: The STM32F4xx is powered by a 32-bit ARM The USB controller can be used to transfer data,
Cortex-M4 CPU, which can run at up to 168 MHz. connect to the internet, and control external
The Cortex-M4 CPU is a high-performance devices.
processor that can be used for a variety of Q.13 Explain different clocks of STM32F4XX
applications, including real-time control, The STM32 has an internal clock circuit that has
embedded vision, and audio processing. the objective of generating and distributing the
FPU: The STM32F4xx also has a floating-point clock signal for the CPU and all the peripherals
unit (FPU), which can be used for high-precision The clock circuit is programmable, meaning that
mathematical operations. The FPU is especially it can use different clock source and may apply
useful for applications that require complex division and multiplication factors
calculations, such as digital signal processing Each family of STM32 MCUs has a different clock
(DSP) and image processing. circuit with different features: here we consider
Memory: The STM32F4xx has up to 2 MB of the clock of STM32F4
Flash memory and 1 MB of RAM. The Flash The STM32F4 manages two different clock
memory is used to store the program code and signals
HS: High Speed Cortex-M4 processors have: Three-stage
LS: Low Speed pipeline design Harvard bus architecture with
Each clock signal is generated by clock source unified memory space: instructions and data use
that can be: the same address space 32-bit addressing,
Internal: Generated by a Resistor-Capacitor net supporting 4GB of memory space On-chip bus
External: Generated by a quartz crystal interfaces based on ARM AMBA (Advanced
resonator Microcontroller Bus Architecture) Technology,
Therefore, we have the following signal names: which allow pipelined bus operations for higher
HSI: High Speed Internal throughput An interrupt controller called NVIC
HSE: High Speed External supporting up to 240 interrupt requests and
LSI: Low Speed Internal from 8 to 256 interrupt priority levels .
LSE: Low Speed External Support for various features for OS (Operating
Low Speed Clock (LSI and LSE) must run at a fixed System) implementation such as a system tick
frequency of 32.768 KHz timer, shadowed stack pointer Sleep mode
It is used to feed the Real-Time Clock circuit HSI support and various low power features
(Internal High Speed) runs at a fixed frequency of Support for an optional MPU (Memory
16 MHz HSE (External High Speed) can run at a Protection Unit) to provide memory protection
frequency that goes from 4 MHz to 26 MHz. features like programmable memory, or access
The frequency of the HSI or HSE can be speed-up permission control Support for bit-data
by using a circuit called PLL = Phase Locked Loop accesses in two specific memory regions using a
It is a standard circuit that can act as a frequency feature called Bit Band The option of being
multiplier/divisor used in single processor or multi-processor
List of Clock: designs.
1. CPU Clock The ISA used in Cortex-M4 processors provides a
2. HCLK to AHB BUS, CORE, MEMORY, DMA
wide range of instructions: General data
3. FCLK Cortex free running clock
processing, including hardware divide
4. APB peripheral clock
instructions Memory access instructions
5. APB Timer clock
supporting 8-bit, 16-bit, 32-bit, and 64-bit data,
6. RTC
as well as instructions for transferring multiple
Q.14 ARM Cortex M4Architecture
32-bit data Instructions for bit field processing
MultiplyAccumulate (MAC) and saturate
instructions Instructions for branches,
conditional branches and function calls
Instructions for system control, OS support, etc.
UNIT – 5 6. Set the 7 segment display pins to the 7
Q.1 Draw an interfacing diagram and algorithm segment display pattern for the current digit.
to interface push button and LED using 7. Repeat step 4 until the user exits the program.
STM32F4XX. END
Q.3 Draw and explain interfacing diagram of
seven segment display with STM32F4xx.