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Unit 6
Unit 6
Computer Organization
(Autonomous) • Computer Arithmetic: Addition and subtraction –
Addition and Subtraction with Signed Magnitude Data,
UNIT VI Hardware Implementation, Hardware Algorithm, Addition
and Subtraction with Signed 2’s Complement Data,
Sections - A & D Multiplication Algorithms – Hardware Implementation for
Signed Magnitude Data, Hardware Algorithm, Booth
Multiplication Algorithm, Array Multiplier, Division
Prepared by Algorithms - Hardware Implementation for Signed
Magnitude Data, Divide Overflow, Hardware Algorithm,
Anil Kumar Prathipati, Asst. Prof., Dept. of CSE. Floating – point Arithmetic operations – Basic
Considerations, Register Configuration, Addition and
Subtraction, Multiplication, Division.
INDEX
Addition & Subtraction
Signed - Magnitude
Addition and Subtraction of Signed-Magnitude data
Addition and Subtraction of Signed-2’s Compliment data
Multiplication of Signed-Magnitude and Signed-2’s Compliment
data
Array Multiplier
Division of Signed-Magnitude and Signed-2’s Compliment data
Floating point Arithmetic operations.
Cont.…
Cont.…
Hardware Architecture
Flowchart
Multiplicand in B
Multiplier in Q E A Q SC
shr(EAQ)
Final Product in AQ
Multiplication Cont.…
Signed – 2’s Complement (Booth’s)
Flowchart
Cont.… Example Division
Signed – 2’s Complement
Number1 X Number 2
Multiplicand in BR
Multiplier in QR Qn Qn+1 AC QR
SC
‘J’ is Multiplier
‘k’ is Multiplicand
J*k AND gates
(J-1)*k HA
Here, a is Multiplier
And b is Multiplicand
Flowchart
Hardware Architecture
Flowchart
2. Add the Exponents.
3. Multiply the mantissas.
4. Normalize the Product.
Division
Floating Point Numbers
Flowchart
The algorithm can be divided into four consecutive parts:
1. Check for zeros.
2. Subtract the Exponents.
3. Divide the mantissas.