ESD TR26.

0-01-23

For Behavioral IC Modeling to Perform

System Level ESD Simulations

General Description and Trends

Authors:
Working Group 26.0,
System Level Modeling
EOS/ESD Association, Inc.

EOS/ESD Association, Inc.

218 West Court Street
Rome, NY 13440

Published XXXXXXXXX
 ESD TR26.0-01-23

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 ESD TR26.0-01-23

(This foreword is not part of ESD Association Technical Report ESD TR26.0-01-23)

FOREWORD
This technical report1 (TR) on system level electrostatic discharge (ESD) modeling [3] addresses
the need for standardized models for system ESD simulation. Only direct contact discharges into
the system are considered in this document. Effects of radiated fields are not topics of this technical
report. A system in this document is an IO port, defined as a location susceptible to an ESD event
connected by a printed circuit board (PCB) trace or (ribbon) cables to another part of an electronic
circuit. The circuit can comprise several elements, notably an integrated circuit (IC), ESD protection
devices, and other components connected to this trace. These models must cover the high current
behavior of IC IO pins, supply pins, and discrete components in the time frame of ESD events
outside of an ESD controlled area, up to failure, or the current levels of the expected ESD threats.
This can be up to several tens of amperes. The goal is to enable a seamless simulation environment
where standard PCB or circuit simulation tools can be applied to system ESD simulation. The
simulations should guide PCB designers in choosing discrete components and placement on the
board. While reproducing accurate physical behavior is always welcome, accepting models with
lower accuracy and reduced dependence on physics for simpler characterization and improved
simulation time is often preferable.
A minimum set of parameters describing hard failures contain the pulse I-curve of IOs and the
respective failure levels. Protection models covering the transient waveform are included.
Categories of model accuracy and coverage are defined.
It is intended to allow an early extraction of the models in the value chain of design. For example,
models which can be created at the IO test structure level may be the only ones accessible on the
final IC design.
The proposed modeling approach is based on parameters extracted from quasi-static
measurements, for example, via transmission line pulse TLP, testing – ANSI/ESD STM5.5.1. Even
if the models can be defined as "quasi-static", the models allow simulation in the time domain,
"transient simulation". This document shows that if snapback delays can be neglected and turn-on
effects do not play a significant role, transient simulations with the quasi-static models can predict
ESD failures with good accuracy. The reason is that parasitic elements from PCB lines, packages,
and other circuit elements, often hide the very fast behavior related to the turn-on of protection
devices. This document addresses this, referring to examples and references to articles where hard
failure is the primary focus. Note that this document does not detail how to determine the parasitic
elements of the system.
Dynamic models which describe the turn-on behavior of protection devices are not considered in
this document. Such models would improve the simulation of devices with turn-on delay, which can
result in high voltages. This is under consideration by the working group, but such models are much
more complex to define and will be addressed in another technical report.
This document shares a general overview of the need for behavioral models and basic principles.
The working group does not detail how these behavioral models can be implemented in different
languages and design flows. A future TR will address quasi-static model definitions and building
models. This document on system level ESD modeling does not cover the ESD aspects of system
case design or the effects of radiated emissions during ESD events.
This technical report was originally published on XXXXXXXXX and was designated ESD TR26.0-
01-23.

1EOS/ESD Association, Inc. Technical Report (TR). A collection of technical data or test results published
as an informational reference on a specific material, system, or process.

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ESD TR26.0-01-23

At the time ESD TR26.0-01-23 was prepared, the WG 26.0 – System ESD Models Subcommittee
had the following members:
Steffen Holland, Chair
Nexperia

Michael Ammer Robert Ashton Sergej Bub

Infineon Technologies Retired Nexperia

Fabrice Caignet Lorenzo Cerati Mart Coenen

LAAS-CNRS STMicroelectronics EMCMCC

Leonardo Di Biccari Jeffrey Dunnihoo Harald Gossner

STMicroelectronics Pragma Design Intel

Fatjon (Toni) Gurga Wei Huang Peter Koeppen

Reliant ESD ESDEMC Technology ESD Unlimited LLC

Kwanghoi Koo Henning Lohmeyer Timothy Maloney

LAB126 - Amazon Company Robert Bosch GmbH CAI

Shubhankar Marathe Thomas Meuse Kathleen Muhonen

Amazon Thermo Fisher Scientific Qorvo
David Pommerenke Masanori Sawada
Martin Pilaski
Graz University of Hanwa Electronic Ind. Co.,
Nexperia Germany GmbH
Technology Ltd.
Theo Smedes Pasi Tamminen
NXP Semiconductors Danfoss

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 ESD TR26.0-01-23

TABLE OF CONTENTS

1.0 INTRODUCTION ..................................................................................................................... 1

2.0 SYSTEM LEVEL ESD ............................................................................................................. 1

3.0 BEHAVIORAL MODELS ........................................................................................................ 3

4.0 METHODOLOGY SUMMARY ................................................................................................ 6

4.1 BASIC CONCEPT ................................................................................................................... 6

4.2 IMPLEMENTATION EXAMPLE ................................................................................................... 7
4.3 I-V MEASUREMENT USING TLP TO BUILD BEHAVIORAL MODEL ............................................... 9
4.4 DEFINITION OF FAILURE CRITERIA ........................................................................................ 11

5.0 BUILD BEHAVIORAL MODEL ............................................................................................. 12

5.1 DIODES .............................................................................................................................. 12

5.2 SNAPBACK PROTECTION ..................................................................................................... 13
5.3 OTHER TRIGGERING CONDITIONS ........................................................................................ 16
5.4 FILE FORMAT FOR INFORMATION EXCHANGE ........................................................................ 17

6.0 IMPLEMENTATION INTO THE DESIGN FLOW .................................................................. 20

6.1 VALIDATION ........................................................................................................................ 21

7.0 SUMMARY ............................................................................................................................ 23

8.0 OUTLOOK ............................................................................................................................. 24

9.0 DEFINITION OF TERMS....................................................................................................... 24

10.0 REFERENCES ...................................................................................................................... 24

Annexes
Annex A (Informative):
Annex B (Informative):
Annex C (Informative):
Annex D (Informative):
Analysis of IBIS – Advantages and Disadvantages ................................ 27
Example of Exchange File for ESD Protection For SEED ...................... 31
Validation Case Study: LIN Component Modelling ................................ 33
Revision History for ESD TR26.0-01 ....................................................... 35

Tables
Table 1: Keywords Proposal to Provide Exchangeable Information to Build Quasi-Static
Model ........................................................................................................................... 18
Table 2: Examples of Shared Information to Build Protection Device Models Using Proposed
Keywords ..................................................................................................................... 19
Table 3: Summary of IBIS Advantages and Disadvantages and an Overview of Proposed
Improvements .............................................................................................................. 29

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ESD TR26.0-01-23

Figures
Figure 1: Problem of the Interactions Between the Various Elements of a System ..................... 2
Figure 2: System Level ESD Interactions ..................................................................................... 3
Figure 3: Single TLP Pulse and its Data Point on I-V Curve ........................................................ 4
Figure 4: Simple Circuit Used to Explain the Effect of a Parasitic Inductance and Capacitance;
Transient Simulation for Different Circuit Configurations .............................................. 5
Figure 5: Hierarchical Modular Modeling Principle to Address SEED Complexity ....................... 6
Figure 6: Summary of the Elements Needed to Build IC Model ................................................... 7
Figure 7: Example of a PCB Showing the Path from the External Connector to the IC ............... 8
Figure 8: Example of the Analysis of a PCB: Schematic and Block Approach of the Net
Involved in the ESD Propagation and Simulation Result .............................................. 9
Figure 9: Circuit Board Layout with a Circuit Schematic Superimposed Showing the Stress
Injection Point and the Voltage Simulation at the IC ..................................................... 9
Figure 10: Measurement and Simulation of a Sample 100 ns TLP Pulse using a Time Domain
Reflection (TDR) Configuration ................................................................................... 10
Figure 11: Piecewise-Linear Description of I-V TLP Measurements ............................................ 11
Figure 12: Time to Failure Measured, Fitted Equation, and Simulated of a Snapback Protection
Device .......................................................................................................................... 12
Figure 13: Piecewise Linear Diode Implementation into State-Machine Diagram for VHDL ....... 13
Figure 14: Snapback Device Philosophy - from Analog Measurements to Digital States
Machine ....................................................................................................................... 14
Figure 15: Modified VHDL AMS Model of the SCR I/V Characteristic from Figure 14 ................. 15
Figure 16: TVS Statement Entity for I,V, and Simulation Result for the Positive Voltage Part of
the SC17R in Figure 14 ............................................................................................... 16
Figure 17: Example of Power Clamp Device Implementation into State-Machine for VHDL-AMS
Coding ......................................................................................................................... 17
Figure 18: Reconstructed Schematic Obtained from Component Description Between Three
Pins .............................................................................................................................. 20
Figure 19: Implementation of IC Model from Component Description File into the Design Flow
to Achieve System Level Simulation ........................................................................... 21
Figure 20: Modular PCBs Which can be Combined for the Validation of Different Simulation
Set-ups ........................................................................................................................ 22
Figure 21: Parasitic Elements of the Device and Measurement Set-up ....................................... 23
Figure 22: Information Related to the Inputs and Outputs Provided by IBIS ................................ 27
Figure 23: IBIS Compared to 100 ns TLP Measurement of ESD Protection of a Digital
Component .................................................................................................................. 28
Figure 24: Schematic Overview of the IC Modeling Showing the New ESD Structures .............. 30
Figure 25: Equivalent Schematic of the LIN Component .............................................................. 33
Figure 26: Schematic of the Whole System to Reproduce TLP Injection ..................................... 34
Figure 27: Simulation Result Showing the Mismatch ................................................................... 34

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ESD Association Technical Report ESD TR26.0-01-23

ESD Association Technical Report for Behavioral IC Modeling to Perform System Level ESD
Simulations – General Description and Trends

1.0 INTRODUCTION
This document introduces a methodology for creating behavioral models of integrated circuit (IC)
inputs and outputs and electrostatic discharge (ESD) protection devices for use in the simulation
of ESD events that strike external connections of electronic systems. These models provide a
framework for ESD simulation without revealing proprietary information about the components and
provide a method for exchanging information between component manufacturers and original
equipment manufacturers (OEM).
This document focuses on hard failures and quasi-static behavioral models. Hard failures are those
caused by physical damage. In the future, these models may prove useful in the analysis of soft
failures – failures due to system upset with no permanent damage. Behavioral models
mathematically describe a component without an underlying physical understanding of the device.
Quasi-static models describe the current versus voltage characteristics after initial transients and
device turn-on but before self-heating. A future TR will address the implementation of these models
into the design flow.
System level ESD design is probably the most difficult design issue in the ESD field. As discussed
below, the ESD robustness of an electronic system (including hard and soft failures) depends on
many variables. These include properties of integrated circuits, protection devices and passive
components, printed circuit board (PCB) design and layout, design and material of the enclosure,
and software issues such as protocols, self-correction, and redundancy. ESD threats can come
from many directions, as people and objects become charged and discharged to or near the
electronic system. Data ports such as USB and HDMI are important entry points for ESD stress.
An ESD event can occur when a cable is plugged in or, more likely, when the cable conducts an
ESD event into the system. Therefore, understanding the propagation of an ESD stress from an
external connector into a system and potentially sensitive integrated circuits is an important
component in system level ESD design.
Electronic systems are tested for ESD robustness with IEC 61000-4-2 [1] or automotive products
with ISO 10605 [2]. These test standards focus on ESD to enclosures and points of human contact;
however, most OEMs also perform discharges to external connections. ESD failures for this type
of stress are a serious concern for ICs, ESD protection devices, and system manufacturers.
The Industry Council on ESD Target Levels proposed a simulation methodology to address ESD
threats to external connectors - system-efficient ESD design (SEED) [3]. In SEED, device models
for all components on the ESD stress path into the system are developed, valid in the voltage,
current, and time domain of an ESD threat. These models can then be used in a circuit simulator,
such as SPICE, to predict circuit behavior during an ESD event. The subjects in this document are
important elements of SEED.

2.0 SYSTEM LEVEL ESD

Figure 1 illustrates the complexity of system level ESD. Integrated circuits make most of the
features of modern electronic systems possible, but they are also the circuit elements most
susceptible to ESD damage. In Figure 1, an IC sits at the center of the diagram and feels the effects
of ESD events from many sources, PCB traces, passive components, transient voltage
suppressors (TVS), and even directly from an ESD tester (gun or generator) through emitted
radiation. All the elements around the IC conduct, modulate, or redirect the stress in the system. It
is impossible to simulate the entire system's response to all ESD threats, even with extremely
complicated 3D simulations. What is lacking is an understanding of how individual components act
during an ESD event.

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ESD TR26.0-01-23

Figure 1: Problem of the Interactions Between the Various Elements of a System

System designers make extensive use of simulation during design. Unfortunately, tools are limited
for ESD design because the models used to describe circuit components are only valid for voltage
and current found during normal operation. An excellent example of this is input-output buffer
information specification (IBIS) models [4]. These models describe the electrical properties of IC
inputs and outputs without providing details about the IC's internal, proprietary structure. IBIS
models are used extensively for modeling signal integrity of high-speed interfaces on PCBs. The
models, however, only apply within normal device operating voltages and a narrow range beyond.
While of limited use for ESD simulation, IBIS models provide an excellent example of how models
for ESD simulation could work. IBIS models provide the system designer with the information
necessary to perform a simulation without revealing proprietary information about the IC structure
being used. IBIS models are behavioral, meaning electrical properties are described but are not
based on the actual structure of the circuit and have no basis in the physics of the circuit elements.
Section 3.0 discusses behavioral models for ESD simulation in greater detail.

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 ESD TR26.0-01-23

Figure 2: System Level ESD Interactions

NOTE: Areas addressed by this document are inside green ovals.

The green ovals in Figure 2 illustrate the areas of system level ESD that this document addresses.
The development of models to characterize IC IOs and TVS devices does not address the full
system level ESD simulation environment. However, if these models prove useful within the limited
scope of SEED, the same models would likely be useful in a more thorough system level ESD
simulation environment, either as-is or augmented.
Another unique area of system level ESD that separates it from other areas of ESD is the possible
occurrence of soft failures. There are four possible outcomes after an ESD event to a system or a
system level ESD test.
• The system is unaffected by the stress.
• The system function is upset by the event but recovers without user intervention.
• The system function is upset by the event and needs user intervention to restore full
functionality (reset or reboot).
• There is physical damage from the event, often called hard failure.
The two middle outcomes of system upset are commonly called soft errors since functionality can
be restored, and there is no physical or hard damage. This document aims to focus on hard failures.
In the future, the models developed here could be useful for investigating soft errors if additional
information on the IC properties were included that indicate what types of stress would cause upset
but not physically damage the IC.

3.0 BEHAVIORAL MODELS

Behavioral models are often called black box models. Behavioral models for electronic components
are mathematical or circuit representations of the electrical properties, with little or no underlying
physics-based meaning to the equations or circuits. ESD behavioral models are based on quasi-
static transmission line pulse (TLP) measurements [5]. TLP is a test method in which a transmission
line, a coaxial cable, is charged and then discharged to produce a rectangular waveform to stress
a component. A typical pulse length is 100 ns. During each pulse, a measurement window is

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ESD TR26.0-01-23

defined late in the pulse, where the voltage across the device under test (DUT) and the current
through the DUT are measured, creating a current-voltage pair. A set of current-voltage pairs can
be used to create an I-V curve by stressing at progressively higher charging voltages.
An example is shown in Figure 3. Figure 3a shows the transient voltage and current of a sample
pulse on a device with snapback properties. A stable plateau is reached after an initial overshoot,
which triggers the device to turn on, and possible ringing. A measurement window is defined within
the plateau or quasi-static region, during which the voltage and current are measured. Figure 3b
shows the data point from Figure 3a on the resulting I-V curve from a series of TLP pulses. Only
the data in Figure 3b provides the input information for the model file development.

Figure 3: (a) Single TLP Pulse and (b) its Data Point on I-V Curve

While a device model may be based on quasi-static data, as described in Figure 3, that does not
mean that the model can't be used successfully in a transient simulation. In many circuit situations,
the parasitic elements of capacitance and inductance dominate the transient characteristics, not
the active devices. Capacitance and inductance can also supplement the quasi-static model to
make it more realistic and improve the model's behavior during simulation. Nevertheless, it should
be kept in mind that a quasi-static model is a simplification. That means transient effects which
occur inside the (silicon) device, like snapback delay, are not considered. The transient effects
could have an additional impact on the ESD behavior of the system. Therefore, it might be
necessary for the user to employ a more detailed dynamic model. These models are complicated,
and a good calibration of the model is more time-consuming. It depends on the application when a
quasi-static model is sufficient.
Figure 4 illustrates how a model based on quasi-static measurements becomes more realistic when
adding capacitive and inductive elements. Figure 4a shows the basic circuit, and Figure 4b shows
the results of different simulations. The voltage drop of the device is taken at the position indicated
by the red dot.
The snapback element has a resistance of 1 megohm if the voltage across it is less than or equal
to 10 volts and a resistance of 1 ohm if the voltage across it is greater than a 10-volt trigger voltage.
The circuit simulations apply a voltage step with a linear ramp over 0.3 ns to a maximum voltage
of 25 volts with a 50-ohm source impedance to the device. If the simulation is performed without
the capacitor and inductor, the voltage rises until Vtrigger is reached, at which point the voltage drops
suddenly into the snapback region. The sharp transition between trigger and snapback is not
realistic. All devices include capacitance. If a 2-pF capacitance, blue in Figure 4, is added across
the snapback device, the voltage rises more slowly as the capacitance charges, as shown in

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 ESD TR26.0-01-23

Figure 4b. When the voltage reaches Vtrigger, the voltage starts to drop back to the snapback region.
The addition of capacitance slows the voltage drop, creating a more realistic simulation. Adding
15 nH of inductance, green in Figure 4, but no capacitance changes the behavior in a different
manner. There is no change in the voltage between the circuit configurations until the snapback
device turns on. When the snapback device turns on, the voltage begins to fall but not as fast as
with no inductance as the inductor’s voltage (=L*dI/dt) resists a rapid fall in voltage. There is an
increase in the rate of voltage drop after the stress pulse voltage reaches its 25-volt plateau.
There is further change in behavior if both a 2-pF capacitor and 15-nH inductor are included in the
simulation (orange curve of Figure 4b). For voltage below the turn-on of the snapback device, the
inductor resists the initial inrush current due to the capacitor. The simulated voltage starts between
the no capacitance, no inductance simulation, and the capacitor-only simulation. When the
snapback device does turn on, the presence of the inductor results in a much slower drop in voltage
from the capacitor-only simulation as the inductor resists the sudden increase in current into the
snapback device.
A second benefit of adding capacitive and inductive circuit elements is that corners tend to be
rounded in the simulation results. The rounding of the results can often be very helpful in avoiding
convergence problems simulation programs often have with discontinuous circuit models.

Figure 4: a) Simple Circuit Used to Explain the Effect of a Parasitic Inductance and Capacitance;
b) Transient Simulation for Different Circuit Configurations

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ESD TR26.0-01-23

4.0 METHODOLOGY SUMMARY

4.1 Basic Concept
This methodology is intended to model a system composed of ICs, active components, and external
protection elements mounted on a PCB. The main principle consists in modeling each system part
separately and assembling all parts hierarchically by following the system topology. Each part of
the system can be identified as an independent block, as shown in Figure 5 (a building block system
approach). Each block is intended to consider the various interactions (shown in Figure 1).

Figure 5: Hierarchical Modular Modeling Principle to Address SEED Complexity

The PCB (including PCB lines and passive elements) and environment modeling are carried out
following the methodology described in [6] [7]. Behavioral models are applied for ICs and external
protection devices based on dedicated TLP measurements with high-current behavior.
The proposed model must maintain the intellectual property rights of several manufacturers. It
follows the IBIS model's existing methodology by providing behavioral information to perform a
simulation that does not represent physical implementations. Some of the information given by IBIS
can be kept, such as parasitic elements of the package (these parasitic parameters allow transient
simulations). Parameters that can be kept from IBIS are discussed in Annex A. Additional
information is required to perform SEED simulations, including high current behavior and the
current paths into the device created by the ESD protection.
The first step is to improve this information with parameters extracted from TLP measurements,
extending the model beyond the circuit's normal voltage and current range. The behavior of the on-
chip ESD strategy is determined from these measurements. Many articles describe the extraction
of parameters to perform SEED simulations. This document summarizes all articles found in the
literature [6-18].
The protection characteristics for the following discharge paths of an IC have to be extracted from
TLP measurements and modeled. Examples are:
• input/output to GND
• input/output to a power supply (VDD)
• VDD to GND (for each power supply)
• between grounds
• between power supplies
This list can be increased depending on the IC and configurations. The power domain network
(PDN) could be considered by adding large capacitors via an inductive-resistive path.
The acronym PDN has several related meanings and can be confusing. In different publications
and models, it has been called the “power domain network”, the “power distribution network”, and

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 ESD TR26.0-01-23

the “power delivery network”. This document considers the PDN to be all power and ground rails
and connections. The PDN can also incorporate antiparallel diodes and low-dropout regulators in
the VDD domain.
For each protection element that needs to be added to the device network, three main steps are
followed:
• Measure I-V curves using TLP characterization. Duration and rise time can depend on the ESD
protection's characteristics (see Section 4.3).
• Build a behavioral model from the I-V curve between each pair of pins.
• Implement the model for each protection device into a design tool (SPICE, VHDL-AMS,
VERILOG-A, …).
For more complex ICs, with a high number of pins, it would be interesting to develop a model for
the internal power supply network as described in the ICEM-CE (integrated circuits electromagnetic
model-conducted emission) model [38]. The PDN can describe the ESD protection concept and
represent the current paths into the IC.
Before building an equivalent ESD protection strategy, the IC model can include information from
the IBIS files, datasheet, and new parameters extracted from TLP. The protection strategy could
be based on the PDN structure. Figure 6 describes the elements that can be used to build an IC
model. Information from IBIS (in green) allows the quasi-static behavior of the device. In some
cases, a dynamic simulation can be achieved by adding parasitic elements while performing SEED.
This is because the literature shows that most of the transient effects observed are related to the
parasitic elements of the package, device, and PCB, which can be obtained from IBIS models.
Black boxes refer to the device's functional information that has nothing to do with ESD but can be
used when investigating functional robustness. The main new blocks that must be added to the
model for SEED are the non-linearities introduced by the protection circuits triggering for high
current injection (blue) and additional failure criteria (in red) to achieve failure prediction.

Figure 6: Summary of the Elements Needed to Build an IC Model [18]

4.2 Implementation Example

One example is presented in Figure 7, where an ESD stress is injected on the input port of a PCB
extracted from reference [18]. The stress is injected into the CN2 connector and follows the PCB
trace in blue to IC1 through two protection devices and one electromagnetic interference (EMI) filter.

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ESD TR26.0-01-23

The PCB footprint for the connector, protection devices, and EMI filter is shown in a dedicated
insert on the bottom left.

Figure 7: Example of a PCB Showing the Path from the External Connector to the IC
NOTE: The inset shows magnification at the connector location where three TVS devices and an EMI filter have
been placed.

The equivalent SPICE schematic (see Figure 8) of the propagation path of the ESD is built to
include varistors, TVS, EMI filter, and an equivalent SPICE model of the device. Referring to the
article, the models of the TVS and varistor have been extracted from TLP measurement. The IC
model includes multiple elements to reproduce its on-chip equivalent network. The simulation
includes two input diodes to analog power supplies, AGND and AVDD and on-chip parasitic
elements (R and L). The protection element models used for the chip (D1, D2, D3, D4, power clamp)
have been extracted from TLP measurements. The ESD strategy network is reproduced with
additional information (such as Idie) to reproduce the chip's current consumption. The observed
simulation results are reported in Figure 9 with a 5-kilovolt IEC 61000-4-2 injection. The resulting
current caused a transient voltage overshoot with a magnitude of 120 volts at the connector and a
residual voltage pulse on the processor IC input signal trace with a peak voltage of 2.78 volts.

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 ESD TR26.0-01-23

Figure 8: Example of the Analysis of a PCB: Schematic and Block Approach of the Net Involved in the
ESD Propagation and Simulation Result

Figure 9: Circuit Board Layout with a Circuit Schematic Superimposed Showing the Stress Injection
Point (1) and the Voltage Simulation at the IC (2)
NOTE: The insert on the lower left shows the stress voltage at point 1, and the insert on the lower right shows the
waveform at point 2, where actual data transfer can be seen.
NOTE: The actual data transfer can be seen in the right inset before 100 ns and after 250 ns.

This example clearly shows that it is possible to investigate how an ESD stress propagates into a
PCB using a simple equivalent SPICE schematic. All the protection devices (external and on-chip)
have been characterized using TLP (1 ns rise-time/100 ns duration), and behavioral models have
been used. These behavioral models are the key issue in investigating triggering conditions and
the reduced impact on devices. Sometimes not all component information is available. They can
be requested from the component manufacturers or need to be determined by measurement of the
component. [24], [26], [28], [30], [32], [35], and [36] give more insight into system level ESD
protection.

4.3 I-V Measurement Using TLP to Build Behavioral Model

Based on the literature, it is recommended to follow the TLP procedures of ANSI/ESD STM5.5.1.
The TLP should have a duration of around 100 ns and a rise-time of around 1 ns to cover the rise-
time and average duration of most system level stress, such as IEC 61000-4-2 stresses. A

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ESD TR26.0-01-23

correlation between a human metal model (HMM) pulse (essentially the IEC61000-4-2 pulse form
in a 50-ohm environment) and TLP is reported in [27]. A correlation of a human body model (HBM)
pulse to TLP can be found in [25]. In some cases, other TLP durations and rise times could be used
to cover specific ESD stresses. Using multiple TLP pulse widths would allow the development of
time to failure curves (Wunsch-Bell [19]).
Various components can be studied with TLP measurements, such as simple diodes, more
complex structures with a snapback, such as a silicon controlled rectifier (SCR), or structures that
clamp with dynamic conditions (triggered MOSFET – power clamps).
The I-V curves can be extracted using wafer probes or PCB structures. Still, caution must be taken
to ensure that the I-V characteristic is measured on the stable part of the current and voltage
waveforms (see Figure 10). Of course, as described previously, TLP characteristics could be
changed depending on the device. Experiments could be conducted to know if the rise-time (under
1 ns) and pulse duration (from 5 ns as used for very fast transmission line pulses (VF-TLP) or
longer than 100 ns) has a critical impact on the I-V curve, and finally, on the SEED result.
Calibration of the TLP must follow the recommendations of ANSI/ESD STM5.5.1.

Figure 10: Measurement and Simulation of a Sample 100 ns TLP Pulse using a Time Domain
Reflection (TDR) Configuration
NOTE: The quasistatic voltage is extracted at the end of the TLP pulse where the voltage is stable.

It is proposed to use the most simplified I-V characteristics of the implemented ESD protections.
As shown in Figure 11, piecewise-linear curves can provide sufficient information for the modeling
without disclosing the manufacturers’ intellectual property. For example, only two I-V points can
describe a simple diode (piecewise-linear 11a). For more accuracy, more points could be added
(piecewise-linear 11b to 11c). The main idea is that each piecewise-linear part defines a current
equation. For example, Figure 11b shows between P0 and P1 I=0 ampere. The current between
𝑉 −𝑉 𝑉 −𝑉
P1 and P2 is defined as 𝐼 = 2 1 + 𝐼1 where 𝑅1 = 2 1 , referring to the current and voltages of each
𝑅1 𝐼2 −𝐼1
point Pn (Vn, In).

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 ESD TR26.0-01-23

For snapback devices (see Figures 11d and 11e), the information about the snapback should be
given to ensure a clear break in the I-V curve. A minimum set of four I-V points is necessary to
describe snapback devices. In Figure 11d, point P3 appears at a lower current value than P2. P3
is not extracted from TLP but helps the model simulation while the current is decreasing. When the
current is increasing, the simulation follows the grey line. A strong discontinuity is created on such
components when the device triggers (between P2 and the line between P3 and P4). In SPICE, it
is not possible to define such non-linearity, but it can be done in hardware description language
(HDL). The way to build the models (diode, snapback, etc.) will be detailed in ESD TR26.0-02.

I I I

P2 P3 Pn

P2
P2
P0 P1
P0 P1 V P0 P1 V V
(a) PIECEWISE-LINEAR-2 (b) PIECEWISE-LINEAR-3 (c) PIECEWISE-LINEAR-N

I P4 I
Pn

Pi+2

Pi
P3 P2
Pi+1
P0 P1 V P0 P1 V
(d) SNAPBACK (e) SNAPBACK N

Figure 11: Piecewise-Linear Description of I-V TLP Measurements

Providing such information would allow the implementation of a behavioral description of ESD
protection between two ports into any simulator tool (SPICE, VHDL-AMS, VERILOG-AMS).
Moreover, behavioral models do not reveal any proprietary knowledge of the ESD protection
strategy and would be exchangeable between IC suppliers and OEMs. For further reading, please
see [29], [31], and [33].

4.4 Definition of Failure Criteria

In the second step, Wunsch-Bell-Dwyer curves can be developed to add the time-to-failure
dependency to the model. Even though a thermal failure is not the only way to damage the device,
it is an important failure mode. This would define a new curve that can be added to the ESD
parameters, which is useful for hard failure prediction. Such Wunsch-Bell-Dwyer curves can be
obtained using various TLP lengths [19-22].
An example of such time-to-failure curves is shown in Figure 12. Different TLP pulse lengths are
used from 100 ns to 1 µs (in red) to obtain this curve.
The equations from Wunsch, Bell, and Tasca [20] are recommended to build the behavioral failure
model. The equations can be simplified to have as few parameters as possible, resulting in the
following equation:
𝐴 𝐵
𝑃𝑓 = + +𝐶 (1)
𝑡 √𝑡

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ESD TR26.0-01-23

Pf is the power to failure, and A, B, and C are empirical parameters that correlate with the
measurements. Figure 12 shows a fit to the TLP data. The energy dissipated into a structure during
simulation is calculated by integrating the energy as in equation (2). The integrated power
dissipated in the device can be compared to the Wunsch and Bell curve to determine if a failure is
predicted.

𝐸 = − ∫ 𝑖(𝑡) ⋅ 𝑣(𝑡)𝑑𝑡 (2)

Figure 12: Time to Failure Measured, Fitted Equation, and Simulated of a Snapback Protection Device

5.0 BUILD BEHAVIORAL MODEL

This section summarizes one way to build the model from the measurements depending on the
protection structure. Examples of the implementation into the VHDL-AMS language are given. The
proposed model could also be implemented into other description languages such as Verilog-AMS
or SPICE. The implementation of the structures into the different systems will be provided in ESD
TR26.0-02.

5.1 Diodes
A diode in forward bias is a good example to demonstrate the philosophy.
Only two parameters are needed, the triggering voltage, Vth, and the on-state resistance, Ron (see
Figure 13a). These parameters could be reported in a text file within a piecewise format with two
coordinate pairs (Vx, Ix). The first point (Vth,0) defines the threshold voltage, and a second one
(V1, I1) defines the on-resistance:
(𝑉1 − 𝑉𝑡ℎ)
𝑅𝑜𝑛 =
𝐼1
This defines a very simple two-state machine diagram (see Figure 13b). When the voltage across
the diode is below Vth, the diode is off (state = 0), and no current flows into the protection. Otherwise,
the diode is in state 1 with the I-V properties defined by the two I-V points or by the equation:
V = R 𝑜𝑛 ⋅ I + Vth
A Zener or avalanche diode in reverse bias could be described similarly.

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 ESD TR26.0-01-23

a) b)
From I-V characteristic to state machine Algorithm of diode model
diagram

Figure 13: Piecewise-Linear Diode Implementation into State-Machine Diagram for VHDL

5.2 Snapback Protection

The same philosophy is used for snapback protection, where an SCR is used as an example.
Snapback requires a minimum of four states if considering both forward and reverse bias
characteristics. The properties are extracted from the measured I-V curves shown in Figure 14(left)
and follow the state diagram shown in Figure 14(right). Six voltage and current pairs are defined
as parameters. This number of points to define the structure can be extended if needed. These (Vx,
Ix) pairs define the inflection points of the SCR and the equivalent equations for the states 0, 1, 2,
and 3. Previous works have used the model to simulate ESD stress injection (TLP and IEC 61000-
4-2). Such a model can suffer from convergence issues. The most critical point of such a behavioral
model is the strong discontinuities in the piecewise-linear description of the protections from (V4,
I4) to (V5, I5). It generally causes simulators to fail to converge. This is observed even in SPICE
simulators or other description languages that can use VHDL-AMS or Verilog-A. This could be
solved by adding its equivalent junction capacitances in parallel to the SCR. The added capacitance
prevents the internal voltage of the SCR from a sudden drop in voltage. Solving cases of non-
convergence is beyond this document and will be discussed in another document.

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ESD TR26.0-01-23

Figure 14: Snapback Device Philosophy - from Analog Measurements to Digital States Machine

The VHDL code is shown in Figure 15. The entity declaration at the top of Figure 15 defines the six
(I, V) points. The architecture part of the code at the bottom of Figure 15 describes how to go from
one state to another.

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 ESD TR26.0-01-23

Figure 15: Modified VHDL AMS Model of the SCR I/V Characteristic from Figure 14

The results of the simulation for positive voltage are shown in Figure 16.

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ESD TR26.0-01-23

Figure 16: TVS Statement Entity for I,V, and Simulation Result for the Positive Voltage Part of the
SCR in Figure 14

5.3 Other Triggering Conditions

Many power clamps (PC) are based on MOS transistors with complex triggering conditions. If a
PCB with capacitors is present, the power clamps may be disabled if Vdd is applied. The PCs are
built around a strong MOSFET driven by an RC-triggered structure (see Figure 17). The proposed
behavioral model is a four-state machine. When the device triggers, it could have been represented
as a diode (in forward biased direction). In this case, the triggering condition is set on a dV/dt
without knowing the effective RC structure. A dedicated VHDL command "V'dot" is used to change
the state only if the dV/dt is higher than a defined value. In the example, the command
"V'dot>0.1x109" triggers the structure by monitoring the dV/dt in the simulation. If V’dot is higher
than 0.1 x109 volt/ns, the state changes to MOS conduction (yellow state and later green state once
the voltage across the structure is higher than Vth). Please note that the yellow current is rather
small. If the triggering condition is not reached, the structure is not triggered. The other states are
when the stress rise-time cannot trigger the protection and MOS condition. A similar structure has
been implemented into the study of paper [7], where the susceptibility of failure is compared with
measurements in a direct pin injection (DPI) configuration [34]. The PC sinks part of the current
during the stress, increasing the failure level that could be predicted using only IBIS information.

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 ESD TR26.0-01-23

Figure 17: Example of Power Clamp Device Implementation into State-Machine for VHDL-AMS
Coding

5.4 File Format for Information Exchange

Developing a text document to share the information needed to build models for all devices needed
in a simulation should be possible. Following the philosophy of IBIS, this information only provides
the behavior of the devices in the ESD time, current, and voltage domain. It does not provide any
physical description of the device. Some components, such as ICs, may require multiple models
with different models for different types of pins. Keywords should be used to identify the component,
the protection structures (with associated models), I-V curves, and failure behavior to describe the
complete component in a simple text file. The keywords in Table 1 could provide the system
designer with an understandable description.

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ESD TR26.0-01-23

Table 1. Keywords Proposal to Provide Exchangeable Information to Build Quasi-Static

Model
Keyword: Information
Component Name of the component – a component defines any device from two to
multiple pins. It could include only one protection device or many. The
protection devices (models) should be connected to nets that allow the
reconstruction of the ESD strategy of the component. For each protection
device of the component, a model should be provided.
Model xxxxx Name of a protection device model (xxxxx).
From A to B Allocates the current path through the two pins: From A to B defines a
positive current path. (The model could also define a negative current
path). This keyword should follow the model's name line.
Snapback Give information on the presence of a snapback or not. The response
could be Y (Yes) or N (No).
Triggering condition Give information on the way the device triggers. The response could be
voltage, current, dV/dt, etc. This could be important for developing a
model. A value could be added if necessary.
dV/dt value: Value of the triggering condition. This could describe power clamp
structures. The units must be specified.
Number of points: The number of the points provided to describe the quasi-static I-V curve.
I-V table Start the I-V table and provide the used units. If the text file provides more
than one table, a name could be added to the table.
Units Units used in the following table are in the same order, separated by
tabs.
End I-V table Ends the table description. If more than one table, add the name of the
table it ended.
TLP Give details about the TLP generator and process to get the I-V
characteristic. Additional keywords must be added to describe the TLP
measurements, such as "rise-time,"; "duration"; "Measurement
Windows", and system impedance. This only provides additional
information concerning the way the table has been obtained.
Failure level Provide a constant failure level for dedicated protection. It is important to
provide the value and the unit.
Time To Failure table It starts a time to failure table. Units must be provided.
End time to failure Ends the time to failure table.
table
End Model xxxxx Closes the model description (of Model xxxxx).
End Component Ends the component description.
-- Comments. All the text after this is neglected until the end of the line.

The proposed keywords give a framework for what the text file contains. It is not necessary to use
all the keywords. For example, a time to failure table is unnecessary if a failure level is provided.
Following the same philosophy, the model could provide only one I-V table or multiple depending
on the TLP tester conditions. The additional keyword "TLP" explains how the I-V curves have been
obtained. This information must follow the keyword "I-V table" it references.

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 ESD TR26.0-01-23

Table 2 reports examples of the three main protection device structures and the basic information
needed to build the models. The proposed examples only provide different topologies and
behaviors to build the models.
NOTE: The examples in Table 2 are not related to any real component.
The objective is to show how the device can be described. To do so, the number of points to
describe each protection device is limited to the minimum. This number is not limited and can be
extended as needed. It could also be the full TLP measurement.

Table 2. Examples of Shared Information to Build Protection Device Models Using Proposed
Keywords
Diode device Snapback device Power Clamp device

Model: Simple_Diode Model: Simple_snapback Model: Simple_PC

From In to Vdd From In to Gnd From Vdd to Gnd
Snapback: N Snapback: Y Triggering condition: dV/dt
Triggering condition: voltage Triggering condition: voltage dV/dt value: 10 V/ns
I-V table I-V table I-V table
TLP rise-time: 1 ns duration: : Units: Voltage (V) current : Units: Voltage (V) current
100 ns average (A) (A)
Window: 80-90 ns 0.0 0.0 0.0 0.0
: Units: Voltage (V) current 7.2 0.0 12.0 0.0
(A) 7.5. 0.5 15.5. 8.3
0.0 0.0 3.4. 0.3 End I-V table
1.0 0.0 7.0. 12.4 Failure level: 25 V
1.4. 0.5 End I-V table End model Basic_PC_VDD
3.5. 8.3 TimeToFailure table
End I-V table Unit: Time (ns) current (A)
Failure level: 10 A 50.0 17.0
End model Simple_Diode 100.0 13.0
300.0 8.6
500.0. 6.7
End TimeToFailure table
End model Simple_snapback
NOTE: These three models can be part of a single component description. It could be possible to construct
the ESD protection concept between the pins (here IN, VDD, GND) into the equivalent schematic reported in
Figure 18. The complete file of the ESD exchange file is provided in Annex B.

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ESD TR26.0-01-23

P3

VDD
P2

P0 P1 V I
dV/dt > 10V/n s
Sim ple_Diode
P2

IN
I P4
P0 P1 V

Sim ple_PC

P3 P2

P0 P1 V GND
Sim ple_snapbac k

Figure 18: Reconstructed Schematic Obtained from Component Description Between Three Pins

Using such an ESD exchange file would allow a designer to build an equivalent model of the
onboard component to perform a SEED simulation. An "XML" format can also be provided as
defined by IEC 62433-6 [23].

6.0 IMPLEMENTATION INTO THE DESIGN FLOW

As mentioned at the beginning of this document, all system parts must be individually considered
to perform a SEED simulation. The proposed implementation facilitates building a behavioral model
from a generic file description. The file contains quasi-static I-V curves and failure criteria if the
failure level is investigated.
For an IC, the proposed methodology provides a black box model approach. The text file provides
the necessary data to build models of individual protection elements plus the connections between
the protection elements and the PDN (described in IEC 62433-2 – ICEM-CE [38]). Coupled with
the parasitic data found in IBIS files, this provides a full description of the IC’s protection strategy.
A similar black box approach may be followed for other elements on the circuit board, such as TVS
devices or off the shelf models provided by the device manufacturer or other sources.
Figure 19 shows the basic principle of the flow to achieve a system level ESD simulation. It is
clearly shown that the circuits are only part of the full system simulation. A SEED simulation needs
models for each part of the system, which are not described in this document.

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 ESD TR26.0-01-23

Figure 19: Implementation of IC Model from Component Description File into the Design Flow to
Achieve System Level Simulation

The implementation of a simulator is not an easy task. One aspect that can make this easier is the
counterintuitive careful addition of parasitics. As discussed earlier, adding parasitic capacitances
and inductance can eliminate some convergence issues.
Adding the parasitic elements of the system (PCB traces, ground return, etc.) also adds accuracy
to the simulation. All the parasitic elements of the devices and system elements impact the
propagation path and, therefore, the final stress at the protection device(s). The article [35] clearly
details how the system's elements impact the transient behavior. The validation is performed using
a TLP generator, IEC 61000-4-2, and ISO 7637. In all these cases, simulation results are obtained.
In such conditions, a model based on quasi-static measurement can perform simulations in the
time domain. Referenced articles clearly show that good dynamic behavior can be obtained by
adding all the system’s parasitic elements, which often have a higher impact than the dynamic
behavior of the protection itself. An example is provided below. Dynamic behavior of the protection
devices could have a critical impact on high-speed systems or in the case where two protection
elements are parallel with no parasitic elements in between. Within this consideration, a dynamic
model should be used. This will be discussed in a future document.
It is expected that as designers begin to use these tools, various methods are developed to
surmount the inevitable challenges. A future technical report will present a way to implement quasi-
static behavioral models into the different design flows.

6.1 Validation
One way to validate the model is to simulate a TLP measurement using the models and compare
it to the TLP measurements of the devices in question.
All the elements of the set-up have to be introduced into the simulation:

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ESD TR26.0-01-23

• Models of the circuit elements under test

• Model of the TLP generator
• Model of transmission lines used with its length
• Parasitic elements of the PCB and package
Figure 20 shows a modular PCB approach that is developed for validation. Each module is
designed for mounting a specific component or components. Components can then be
characterized individually or connected together to see how well different components work
together. There are also modules for current and voltage measurement.

Figure 20: Modular PCBs Which can be Combined for the Validation of Different Simulation Set-ups
NOTE: Each PCB component can be characterized individually.

A transient simulation of the TLP measurement can then be compared to the measured data. The
goal is to validate the stable I and V points obtained in Figure 21 (current and voltage, respectively).
As observed, by introducing all the parasitic external elements of the system (here, a TLP injection
on a component mounted on PCB), the simulation can reproduce the transient waveform measured
on the transmission line pulse time domain reflection (TLP-TDR) system with good accuracy.

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 ESD TR26.0-01-23

Figure 21: Parasitic Elements of the Device and Measurement Set-up

NOTE: Repetition of Figure 10.

A TLP simulation is the first point to validate the model and ensure that the behavioral model is
simulated correctly. It also validates the methodology of system level simulation.
The next step would be the validation of the model into a prototype following the step-by-step
approach:
• TLP injection (unpowered) (no external elements)
• TLP injection (unpowered) + external elements at the pin under test on the board
• TLP injection (powered) (no external elements)
• TLP injection (powered) + external elements at the pin under test on the board
• IEC 61000-4-2 injection

7.0 SUMMARY
This technical report describes an approach for the behavioral modeling of a system during an ESD
event. In the electrical system, each component influences the ESD robustness. Unfortunately, the
behavior of the individual component and its interaction is unknown. Existing models are not
useable for simulations intending to predict the ESD robustness of the whole system.
There are two kinds of failures: physical (hard) component failures and soft failures. The latter
disturbs the entire system's operation, but it can be reset to the normal operation mode. In this
document, only hard fails are considered.
The behavioral description of the devices in this report uses quasi-static information, such as the
voltage and current, when the device has reached a stable state before self-heating becomes an
issue. This is in apparent contradiction to the requirement that an ESD event is simulated with a
transient simulation. However, devices often show a transient overvoltage at the beginning of the
pulse. Parasitic elements such as inductance and/or capacitance can be added to reproduce this
transient behavior.
The entire system can be reproduced by adding models for each component in a hierarchical way.

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ESD TR26.0-01-23

Device models can be described by a piecewise-linear I-V curve that considers possible non-linear
effects. A failure criterion, for instance, according to the Wunsch-Bell-Dwyer relation, can be added.
Snapback and non-snapback devices can be described similarly by using different states. The
device model switches digitally from one state to the other depending on the input conditions of the
overall simulation. VHDL-AMS or Verilog-A can be used to define such a model. For instance, dV/dt
triggering can be modeled with such an approach for more complex switching conditions.
However, the modeling is not limited to these languages. An exchange file format is proposed to
facilitate the exchange of information about the device behavior in an implementation agnostic way.
Finally, the developed models need to be validated. A method to do this is by comparing TLP
measurements with a simulation of the TLP measurements.

8.0 OUTLOOK
The current document describes how behavioral system level ESD simulations can be done and
focuses on the general approach.
A future document will describe how the device models can be created in more detail. This
document describes how quasi-static device information can be used to set up models for ESD
simulations. Parasitic inductances and capacitances currently allow the simulation of aspects of
dynamic behavior. It is known that semiconductors and other materials do not instantaneously
switch from the off-state to the fully on-state during an ESD event. This requires inherent dynamic
ESD models, which can describe the effects inside the semiconductor.

9.0 DEFINITION OF TERMS

electrical behavioral model. A model which reproduces the behavior of the device without
knowing its details. In the case of an ESD model, it reproduces the behavior of a device during an
ESD event without any physical information about the chip. The small signal behavior of the device
is not modeled. Such a model is also called a "black-box" model.
dynamic model. A model including time-dependent behavior of the protection devices such as
turn-on information.
hard failure. Failure of the system, for which physical repair is required. Most of the time, it refers
to the destruction of the system functionality.
IBIS model. input-output (I/O) buffer information specification – The standard used to perform
signal integrity simulations.
NOTE: It can help to develop SEED simulation models because it contains information such as
parasitic elements. The advantages and constraints of IBIS regarding SEED are presented in
Annex A.
quasi-static model. Model extracted using quasi-static measurement system (generally TLP
following the ESDA’s standard test method - ANSI/ESD STM5.5.1).
SEED. System-Efficient ESD Design – simulation methodology presented in the Industry Council
white paper 3 – system level [3] for predicting ESD behavior for systems.
soft failure. Failure of the system involving a temporary loss of functionality. The system function
is upset by the event but recovers without user intervention. In a more severe case, the system
function is upset by the event and needs user intervention to restore full functionality (reset or
reboot).
transient simulation. Simulation performed in time domain. The component models can be either
a quasi-static model, a dynamic model, or a combination of the two.

10.0 REFERENCES
[1] IEC 61000-4-2, “Electromagnetic compatibility (EMC), Part 4-2 : Testing and measurement
techniques, Electrostatic discharge immunity test".

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[2] ISO 10605, "Road vehicles - Test methods for electrical disturbances from electrostatic
discharge".
[3] Industry Council on ESD Target Levels, White Paper 3, "System Level ESD, Part I: Common
Misconceptions and Recommended Basic Approaches".
[4] IBIS: https://ibis.org/specs/
[5] ANSI/ESD STM5.5.1, ESD Association Standard, "Test Method for Electrostatic Discharge
(ESD) Sensitivity Testing - Transmission Line Pulse (TLP) - Component Level".
[6] N. Monnereau, F. Caignet, and D. Tremouilles, "Building-up of system level ESD modeling:
Impact of a decoupling capacitance on ESD propagation," EOS/ESD Symp Proc; 2010.
[7] Tianqi Li, J. Maeshima, H. Shumiya, D. Pommerenke, T. Yamada, and K. Araki, "An application
of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection
circuit of a cell phone," Electromagnetic Compatibility (EMC), 2012 IEEE International
Symposium.
[8] N. Monnereau, F. Caignet, N. Nolhier, M. Bafleur, and D. Trémouilles, "Investigation of
Modeling System ESD Failure and Probability Using IBIS ESD Models", IEEE Trans. on Device
and Materials Reliability, Volume: 12 Issue: 4 Pages: 599-606, Dec. 2012.
[9] N. Monnereau, F. Caignet, D. Trémouilles, N. Nolhier, M. Bafleur, "A System-Level
Electrostatic Discharge Protection Modeling Methodology for Time-Domain Analysis", IEEE
Trans. on EMC Volume: 55 Issue: 13 Pages: 45-57, Feb. 2013.
[10] N. Monnereau, F. Caignet, and D. Tremouilles “Investigating the probability of susceptibility
failure within esd system level considération”, EOS/ESD Symp Proc; 2011.
[11] P. Besse, F. Lafon, N. Monnereau, and F. Caignet, "Cooperative generic IC characterisation
and simulation methods for esd system level stress," EOS/ESD Symp Proc; 2011.
[12] S. Giraldo, C. Salaméro, F. Caignet, "Impact of the Power Supply on the ESD System Level
Robustness", EOS/ESD Symp Proc; 2010, pp. 137-143.
[13] J. Laine, A. Salles, P. Besse, and A. Delmas, "Impact of snapback behavior on system level
ED performance with single and double stack of bipolar ESD structures," EOS/ESD Symp
Proc, 2012.
[14] S. Isofuku and M. Honda, "System failures due to an induced ESD within the system",
EOS/ESD Symp Proc; 2012.
[15] R. Mertens, E. Rosenbaum, H. Kunz, A. Salman, and G. Boselli, "A flexible simulation model
for system level ESD stresses with applications to ESD design and troubleshooting,"
EOS/ESD Symp Proc; 2012.
[16] S. Bertonnaud, C. Duvvury, and A. Jahanzeb, "IEC system level ESD challenges and effective
protection strategy for USB2 interface," EOS/ESD Symp Proc; 2012.
[17] A. Gallerano, A. Concannon, M. Johnson, W. Kwong, A. Fish, R. Dahl, J. Imholte, and D.
Camp, "A design strategy for 8 kV/contact 15 kV/air gap IEC 6100-4-2 robustness without on
board suppressors," EOS/ESD Symp Proc; 2012.
[18] Robert (Soung-ho) Myoung, Byong-su Seol, Norman Chang, "System-level ESD Failure
Diagnosis with Chip-Package-System Dynamic ESD Simulation", EOS/ESD Symp Proc, 2014.
[19] D, Wunsch, R. Bell. "Determination of threshold failure levels of semiconductor diodes and
transistors due to pulse voltages". IEEE Trans Nucl Sci 1968; NS-15:244–59.
[20] D.M. Tasca, "Pulse power failure modes in semiconductors", IEEE Transactions on Nuclear
Science, vol. 17, no. 6, pp. 346–372, December 1970.
[21] V. Dwyer, A. Franklin, D. Campbell “Thermal failure in semiconductor devices." Sol St El 1990;
33:553–60.
[22] G. Boselli, A. Salman, J. Brodsky, H. Kunz “The relevance of long-duration TLP stress on
system level ESD design". EOS/ESD Symp Proc; 2010. p. 31–9.
[23] IEC 62433-6, “EMC IC modelling - Part 6: Models of integrated circuits for pulse immunity
behavioural simulation - Conducted pulse immunity modelling (ICIM-CPI)".

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ESD TR26.0-01-23

[24] L. Lou, C. Duvvury, C. Torres, Morrison S. "SPICE simulation methodology for system level
ESD design". EOS/ESD Symp Proc; 2010. p. 65–73.
[25] L. Ting, C. Duvvury, O. Trevino, J. Schichl, and T. Diep "Integration of TLP analysis for ESD
troubleshooting". EOS/ESD Symp Proc; 2001. p. 445-452.
[26] G. Notermans, D. Maksimovic,G. Vermont , M. van Maasakkers , F. Pusa ,T. Smedes “On-
Chip system level protection of FM antenna pin”. EOS/ESD Symp Proc; 2010. p. 83–90.
[27] G. Notermans, S. Bychikhin, D. Pogany, D. Johnsson, D. Maksimovic, "HMM–TLP correlation
for system-efficient ESD design"; Microelectronics Reliability 52 (2012) 1012–1019.
[28] D. Johnsson, H. Gossner, "Study of system ESD co-design of a realistic mobile board."
EOS/ESD Symp Proc; 2011. p. 359–68.
[29] Monnereau, Nicolas, et al. "Behavioral-modeling methodology to predict Electrostatic-
Discharge susceptibility failures at system level: An IBIS improvement." EMC Europe 2011
York (2011): 457-463.
[30] N. Monnereau, F. Caignet, et al., "Investigating the probability of susceptibility failure within
ESD system level consideration", EOS/ESD Symposium 2011.
[31] R.P. Santoro, "Piecewise-linear modeling of I-V characteristics with SPICE," Education, IEEE
Transactions on, vol.38, no.2, pp.107,117, May 1.
[32] J. Lee, J.C. and Lim, Z. Seol, B. Li, and D. Pommerenke, "A novel method for ESD soft error
analysis on integrated circuits using a tem cell," EOS/ESD Symp Proc; 2012.
[33] R. Mertens, E. Rosenbaum, H. Kunz, A. Salman, and G. Boselli, "A flexible simulation model
for system level ESD stresses with applications to ESD design and troubleshooting,"
EOS/ESD Symp Proc; 2012.
[34] S. Bertonnaud, C. Duvvury, and A. Jahanzeb, "IEC system level ESD challenges and effective
protection strategy for USB2 interface", EOS/ESD Symp Proc; 2012.
[35] R. Bèges, F. Caignet, M. Bafleur, N. Nolhier, A. Durier, C. Marot, “Practical Transient System-
Level ESD Modeling - Environment Contribution”, EOS/ESD Symp Proc; 2014.
[36] B. Orr, P. Maheshwari, D. Pommerenke, H. Gossner, W. Stadler, “Analysis of Current Sharing
in Large and Small-Signal IC Pin Models”, EOS/ESD Symp Proc; 2014.
[37] C. Reiman, N. Thomson, Y. Xiu, R. Mertens, E. Rosenbaum, "Practical Methodology for the
Extraction of SEED Models", EOS/ESD Symp Proc; 2015.
[38] IEC 62433-2 “EMC IC modelling – Part 2: Models of integrated circuits for EMI behavioural
simulation – Conducted emissions modelling (ICEM-CE)”.
[39] IEC 623132-4: “Integrated Circuits, Measurement of Electromagnetic Immunity, 150 kHz to
1 GHz – Part 4: Direct RF Power Injection Method”.

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 ESD TR26.0-01-23

(This annex is not part of ESD Association Technical Report ESD TR26.0-01-23)

ANNEX A (INFORMATIVE) - ANALYSIS OF IBIS – ADVANTAGES AND DISADVANTAGES

IBIS is generally used for signal integrity analysis. IBIS is a text file built by following the instructions
of the IBIS group [4]. The main advantage of this standard for ESD designers is that it gives useful
information for system level ESD simulations.
Figure 22 shows the information given for an input (a) and an output (b). For each pin of the device,
IBIS gives the parasitic elements of the package (RLC), the input and output capacitances reported
as Ccomp, and some details about the pull-up and pulldown of the outputs, which are I-V curves
reporting the buffer strength, and some timing information that drives these buffers.

VDD
I V)
Files .ibs Table
Input Power
Pad Clamp
C package P
P
IC
Core
Input Capacitance ND
Ccomp CP Clamp
C comp I V)
I V) table f or ESD Table
protections Package VSS
Silicon part

(a) Behavioral Description of an Input Provided by IBIS

Files .ibs
VDD
C package I V) and V t) I V)
Table
Input Capacitance
tables Pull Power Ouput
Ccomp p Clamp P Pad
IC P

I V) table f or ESD Core

protections Pull ND
Dow n CP
Clamp C
Pullup I V) tables I V) and V t) comp
tables
I V) Package
Pulldown I V) tables VSS
Silicon part Table

Timing V t) tables

(b) Behavioral Description of an Output Provided by IBIS

Figure 22: Information Related to the Inputs and Outputs Provided by IBIS
NOTE: Found in the .ibs file.

IBIS also provides information regarding the clamps between I/O to VDD and I/O to ground called
"power clamp" and "GND clamp", respectively. It must be noted that the "power clamp" defined by
IBIS corresponds to the clamp between the input or output node to the power supply VDD. It does
not correspond to the protection between VDD and ground (VSS in the schematic of Figure 22) as
defined by ESD engineers. No other protection structures are given to describe the chip's full ESD
strategy, such as the ICs power to GND protection or capacitances between VDD and GND.

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ESD TR26.0-01-23

Moreover, the diodes provided are obtained by static measurements from –VDD to 2*VDD. An
example of comparing a simple diode given by IBIS and measured with a 100-ns TLP is shown in
Figure 23 (measurement performed on the input of a digital component 74HCT00). A significant
difference is observed between the two curves, meaning that the I-V tables provided by IBIS to
describe the on-chip diodes could not be used to perform SEED.

Figure 23: IBIS Compared to 100 ns TLP Measurement of ESD Protection of a Digital Component
NOTE: Diode between input and ground.

As a result, it appears that to perform SEED, information from IBIS could be useful, but some
elements must be changed (or new ones have to be added). Table 3 summarizes (from one point
of view) the elements of IBIS and the enhancements needed to perform a system level ESD
simulation.
Following these observations, extraction of the IC protection must be added and measured using
static and quasi-static measurement methods (for example, TLP) to accommodate high current
injection and high dI/dt. A serious disadvantage of IBIS models is the lack of snapback functionality.
Moreover, the ESD protection strategy must be reconstructed to predict any current path into the
IC depending on the external components, and IBIS does not provide this.

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 ESD TR26.0-01-23

Table 3. Summary of IBIS Advantages and Disadvantages and an Overview of Proposed

Improvements
Elements Included Impact Improvement
in IBIS
Parasitic Yes Package inductance: Keep without modification
elements of Important role:
the package
Limit high current injection (dI/dt)
Modify current paths: Directly
acts on the current propagation
into the chip (1st few ns)

Resistance and capacitance act

on the high frequency aspects
Buffer Yes Some current can flow through Gate coupling needs to be
the driver during ESD added
Safe operating region of the
drivers (SOA zone) to
determine failures should be
added
Ccomp Yes Represents the on-chip It could be kept if it represents
input/output capacitance. ESD protection. It must be
Most of the time, it is the verified.
equivalent capacitance of the
protection.
In/out Yes Allow high current injection. Prefer quasi-static
diodes Not appropriate for ESD stress: measurement to obtain I-V
curves.
Only defined between –VDD to
2*VDD Extend characterization to high
current regime during stress
Only static measurements; are
not appropriate for ESD Current characterization up to
hardware failure at
fixed TLP duration and rise
time (various values can be
proposed)
Protection No Essential to predict the current To be added
between path in the component Follow the previous
power recommendations
supplies
Protection No Essential to predict the current To be added
between path in the component Follow the previous
grounds recommendations

To summarize, the description of the ESD protection must be improved, new models must be
proposed, and the description of the protection strategy allowing all current paths to be simulated.
Figure 24 summarizes a schematic diagram of the IC model this document provides. In Figure 24,
only the principal improvements (in red) are reported.

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ESD TR26.0-01-23

Figure 24: Schematic Overview of the IC Modeling Showing the New ESD Structures

The schematic diagram shows a basic IC configuration. The elements coming from IBIS are shown
in blue. In red are the add-on elements that must be done to build the IC model. Cdec is the
decoupling capacitance between the power supply and ground.
The ESD strategy on the power supply network changes depending on the number of power
supplies. Still, a minimum set of ESD protection properties must be extracted and provided to
perform SEED.

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 ESD TR26.0-01-23

(This annex is not part of ESD Association Technical Report ESD TR26.0-01-23)

ANNEX B (INFORMATIVE) – EXAMPLE OF EXCHANGE FILE FOR ESD PROTECTION FOR

SEED
File name: Example_component.esd

-- Start one component description, including 3 protection structures

Component Example_component
-- Start first protection structure model
Model: Simple_Diode
From In to Vdd
Snapback: N – this structure is a non-snapback device
Triggering condition: voltage
I-V table – start of the I-V table
TLP risetime: 1 ns duration: 100 ns Measurement Window: 80-90 ns – TLP measurement
information
Number of points: 4
Units: Voltage (V) current (A)
0.0 0.0
12.0 0.0
13.4. 0.5
15.5. 8.3
End I-V table – start of the I-V table
Failure level: 10 A – start of the I-V table
End model Simple_Diode
-- end of the 1st protection model description

-- start of 2nd protection model description

Model: Simple_snapback
From In to Gnd
Snapback: Y – this structure has snapback behavioral
Triggering condition: voltage
I-V table
Number of points: 5
Units: Voltage (V) current (A)
0.0 0.0
7.2 0.0
7.5. 0.5
3.4. 0.3
7.0. 12.4
End I-V table
TimeToFailure table – failure is provided using a time-to-failure table
Unit: Time (ns) current (A)
50.0 17.0
100.0 13.0

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ESD TR26.0-01-23

300.0 8.6
500.0. 6.7
End TimeToFailure table
End model Simple_snapback
-- end of the 2nd protection description

-- start of 3rd protection model description

Model: Simple_PC
From Vdd to Gnd
Triggering condition: dV/dt
dV/dt value: 10 V/ns
I-V table
Number of points: 3
Units: Voltage (V) current (A)
0.0 0.0
12.0 0.0
15.5. 8.3
End I-V table
Failure level: 25 V
End model Simple_PC
-- end of the 3rd protection description

End Component Example_component

-- end of the component description

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 ESD TR26.0-01-23

(This annex is not part of ESD Association Technical Report ESD TR26.0-01-23)

ANNEX C (INFORMATIVE) - VALIDATION CASE STUDY: LIN COMPONENT MODELING

The ESDA working group investigated measurements and simulations on three different
components to validate the approach. The proposed validation is made on a LIN device.
Only three pins are exposed to the outside world for the LIN component and are part of the current
path. Consequently, only three pins are needed to build the ESD model of the component.
Figure 25 shows the device's equivalent schematic, including RLC parasitic elements from the
package and three protection elements: Vsup_LIN, LIN_GND, and Vsup_GND. Each one is
composed of a forward and a reverse block and the equivalent capacitance of the protection.

VS P
VS P

P
VS P

Package I IS
CVS
V
I

VS P
V IN
I

CVsup
IN VSup
VSup IN
V

IN
CVsup

ND VSup IN
IN IN
VSup ND
ND

ND C IN
C

Package I IS
ND IN
IN

IN ND
ND
Package I IS
ND

C
ND

ND

ND

Figure 25: Equivalent Schematic of the LIN Component

The following schematics (see Figure 26) have been used for the simulation to reproduce a TLP
injection of 800 volts, 1 ns rise-time into the LIN device. The PCB structure is reproduced in the
simulation. The measurement probes (500 ohms) are used to sense the device's voltage as close
as possible. (The 50-ohm resistance in series with the 500 ohms is to match the oscilloscope input
impedance).

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ESD TR26.0-01-23

Figure 26: Schematic of the Whole System to Reproduce TLP Injection

The measurement and simulation of the 800-volt TLP injection are reported in Figure 27. As noticed,
the quasi-static level is reproduced correctly. A focus on the first 15 ns clearly shows that the
simulation reproduces the overvoltage. 120 volts is simulated for 150 volts measured,
corresponding to an error of 20%. As noticed in this case, this error could be good enough to
estimate the component's behavior. This overvoltage could be better modeled using a dynamic
model that will be addressed in a future document.

160 160
140 140

120 Simulation 120 Simulation

Measurement Measurement
100 100

80 80

60 60

40 40

20 20

0 0
0 20 40 60 80 100 120 0 5 10 15
-20 -20
-40
-40

Zoom on the peak voltage

Figure 27: Simulation Result Showing the Mismatch

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 ESD TR26.0-01-23

(This annex is not part of EOS/ESD Association, Inc. Technical Report ESD TR26.0-01-23)

ANNEX D (INFORMATIVE) – REVISION HISTORY FOR ESD TR26.0-01

A.1 2023 Version

The document is new, with no previous versions published.

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