EXP.

NO: 2
SIMULATION OF TYPE 0 AND TYPE 1 SYSTEM
DATE:

OBJECTIVE:
To simulate type 0 and type 1 system and obtain the time response for step, ramp and parabolic

THEORY:
SYSTEM
System is defined as when a number of components or elements are arranged in a form to perform a
specified task.

CONTROL SYSTEM
When the output or response of the system can be varied by the input then the system is called
controlled system and it is classified as closed loop and open loop.

OPEN LOOP SYSTEM

In an open loop system output is controlled only by input signal it does not contain any feedback signal.

CLOSED LOOP SYSTEM

Closed loop system means the output of the system affects the input i.e. it contains feedback signal.

Type 0:
The system with no pole at origin is said to be type-0 system.

Type 1:
The system which has one pole at origin is type 1 system

STEADY STATE ERROR

Steady-state error is defined as the difference between the input (command) and the output of a system in the limit as time goes
to infinity (i.e. when the response has reached steady state). The steady-state error will depend on the type of input (step, ramp,
etc.) as well as the system type (0, I, or II).
Steady-state error can be calculated from the open- or closed-loop transfer function for unity feedback systems.
error grows unbounded as time increases toward infinity).

Type-0 System

Consider a unity feedback system

G(s)=

a) Step Response
SCILAB Code

Output

Inference:
Steady-state error is a constant.

b) Ramp Response
SCILAB code

Output

Inference:

Steady-state error is infinite (the error grows unbounded as time increases toward infinity).

c) Parabolic Response
SCILAB code

Output

Inference:

Steady-state error is infinite (the error grows unbounded as time increases toward infinity).

Type-1 System
Consider a unity feedback system

G(s)=
a) Step Response

SCILAB Code

Output

Inference:
Steady-state error is a zero

b) Ramp Response
SCILAB code

Output

Inference
Steady-state error is a constant.

c) Parabolic Response
SCILAB code

Output

Inference

Steady-state error is infinite (the error grows unbounded as time increases toward infinity).
Evaluation by Faculty member:

Criteria Maximum Marks Marks obtained

Background theory (Pre-Lab) 20

Coding 40

Procedure & Execution 20

Results & Discussion 10

Viva-Voce 10

Total Marks 100

Result:

Thus, the type 0 and type 1 system are simulated and the steady state error is determined from the time
response of the system.