IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO.

12, DECEMBER 2021 3587

A 7-Level Switched Capacitor Multilevel Inverter

With Reduced Switches and Voltage Stresses
Tapas Roy , Member, IEEE, Musie Welday Tesfay, Byamakesh Nayak,
and Chinmoy Kumar Panigrahi, Senior Member, IEEE

Abstract—This brief presents a novel switched-capacitor
multilevel inverter (SCMLI). The inverter can produce a 7-level
output voltage utilizing a dc source, nine switches, two series-
connected diodes, and three capacitors. The capacitors are
charged from the supply voltage directly by turning on appro-
priate switching states. The proposed structure realizes all the
output voltage levels without an H-bridge circuit at the load-
end. A detailed comparison study with other similar inverters
has been presented. It shows that the proposed SCMLI requires
a lower number of components and is more cost-effective as com-
pared to other inverters. The circuit build-up, capacitor charging
process, operating principle, voltage stress analysis, and capac-
itor selection procedure of the proposed inverter is presented
in detail. Finally, an extensive experimental study validates the
performance and effectiveness of the proposed inverter.
Index Terms—Boosting factor, capacitor charging, multilevel
inverter, switched capacitor, voltage balance.
I. I NTRODUCTION
OWADAYS, multilevel inverters (MLIs) are widely appli-
N cable as DC to AC converters in different industrial
applications due to their unique features such as the realiza-
tion of improved near sinusoidal output voltage waveform,
higher power handling capability, higher efficiency, lower
filter size requirements, etc [1]–[2]. One of the prominent
applications of MLIs is in the field of renewable energy
conversion systems. The MLIs act as the interfacing ele-
ment between the renewable sources and the load [3]–[4].
Generally, the output voltages of renewable sources such
as solar PV panels are low in magnitude. It is essential
to boost the output voltages of renewable sources at the
load end to achieve the desired voltages. The conventional
MLI topologies such as cascaded H-bridge (CHB), neu-
tral point clamp (NPC), and flying capacitor (FC) MLIs
use auxiliary circuits such as front-end boost convert-
ers or impedance networks to achieve this boosting abil-
ity [5]–[6]. However, these circuits make the conversion
system bulky, lower efficient, and costly. The development
of reduced size and highly efficient MLIs with inherent
boosting ability motivates the researchers to incorporate the
different voltage boosting methodologies with MLIs. One of
the most popular of them is the switched capacitor (SC)
Manuscript received April 5, 2021; accepted May 2, 2021. Date of publi-
cation May 11, 2021; date of current version November 24, 2021. This brief
was recommended by Associate Editor C.-T. Cheng. (Corresponding author:
Tapas Roy.)
The authors are with the School of Electrical Engineering, KIIT University,
Bhubaneswar 751024, India (e-mail: tapas.royfel@kiit.ac.in).
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TCSII.2021.3078903.
Digital Object Identifier 10.1109/TCSII.2021.3078903
1549-7747 
c 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
voltage boosting methodology. The MLIs based on this
methodology is popularly known as the switched capacitor
MLIs (SCMLIs) [7]–[8].
In SCMLIs, the capacitors are charged by the supply voltage
and discharged in different series and parallel combinations
with the supply voltage to synthesize the different voltage
levels at the load. Due to the absence of magnetic ele-
ments such as inductors or transformers, these inverters are
reduced size, and highly efficient [9]. A significant number
of SCMLIs have been reported in the literature in recent
years [10]–[21]. The inverter presented in [10] eliminates
the H bridge circuit for polarity generation. This feature
of [10] reduces the total standing voltage (TSV) and max-
imum switch voltage stresses. However, it requires a large
number of switches and drivers for realizing higher output
voltage levels. The inverter proposed in [11] modifies the
CHB-MLI by replacing the DC sources with SCs. A sepa-
rate DC source is used to charge all the SCs. It has lower
TSV and voltage stresses across switches. The authors of [12]
have proposed a 7-level SCMLI without an H-bridge and
using only two SCs. However, it needs many switches and
drivers. The inverters presented in [19]–[20] can realize 7-
level output voltage with lower TSV and switch voltage stress.
However, they also require a large number of switches and
drivers. The 7-level inverters developed in [10]–[12], [19]–
[20] can realize a maximum output voltage of 3 times the
supply voltage. Hence, the boosting factor of these inverters
is 3.
The 7-level SCMLIs developed in [13]–[16] use two series-
connected capacitors. The supply voltage charges these capac-
itors simultaneously to half of its voltage. With these lower
capacitor voltages, these inverters can realize output volt-
age with reduced devices. However, the lower peak output
voltages of these inverters reduce the boosting factors. The
SCMLIs reported in [17], [18] have boosting factor of 3, and
they use reduced devices for realizing 7-level output voltages.
However, they have higher TSV and PIV (peak inverse voltage
of diodes).
From this discussion, it can be observed that large com-
ponent requirements, higher voltage stress across devices,
and lower boosting factor are the prime constraints of
the recently proposed 7-level SCMLIs. This brief presents
a novel 7 level SCMLI that has the following salient
features
1. The inverter has inherent output voltage boosting and
capacitor voltage balancing abilities.
2. The boosting factor of the inverter is 3.
3. The inverter requires lower switches and drivers as
compared to similar SCMLIs.
4. The inverter does not require an H-bridge circuit for
polarity generation.

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3588 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO. 12, DECEMBER 2021
Fig. 1. Figure presents (a) proposed 7 level SCMLI; equivalent circuit for
charging state of (b) Ca , and (c) Cb .
II. P ROPOSED 7 L EVEL SCMLI
A. Circuit Description and Capacitor Charging Process
Fig. 1(a) shows the proposed 7-level SCMLI. It consists of
nine switches with anti-parallel diodes (S1 ∼ S9 ), two series-
connected diodes (DS1 and DS2 ), three capacitors (Ca , Cb and
Cc ), and a DC source (Vin ). In the circuit, S1 ∼ S5 , DS1 , and
DS2 provide the current flow paths for the capacitors in series
or parallel with Vin . A leg consisting of switches S6 and S7
is placed across the source, Vin . The mid-point of this leg is
y as shown in Fig. 1(a). Similarly, another leg consisting of
switches S8 and S9 is placed across the series combination of
Ca , Cb and Cc . The mid-point of this leg is x as shown in
Fig. 1(a). The load is connected in between x and y.
The capacitors associated with the proposed inverter can be
individually charged by Vin directly. When S2 , S3 , and S4 con-
duct, connecting Ca in parallel with Vin through DS1 as shown
in Fig. 1(b). Under this circuit configuration, Ca accumulates
energy from Vin and charges to near about Vin . Similarly, Cb is
connected in parallel with Vin whenever S1 , S2 , S4 , and S5 con-
duct as depicted in Fig. 1(c). Under this circuit configuration,
Cb accumulates energy from Vin and rises its voltage to near
about Vin . Likewise, when S1 , S3 , and S5 conduct, connect-
ing Cc in parallel with Vin through DS2 . So, Cc accumulates
energy from Vin and charges to near about Vin .
B. Operating Principle and Voltage Stress Analysis
This sub-section presents the operating principle of the
proposed SCMLI. Figs. 2(a)–2(d) depict the equivalent circuits
for +0Vin , +1Vin , +2Vin , and +3Vin voltage levels with pos-
itive load current (io > 0) and charging current paths. Table I
shows the switching states for realizing the different positive
and negative voltage levels. Where ‘1’ and ‘0’ represents ‘on’
and ‘off’ state of a switch respectively; ‘R’ and ‘F’ indicate the
reverse and forward bias of a diode respectively; and ‘C’, ‘D’
and ‘N’ indicate the charging, discharging and not-connected
states of a capacitor respectively. The generation of different
voltage levels are described as follows:
(i) ±0Vin voltage level generation: The +0Vin voltage level
appears across the load terminals whenever S6 and S8 are
turned on as depicted in Fig. 2(a). Further, during this voltage
level, Ca enters into the charging state when S2 , S3 , and S4
are turned on. Similarly, −0Vin voltage can be realized across
the load terminals whenever S7 and S9 are turned on. During
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Fig. 2. Equivalent circuits with load current and capacitor charging current
flow paths corresponding to different positive output voltage levels.
TABLE I
S WITCH , D IODE AND C APACITOR S TATES
FOR P ROPOSED 7- LEVEL SCMLI
this voltage level, Cc enters into the charging state whenever
S1 , S3 , and S5 are turned on as depicted in Table I.
(ii) ±1Vin voltage level generation: These voltage levels
can be realized by directly connecting Vin across the load.
As shown in Fig. 2(b), when S7 and S8 are turned on, DS1
becomes forward biased, and the +1Vin voltage level appears
across the load. During this voltage level, Ca remains in the
charging state as like +0Vin voltage level. Similarly, −1Vin
voltage level appears across the load whenever S6 and S9 are
turned on. During this voltage level, Cc remains in a charging
state as like −0Vin voltage level as shown in Table I.
(iii) ±2Vin voltage level generation: By connecting Vin in
series with Ca , +2Vin voltage level appears across the load.
The switches S1 , S2 , S7 , and S8 are in on state for this voltage
level as depicted in Fig. 2(c). During this voltage level, Ca
discharges its stored energy towards the load. Further, during
this voltage level, Cb enters into the charging state whenever
S4 and S5 are turned on. Also, Cc remains in the not-connected
state during this voltage. Similarly, by connecting Vin in series
with Cc , −2Vin voltage level appears across the load. The on
switches for achieving this voltage level are S4 , S5 , S6 , and S9
as shown in Table I. During this voltage level, Cc discharges
its stored energy. Further, during this voltage level, Cb enters
into the charging state whenever S1 and S2 are turned on, and
Ca remains in the not-connected state as depicted in Table I.
(iv) ±3Vin voltage level generation: By adding the voltage
across Ca and Cb with Vin , +3Vin voltage level can be realized
across the load as depicted in Fig. 2(d). For achieving this,
ROY et al.: 7-LEVEL SWITCHED CAPACITOR MULTILEVEL INVERTER WITH REDUCED SWITCHES AND VOLTAGE STRESSES 3589

With considering resistive load (R), io (t) during LDPs can

be expressed by (3). The transition time instances t2 , t3 and
t4 can be calculated by (4) considering fundamental switching
frequency modulation scheme (Half-Height) and unity mod-
ulation index [4], [21]. Where f and T are the frequency
and time period of output voltage respectively. By using
equations (1)-(4), the optimum capacitances can be evaluated
by (5).
The major power losses associated with the proposed
Fig. 3. LDP of capacitors. inverter are (a) conduction losses in switches, diodes, and
capacitors, and (b) capacitor voltage ripple losses [21]. As
the proposed inverter is switched using low frequency modu-
S1 , S3 , S5 , S7 , and S8 are needed to be turned on. Further, lation, the switching losses of the inverter are negligible. The
it observes that Cc enters into the charging state during this conduction losses can be evaluated by considering the equiv-
voltage level without turning on any extra switches as shown alent on-state resistances of switches (ron ), diodes (rd ), and
in Fig. 2(d). Similarly, −3Vin voltage can be realized at load equivalent series resistance of capacitor (re ). The instantaneous
by adding the voltage across Cb and Cc with Vin . For achiev- conduction losses (pcon,i ) for ith voltage level can be evaluated
ing this, the on switches are S2 , S3 , S4 , S6 , and S9 . During by (6).
this voltage level Ca enters into the charging state inherently
without turning on any switches as shown in Table I. pcon,i = req,i × i2o,i (6)
As the switch pair (S6 , S7 ) is connected across Vin , the
maximum voltage stress of S6 and S7 is Vin each. Similarly, where req,i is the equivalent series resistance in the load current
the switch pair (S8 , S9 ) is connected across the capacitors, so flow path, and io,i is the load current for ith voltage level. As
the maximum voltage stress for S8 and S9 is 3Vin each. It the ith voltage level occurs four times in a cycle, the average
observes that the maximum voltage stress across switches S1 , conduction losses over a cycle (Pconav,i ) can be evaluated by
S2 , S3 , S4 , and S5 is Vin each. The TSV of the inverter which (7). Where (ti+1 − ti ) is the time duration for ith voltage level.
is the summation of all the maximum voltage stresses across 4(ti+1 − ti )
switches is 13Vin . The PIVs of diodes DS1 and DS2 are 2Vin Pconav,i = pcon,i (7)
each as can be evaluated from Fig. 2(d). The summation of T
TSV and PIV of the inverter is 17Vin . The per unit (TSV+PIV) Similarly, for each voltage level, the average conduction losses
of the inverter (i.e., the ratio of the total (TSV+PIV) and the of the inverter need to be evaluated. The sum of all the average
maximum output voltage produced by the inverter) is 5.67. conduction losses provides the overall conduction losses of the
inverter.
III. S WITCHED C APACITOR S ELECTION P ROCEDURE AND The capacitor ripple losses occurs whenever the capacitor
P OWER L OSSES A NALYSIS enters into the charging state [21]. The losses depend on the
voltage difference of input voltage and the capacitor instan-
For finding the optimum capacitance values, the longest dis- taneous voltage during the charging state and the capacitance
charging period (LDP) of individual capacitors over an output value. The expression for these losses for jth capacitor is shown
cycle is needed to be evaluated [21]. During LDP, the capaci- in (8). Where (tj+1 -tj ) is the charging time duration and iCj (t)
tors discharge their stored energies towards the load. Based on
is the charging current for jth capacitor. The sum of ripple
Table I, LDPs for Ca , Cb , and Cc are shown in Fig. 3. Where
losses of all the utilized capacitors provide the overall ripple
ti (i = 1 to 14) are the transition times between two voltage
losses of the inverter.
levels. From this figure, it can be observed that LDPs for Ca 
and Cc are equal time duration. It is either (t6 −t2 ) or, (t13 −t9 ). 1  2 1 tj+1
2
Similarly, LDP for Cb is either (t5 − t3 ) or (t12 − t10 ). During prip,j = Cj  vCj = Cj iCj (t)dt . (8)
LDPs, the amount of charge transferred from Ca or Cc (i.e., 2T 2T tj
QCa or QCc ) and Cb (QCb )can be expressed by (1). Where
io (t) is the load current that is the capacitor discharging cur- IV. C OMPARISON S TUDY
rent during LDPs. With a specified capacitor voltage ripple (δ), This section presents the comparison study of the proposed
optimum capacitance for Ca or Cc and Cb can be expressed SCMLI with recently developed 7-level SCMLIs (NL = 7) as
by (2). shown in Table II.
 t4  t4
The comparison is done in respect of component require-
QCa = QCc = 2 × io (t)dt; QCb = 2 × io (t)dt (1) ment, per unit (TSV+PIV), boost factor (B) of the inverters,
t2 t3
QCa or QCc QCb and cost comparison. The cost comparison among the topolo-
Ca = Cc ≥ ; Cb ≥ (2) gies has been evaluated based on a cost function (CF) as
δ × Vin δ × Vin
 2Vin represented by (9) [21]. Where τ is the weightage factor for
io (t) = R , for t2 ≤ t < t3 (3) per unit (TSV+PIV).
3Vin
R , for

t3 ≤ t < t4
  CF Nsw + Ndr + Ndi + Nc + τ × (TSV + PIV)pu
sin−1 12 sin−1 56 = (9)
T B × NL B × NL
t2 = ; t3 = ; t4 = (4)
2×π ×f 2×π ×f 4 As per Table II, the proposed SCMLI (PT) requires a lower
2.67 1.76 number of switches than the inverters presented in [10]–[12],
Cao = Cco ≥ ; Cbo ≥ (5)
π ×f ×δ×R π ×f ×δ×R [14]–[20]. Further, the PT needs a lower number of drivers as

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3590 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 68, NO. 12, DECEMBER 2021

Fig. 4. Experimental waveforms for (a) vo (t) and io (t) for resistive load (RL = 33), (b) capacitor voltages along with io (t) for resistive load (R = 33)
(c) vo (t) and io (t) for resistive-inductive load R = 50, L = 50mH and (d) vo (t) and io (t) for inductive load L = 150mH (e) vo (t), io (t), capacitor voltages
for dynamic load.

Fig. 5. Experimental waveforms for (a) voltage stress across S6 , S7 , S8 , and S9 , (b) S4 , S5 , S3 , S1 and S2 (c) capacitor currents and input source current
along with io (t) and (d) switch currents under resistive load (R = 33) condition.

TABLE II TABLE III

C OMPARISON OF P ROPOSED 7 L EVEL SCMLI S PECIFICATIONS FOR E XPERIMENTAL S TUDY
W ITH OTHER 7 L EVEL SCMLI S

Considering the resistive load of 33, the experimental

compared to the inverters developed in [10]–[12], [17]–[20].
Furthermore, as per Table II, PT requires a lower number of
diodes and capacitors as compared to the inverters presented
in [11], [18], [20] and [15], [16], [20] respectively. In the case
of per unit (TSV+PIV) comparison, the PT sustains lower
per unit (TSV+PIV) as compared to the inverters presented
in [15], [17], [18]. In the case of boosting factor compari-
son, the PT has a higher boosting factor than the inverters
presented in [13]–[16]. However, the inverter provides the
same boosting factor as compared to the inverters presented
in [10]–[12], [17]–[20].
In CF comparison, PT provides a lower CF per boosting
factor per level than all the suggested topologies. In this com-
parison, τ is selected as 0.5 and 1. It observes that CF/(B×NL )
for the PT is 1.23 and 1.50 for τ = 0.5 and τ = 1.5 respec-
tively. These values are significantly lower than CF/(B × NL )
values for [10], [11], [13]–[16], [19]–[20]. This signifies the
cost-effectiveness of the PT with respect to other inverters.
V. E XPERIMENTAL V ERIFICATION
A laboratory prototype of the proposed inverter has been
developed. The specification for the experimental study is
shown in Table III.
waveforms of output voltage (vo (t)) and current (io (t)) are
shown in Fig. 4(a). It observes that vo (t) consists of 7 levels
and io (t) is in phase with vo (t). The capacitor voltages along
with the output current are shown in Fig. 4(b). It observes
that the steady-state voltages across Ca and Cc are 46.7V
each whereas that for Cb is 47.4V. Further, it observes that
the peak to peak ripple voltages for Ca and Cc are near about
9V whereas that for Cb is near about 8V.
With resistive-inductive (R = 50 and L = 50mH) and
inductive (L = 150mH) load conditions, vo (t) and io (t) are
shown in Figs. 4(c) and 4(d) respectively. It observes that io (t)
is near sinusoidal and lags vo (t). Further, the performance of
the proposed inverter has been evaluated for dynamic load
change conditions. For this, initially, the inverter is loaded
with 110 of resistive load, after that the load resistance
is decreased to 55 and finally again the load resistance is
increased to 110. With these sudden load change conditions,
the variations of vo (t), io (t), capacitor voltages are observed
as shown in Fig. 4(e). It observes that the capacitor voltages
remain stable within the load change time period.
With a resistive load condition of 33, the voltage stresses
across S6 and S7 are within 50V whereas those for S8 and
S9 are within 150V as shown in Fig. 5(a),. Similarly, voltage
stresses across S1 , S2 , S3 , S4 , and S5 are within 50V as shown
in Fig. 5(b). With the same load, the capacitor currents (iCa ,
iCb , iCc ) and input source current (iin ) along with io (t) are
shown in Fig. 5(c). It observes that the currents are pulsating
in nature due to the charging state of the capacitors. Similarly,
the different switch currents are presented in Fig. 5(d). All the
capacitor’s current and switch currents are within 12A.

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ROY et al.: 7-LEVEL SWITCHED CAPACITOR MULTILEVEL INVERTER WITH REDUCED SWITCHES AND VOLTAGE STRESSES
Fig. 6. FFT analysis of (a) output voltage and (b) output current.
Fig. 7. Figure presents comparison of (a) efficiencies (b) conduction
losses (c) ripple losses (d) conduction losses in different switches.
Considering the resistive load of 33, the FFT analysis
of vo (t) provides the peak magnitude of the fundamental
voltage of 142.4V with 11.99% of total harmonic distor-
tion (THD)as shown in Fig. 6(a). Similarly, the FFT analysis
of io (t) provides the peak magnitude of the fundamental cur-
rent of 4.4A with 8.68% of THD as shown in Fig. 6(b). The
experimental conduction losses, ripple losses, switching losses,
and output power of the inverter are 11.39W, 11.82W, 5.7mW,
and 313.28W respectively. The experimental efficiency of the
inverter is 93.1%.
With considering the same specifications as tabulated
in Table III, Figs. 7(a)–(c) show the comparison of
efficiency, conduction losses and ripple losses between
proposed SCMLI (PT) with the 7 level SCMLIs presented
in [10], [12], [19], [20]. Fig. 7(a) shows that the efficiency
of PT is higher than others as the power level increases.
Conduction losses of PT are minimum throughout the power
range as depicted in Fig. 7(b). As per Fig. 7(c), PT has
lower capacitor ripple losses than [10], [19] as the power level
increases. However, PT has more ripple losses than [12], [20].
Besides, considering the same specification, the variation of
conduction losses in the utilized switches of PT is shown in
Fig. 7(d). It can be observed that the conduction losses in
switches increase as the power level increases. Switch S3 has
the maximum conduction losses.
VI. C ONCLUSION
In this brief, a novel 7-level switched capacitor multilevel
inverter has been proposed for renewable energy conversion. It
has inherent capacitor voltage balancing and boosting abilities.
It does not require an H-bridge circuit for polarity generation
at the load end. The circuit build-up, operating principle, volt-
age stress analysis, and capacitor selection procedure of the
proposed inverter have been presented in detail. An exten-
sive comparison study with similar inverters shows that the
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3591
proposed inverter requires reduced switches and drivers for
realizing the same number of output voltage levels. This ben-
efit of the proposed inverter makes it more cost-effective than
other inverters. The efficiency, conduction losses, and ripple
losses of the proposed inverter have been evaluated for differ-
ent power levels and compared with similar inverters. It shows
that the proposed inverter has higher efficiency than others as
the output power level enhances. Lastly, the merits and effec-
tiveness of the proposed inverter have been validated with an
extensive experimental study.
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