Elo 1

Chapter #1: Signals and
Amplifiers
from Microelectronic Circuits Text
by Sedra and Smith
Oxford Publishing
Oxford University Publishing
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
Introduction
▪ IN THIS CHAPTER YOU WILL LEARN…

▪ That electronic circuits process signals, and thus
understanding electrical signals is essential to
appreciating the material in this book.
▪ The Thevenin and Norton representations of signal
sources.
▪ The representation of a signal as sum of sine waves.
▪ The analog and digital representations of a signal.

Introduction
▪ IN THIS CHAPTER YOU WILL LEARN…

▪ The most basic and pervasive signal-processing
function: signal amplification, and correspondingly,
the signal amplifier.
▪ How amplifiers are characterized (modeled) as circuit
building blocks independent of their internal circuitry.
▪ How the frequency response of an amplifier is
measured, and how it is calculated, especially in the
simple but common case of a single-time-constant
(STC) type response.

1.1. Signals
▪ signal – contains information

▪ e.g. voice of radio announcer reading the news
▪ process – an operation which allows an observer to
understand this information from a signal
▪ generally done electrically
▪ transducer – device which converts signal from non-
electrical to electrical form
▪ e.g. microphone (sound to electrical)
1.1: Signals
▪ Q: How are signals represented?

▪ A: thevenin form – voltage source vs(t) with series
resistance RS
▪ preferable when RS is low
▪ A: norton form – current source is(t) with parallel
resistance RS
▪ preferable when RS is high

1.1. Signals
Figure 1.1: Two alternative representations of a signal source: (a) the

Thévenin
Microelectronic Circuits by Adel S. Sedra form;
and Kenneth C. Smith (b) the Norton form.
(0195323033)
Example 1.1:
Thevenin and Norton
Equivalent Sources
▪ Consider two source / load combinations to upper-right.

▪ note that output resistance of a source limits its
ability to deliver a signal at full strength
▪ Q(a): what is the relationship between the source and
output when maximum power is delivered?
▪ for example, vs < vo??? vs > vo??? vs = vo???
▪ Q(b): what are ideal values of RS for norton and thevenin
representations?

1.2. Frequency
Spectrum of Signals
▪ frequency spectrum – defines the a time-domain signal

in terms of the strength of harmonic components
▪ Q: What is a Fourier Series?
▪ A: An expression of a periodic function as the sum
of an infinite number of sinusoids whose
frequencies are harmonically related

What is a Fourier
Series?
▪ decomposition – of a periodic function into the

(possibly infinite) sum of simpler oscillating functions
Fourier Series Representation of f( x)


a0
f( x ) = +
2
a cos(kx) + b sin(kx)
k =1
k k
1
ak =  f(x)cos(kx)dx , n0
 −
1
bk =  f(x)sin(kx)dx , n1
 −
What is a Fourier
Series? (2)
▪ Q: How does one calculate Fourier Series of square

wave below?
▪ A: See upcoming slides…

Fourier Series
Example
step #1: define ak for the square wave

note that the piece-wise square wave must be divided in two dc functions

−Va
0
Va
ak =
 −
 cos(kx)dx +   cos(kx)dx = 0 0
0 
1 1
sin( kx ) sin( kx )
k − k 0
1 1 1 1
sin( k 0 ) − sin( − k ) sin( k )− sin( k 0 )
k k k k
0 −0 0 −0

Fourier Series
Example
step #2: define bk for the square wave if k is even

−Va
0
Va
bk =
 −
 V sin(kx)dx +   sin(kx)dx
a
0
0 
1 1
− cos( kx ) − cos( kx )
k − k 0
1 1 1 1
− cos( k 0 ) + cos( − k ) − cos( k ) + cos( k 0 )
k k k k
1 1 1 1
− + (-1)k − (-1)k +
k k k k
 4Va
 k is odd
bk =  k
k is even 0
Fourier Series this series may be truncated
because the magnitude of each
Example terms decreases with k…
step #3: define Fourier Series
0
0 4Va
k

a0   
f(x) = +  ak cos(kx) + bk sin(kx)
2 k =1  
 
 
1
4Va  k is odd sin(k0t )
f( x ) =  
 k =1 
k  x = 0t
k is even 0
4Va  1 1 
f( x ) =  sin(0t ) + sin(30t ) + sin(50t ) + 
  3 5
Fourier Series
Example
Figure 1.6: The frequency spectrum (also known as the

lineOxford
spectrum)
University Publishingof the periodic square wave of Fig. 1.5.
1.2. Frequency
Spectrum of Signals
▪ Examine the sinusoidal wave below…
v a (t ) = Va sin(t +  )
Va = amplitude in volts
 = angular frequency in rad/sec
 = phase shift in rad
t = time in sec
root mean square magnitude =

sine wave amplitude / square root of two
1.2. Frequency
Spectrum of Signals
▪ Q: Can the Fourier Transform be applied to a non-

periodic function of time?
▪ A: Yes, however (as opposed to a discrete frequency
spectrum) it will yield a continuous…

1.3. Analog and
Digital Signals
▪ analog signal – is continuous with respect to both value

and time
▪ discrete-time signal – is continuous with respect to
value but sampled at discrete points in time
▪ digital signal – is quantized (applied to values) as well as
sampled at discrete points in time

1.3. Analog and
Digital Signals
analog signal
discrete-time signal
digital signal

1.3. Analog and
Digital Signals
sampling
quantization

1.3. Analog and
Digital Signals
▪ Q: Are digital and binary

synonymous?
digital
▪ A: No. The binary number
system (base2) is one way to
represent digital signals.
base 10  base 2
digital and
y = b0 2 + b1 2 + b2 2 +
0 1 2
binary LSB
+ b3 23 + bn−1 2n−1
MSB
1.4. Amplifiers
▪ Q: Why is signal amplification needed?

▪ A: Because many transducers yield output at low
power levels (mW)
▪ linearity – is property of an amplifier which ensures a
signal is not “altered” from amplification
▪ distortion – is any unintended change in output

1.4.1. Signal
Amplification
▪ voltage amplifier – is used to boost voltage levels for

increased resolution.
▪ power amplifier – is used to boost current levels for
increased “intensity”.
output / input relationship for amplifier
v o (t ) = Av v i (t )
voltage gain
1.4.2. Amplifier
Circuit Symbol
Figure 1.11: (a) Circuit symbol for amplifier. (b) An amplifier with
a common terminal (ground) between the input and output
ports.

1.4.4. Power and
Current Gain
▪ Q: What is one main difference between an amplifier

and transformer? …Because both alter voltage levels.
▪ A: Amplifier may be used to boost power delivery.
load power (PL ) voio

power gain (Ap ) = =
input power (PI ) vi ii

1.4.5. Expressing
Gain in Decibels
▪ Q: How may gain be expressed in decibels?
voltage gain in decibels = 20 log Av dB

current gain in decibels = 20 log Ai dB
power gain in decibels = 10 log(Ap )dB

1.4.6. Amplifier
Power Supply
▪ supplies – an amplifier has two power supplies

▪ VCC is positive, current ICC is drawn
▪ VEE is negative, current IEE is drawn
▪ power draw – from these supplies is defined below
▪ Pdc = VCC ICC + VEE IEE

1.4.6. Amplifier
Power Supply
▪ conservation of power – dictates that power input (Pi)

plus that drawn from supply (Pdc) is equal to output (PL)
plus that which is dissipated (Pdis).
▪ Pi + Pdc = PL + Pdissapated
▪ efficiency – is the ratio of power output to input.
▪ efficiency = PL / (Pi + Pdc)

1.4.6. Amplifier
Power Supply
Figure 1.13: An amplifier that requires two dc supplies (shown as

batteries)
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)for operation.
1.4.7. Amplifier
Saturation
▪ limited linear range – practically, amplifier operation is

linear over a limited input range.
▪ saturation – beyond this range, saturation occurs.
▪ output remains constant as input varies
Lminus Lplus
 vi 
Av Av
or...
Lminus vo Lplus

1.5. Circuit Models
for Amplifiers
▪ model – is the description of component’s (e.g.

amplifier) terminal behavior
▪ neglecting internal operation / transistor design

1.5.1. Voltage
Amplifiers
model of amplifier input terminals model of amplifier output terminals
Ri RL
input voltage = vi = (v s ) output voltage = vo = (Avovi )
R + Rs
source i
R + Ro
open-ckt L
volt. output
source and
input voltage output and
load
resistances resistances

1.5.1. Voltage
Amplifiers
▪ Q: How can one model the amplifier behavior from

previous slide?
▪ A: Model which is function of: vs, Avo, Ri, Rs, Ro, RL
 
 
 
R  RL = Avov s Ri RL
vo =  Avo (v s ) i
 source Ri + Rs  RL + Ro Ri + Rs RL + Ro
 volt. 
source and output and
 input  load
 resistances  resistances
open-ckt
Oxford University output voltage
Publishing
1.5.1. Voltage
Amplifiers
▪ Q: What is one “problem” with this behavior?

▪ A: Gain (ratio of vo and vs) is not constant, and
dependent on input and load resistance.
 
 
 
R  RL = Avov s Ri RL
vo =  Avo (v s ) i
 source Ri + Rs  RL + Ro Ri + Rs RL + Ro
 volt. 
source and output and
 input  load
 resistances  resistances
The ideal open-ckt

amplifier model neglects this nonlinearity.
output voltage
1.5.1. Voltage
Amplifiers
▪ ideal amplifier model – is function of vs and Avo only!!

▪ It is assumed that Ro << RL…
▪ It is assumed that Ri << Rs…
non-ideal model
ideal model
key characteristics of ideal voltage amplifier model = high input

impedance,
Oxford University Publishing low output impedance
1.5.1. Voltage
Amplifiers
▪ ideal amplifier model – is function of vs and Avo only!!

▪ It is assumed that Ro << RL…
▪ It is assumed that Ri << Rs…
Ri RL
vo = Avov s = Avov s
Ri + Rs RL + Ro ideal
model
non-ideal model
key characteristics of ideal voltage amplifier model = source

resistance RS Publishing
Oxford University and load resistance RL have no effect on gain
1.5.2. Cascaded
Amplifiers
▪ In real life, an amplifier is not ideal and will not have

infinite input impedance or zero output impedance.
▪ Cascading of amplifiers, however, may be used to
emphasize desirable characteristics.
▪ first amplifier – high Ri, medium Ro
▪ last amplifier – medium Ri, low Ro
▪ aggregate – high Ri, low Ro

Example 1.3:
Cascaded Amplifier
Configurations
▪ Examine system of cascaded amplifiers on next slide.

▪ Q(a): What is overall voltage gain?
▪ Q(b): What is overall current gain?
▪ Q(c): What is overall power gain?

Example 1.3:
Cascaded Amplifier
Configurations
aggregate amplifier
with gain
vL
Av =
v s − ii Rs
Figure 1.17: Three-stage amplifier for Example 1.3.

1.5.3. Other
Amplifier Types
voltage amplifier current amplifier
transconductance amp. transresistance amp.

1.5.3. Other
Amplifier Types
v0 Ri =  i0 Ri = 0
Av 0 = with Av 0 = with
vi i0 =0
Ro = 0 ii v0 =0
Ro = 
voltage amplifier current amplifier
transconductance amplifier transresistance amplifier
i0 Ri =  v0 Ri = 0
Gm = with Rm = with
vi v by =Adel
0 University
Oxford
R =
Publishing o ii i0 =0
Ro = 0
Microelectronic Circuits 0 S. Sedra and Kenneth C. Smith (0195323033)
1.5.4. Relationship
Between Four Amp
Models
▪ interchangeability – although these four types exist,

any of the four may be used to model any amplifier
▪ they are related through Avo (open circuit gain)
current
to voltage transres.
amplifier transcond. to voltage
to voltage amplifier
amplifier
 Ro  Rm
Avo = Ais   = GmRo =
 Ri  Ri

1.5.5. Determining
Ri and Ro
▪ Q: How can one calculate input resistance from terminal

behavior?
▪ A: Observe vi and ii, calculate via Ri = vi / ii
▪ Q: How can one calculate output resistance from
terminal behavior?
▪ A:
▪ Remove source voltage (such that vi = ii = 0)
▪ Apply voltage to output (vx)
▪ Measure negative output current (-io)
▪ Calculate via Ro = -vx / io
Section 1.5.5:
Determining Ri and Ro
▪ question: how can we calculate input resistance from terminal behavior?

▪ answer: observe vi and ii, calculate via Ri = vi / ii
▪ question: how can we calculate output resistance from terminal behavior?
▪ answer:
▪ remove source voltage (such that vi = ii = 0)
▪ apply voltage to output (vx)
▪ measure negative output current (-io)
▪ calculate via Ro = -vx / io
Figure 1.18: Determining the output

resistance.
1.5.6. Unilateral
Models
▪ unilateral model – is one in which signal flows only from

input to output (not reverse)
▪ However, most practical amplifiers will exhibit some
reverse transmission…

Example 1.4:
Common-Emitter
Circuit
▪ Examine the bipolar junction transistor (BJT).

▪ three-terminal device
▪ when powered up with dc source and operated with
small signals, may be modeled by linear circuit below.

input resistance (r)
base Example 1.4. collector
output resistance (ro)
▪ examine:
▪ bipolar junction transistor (BJT):
▪ three-terminal device
▪ when powered up with dc source and operated with small signals, may
be modeled by linear circuit below.
short-circuit Figure 1.19 (a) small-signal

circuit model for a bipolar
conductance junction transistor (BJT)
(gm) Oxford University Publishing
emitter
Example 1.4:
Common-Emitter
Circuit
▪ Q(a): Derive an expression for the voltage gain vo / vi of

common-emitter circuit with:
▪ Rs = 5kohm
▪ r = 2.5kohm
▪ gm = 40mA/V
▪ ro = 100kohm
▪ RL = 5kohm

input and output share common terminal
source load
Figure 1.19(b): The BJT connected as an amplifier with

the emitter as a common terminal between input and
Microelectronic Circuits by output
Adel S. Sedra and(called
Kenneth C. Smitha common-emitter amplifier).
(0195323033)
1.6.1. Measuring the
Amplifier Frequency
Response
▪ Q: How does one examine frequency response?

▪ A: By applying sine-wave input of amplitude Vi and
frequency .
▪ Q: Why?
▪ A: Because, although its amplitude and phase may
change, its shape and frequency will not.
this characteristic of sine wave applied to linear circuit is
unique
1.6.1: Measuring the
Amplifier Frequency
Response
input and output are similar for linear
amplifier

1.6.1. Measuring the
Amplifier Frequency
Response
▪ amplifier transfer function (T) – describes the input-

output relationship of an amplifier – or other device –
with respect to various parameters, including
frequency of input applied.
▪ It is a complex value, often defined in terms of
magnitude and phase shift.
Vo
T() = and T( ) = 
Vi phase shift
magnitude gain
1.6.2. Amplifier
Bandwidth
▪ Q: What is bandwidth of a device?

▪ A: The range of frequencies over which its
magnitude response is constant (within 3dB).
▪ Q: For an amplifier, what is main bandwidth concern?
▪ A: That the bandwidth extends beyond range of
frequencies it is expected to amplify.

1.6.2. Amplifier
Bandwidth

1.6.4. Single Time-
Constant Networks
▪ single time–constant (STC) network – is composed of

(or may be reduced to) one reactive component and
one resistance.
▪ low pass filter – attenuates output at high
frequencies, allow low to pass
▪ high pass filter – attenuates output at low
frequencies, allow high to pass
▪ time constant (t.) – describes the length of time
required for a network transient to settle from step
change (t = L / R = RC)
1.6.4. Single Time-
Constant Networks
▪ low pass filter (left) Figure 1.22:output

attenuates Two examples
at highofsSTC
networks: (a) a low-pass network
▪ high pass filter (right) and (b) a high-pass network.

1.6.4. Single Time- 1
vo Zo jC 1
Constant Networks
low-pass: = = k
vi Z i + Z o R + 1 
jC
vo Zo R
high-pass: = =  k
vi Z i + Z o R + 1
jC

1.6.4. Single Time-
Figure 1.2 : Characteristics of Various STC
Constant Networks
low - pass high - pass
K Ks
transfer function
1 + ( s / 0 ) 1 + 0
transfer function K K
(for physical freq.) 1 + j( / 0 ) 1 − j(0 /  )
K K
magnitude response
1 + j( / 0 )2 1 + j(0 /  )2
phase response −tan( / 0 ) tan(0 /  )
transmission at  = 0 K 0
transmission at  =  0 K
1
3db Frequency 0 = same
t
Bode Plots refer to next slide
Figure: Low-Pass Filter Magnitude (top-left) and Phase
(top-right) Responses as well as High-Pass Filter (bottom-
left) and Phase (bottom-right) Responses

-20dB/decade drop, beginning -45 degrees/decade drop,
from maximum gain at corner moving outward from -45
Figure: Low-Filter Magnitude degree
frequency (top-left) andatPhase
shift corner(top-
frequency
right) Responses as well as High-Pass Filter (bottom-left)
and Phase (bottom-right) Responses
+20dB/decade incline, until -45 degrees/decade drop,
maximum gain is reached at moving outward from +45
corner frequency degree shift at corner frequency

Example 1.5:
Voltage Amplifier
▪ Examine voltage amplifier with:

▪ input resistance (Ri)
▪ input capacitance (Ci)
▪ gain factor (m)
▪ output resistance (Ro)
▪ Q(a): Derive an expression for the amplifier voltage gain
Vo / Vs as a function of frequency. From this, find
expressions for the dc gain and 3dB frequency.
Example 1.5:
Voltage Amplifier

Example 1.5:
Voltage Amplifier
▪ Q(b): What is unity-gain frequency? How is it

calculated?
▪ A: Gain = 0dB
▪ A: It is known that the gain of a low-pass filter drops
at 20dB per decade beginning at 0. Therefore unity
gain will occur two decades past 0 (40dB – 20dB –
20dB).
▪ Q(c): Find vo(t) for each of the following input: vs =
0.1sin(102t), vs = 0.1sin(105t)
1.6.5. Classification of
Amps Based on
Frequency Response
▪ internal capacitances – cause the falloff of gain at high

frequencies
▪ like those seen in previous example
▪ coupling capacitors – cause the falloff of gain at low
frequencies
▪ are placed in between amplifier stages
▪ generally chosen to be large

1.6.5. Classification of
Amps Based on
Frequency Response
▪ directly coupled / dc amplifiers – allow passage of low

frequencies
▪ capacitively coupled amplifiers – allow passage of high
frequencies
▪ tuned amplifiers – allow passage of a “band” of
frequencies

Conclusion
▪ An electrical signal source can be represented in either Thevenin

form (a voltage source vs in series with source resistance Rs) or the
Norton form (a current source is in parallel with resistance Rs). The
Thevenin voltage vs is the open-circuit voltage between the source
terminals. The Norton current is is equal to the short-circuit
current between the source terminals. For the two
representations to be equivalent, vs and Rsis must be equal.
▪ A signal can be represented either by its waveform vs time or as
the sum of sinusoids. The latter representation is known as the
frequency spectrum of the signal.

Conclusion (2)
▪ The sine-wave signal is completely characterized by its peak value

(or rms value which is the peak / 21/2), frequency ( in rad/s of f in
Hz;  = 2f and f = 1/T, where T is the period is seconds), and
phase with respect to an arbitrary reference time.
▪ Analog signals have magnitudes that can assume any value.
Electronic circuits that process analog signals are called analog
circuits. Sampling the magnitude of an analog signal at discrete
instants of time and representing each signal sample by a number
results in a digital signal. Digital signals are processed by digital
circuits.

Conclusion (3)
▪ The simplest digital signals are obtained when the binary number
system is used. An individual digital signal then assumes one of
only two possible values: low and high (e.g. 0V and 5V)
corresponding to logic 0 and logic 1.
▪ An analog-to-digital converter (ADC) provides at its output the
digits of the binary number representing the analog signal sample
applied to its input. The output digital signal can then be
processed using digital circuits.
▪ A transfer characteristic, vo vs. vi, of a linear amplifier is a straight
line with a slope equal to the voltage gain.

Conclusion (4)
▪ Amplifiers increase the signal power and thus require dc power

supplies for their operation.
▪ The amplifier voltage gain can be expressed as a ratio Av in V/V or
in decibels, 20log|Av| in dB.
▪ Depending on the signal to be amplified (voltage or current) and
on the desired form of output signal (voltage or current) there are
four basic amplifier types: voltage, current, transconductance, and
transresistance. A given amplifier may be modeled by any of
these configurations, in which case their parameters are related
by (1.14) through (1.16) in the text.

Conclusion (5)
▪ The sinusoid is the only signal whose waveform is unchanged

through a linear circuit. Sinusoidal signals are used to measure
the frequency response of amplifiers.
▪ The transfer function T(s) = Vo(s)/Vi(s) of a voltage amplifier may
be determined from circuit analysis. Substituting s = j gives T(j)
whose magnitude (|T(j)| is the magnitude response and () is
the phase response.
▪ Amplifiers are classified according to the shape of their frequency
response.

Conclusion (6)
▪ Single-time-constant (STC) networks are those networks that are

composed of, or may be reduced to, one reactive component (L
or C) and one resistance. The time constant (t) is L/R or RC.
▪ STC networks can be classified into two categories: low-pass (LP)
and high-pass (HP). LP network pass dc and low-frequencies
while attenuating high-frequencies. The opposite is true for HP.
▪ The gain of an LP (HP) STC circuit drops by 3dB below the zero-
frequency (infinite-frequency) value at a frequency 0 = 1/t. At
high-frequencies (low-frequencies) the gain falls of at a rate of
6dB/octave or 20dB/decade.
▪ Refer to Table 1.2. on page 34 and Figs. 1.23 and 1.24. Further details are
provided
Oxfordin Appendix
University Publishing E.
Chapter #2: Signals and
Amplifiers
by Sedra and Smith
Oxford Publishing
Introduction
▪ IN THIS CHAPTER YOU WILL LEARN

▪ The terminal characteristics of the ideal op-amp.
▪ How to analyze circuits containing op-amps, resistors,
and capacitors.
▪ How to use op-amps to design amplifiers having
precise characteristics.

Introduction
▪ IN THIS CHAPTER YOU WILL LEARN

▪ How to design more sophisticated op-amp circuits,
including summing amplifiers, instrumentation
amplifiers, integrators, and differentiators.
▪ Important non-ideal characteristics of op-amps and
how these limit the performance of basic op-amp
circuits.

2.1.1. The Op Amp
Terminals
▪ terminal #1
▪ inverting input
▪ terminal #2
▪ non-inverting input
▪ terminal #3
▪ output
▪ terminal #4
▪ positive supply VCC
▪ terminal #5
▪ negative supply VEE
2.1.2. Function and
Characteristics of
Ideal Op Amp
▪ ideal gain is defined below

v3 = A(v2 − v1 )
▪ ideal input characteristic is infinite impedance

▪ ideal output characteristic is zero impedance
▪ differential gain (A) is infinite
▪ bandwidth gain is constant from dc to high
frequencies
Q: But, is an amplifier with infinite gain of any use?

2.1.2. Function and
Characteristics of
Ideal Op Amp
▪ ideal gain: is defined below
v3 = A(v2 − v1 )
▪ ideal input characteristic: infinite impedance
▪ ideal output characteristic: zero impedance

2.1.2. Function and
Characteristics of
Ideal Op-Amp
▪ An amplifier’s input is composed of two components…

▪ differential input (vdfi) – is difference between inputs
at inverting and non-inverting terminals
▪ common-mode input (vcmi) – is input present at both
inverting and non-inverting terminals
common-mode differential
input (vcmi ) input (vdfi )
vin = (10 + 1) − (10 − 1 ) = (10 − 10 ) + (1 + 1)

2.1.2. Function and
Characteristics of
Ideal Op-Amp
▪ Similarly, two components of gain exist…

▪ differential gain (A) – gain applied to differential input
ONLY
▪ common-mode gain (Acm) – gain applied to common-
mode input ONLY
common-mode differential
e.g. v1 =10 +1 e.g. v2 =10 −1 output output
vout = ( Acm 10 + A1) − ( Acm 10 − A1 ) = Acm (10 − 10 ) + A (1 + 1 )

2.1.2. Function and
Characteristics of
Ideal Op Amp
▪ Table 2.1: Characteristics of Ideal Op Amp

▪ infinite input impedance
▪ zero output impedance
▪ zero common-mode gain (Acm = 0)
▪ complete common-mode rejection
▪ infinite open-loop gain (A = infinity)
▪ infinite bandwidth

2.1.3. Differential &
Common-Mode
Signals
▪ Q: How is common-mode input (vcmi) defined in

terms of v1 and v2?
inverting input
common-mode input
v1 = vcmi − vdi / 2
1
vcmi = (v1 + v2 ) but also... diff
2 v2 = vcmi + vdi /2
non-inverting input

2.1.3. Differential &
Common-Mode
common-mode input
1 Signals
vcmi = (v1 + v2 )
2
but also...
inverting input
v1 = vcmi − vdi /2
diff
v2 = vcmi + vdi /2
non-inverting input

2.2. The Inverting
Configuration
▪ Q: What are two basic closed-loop op-amp

configurations which employ op-amp and resistors
alone?
▪ A: 1) inverting and 2) non-inverting op amp

Figure
2.2. The2.5:Inverting
The inverting closed-loop configuration.
Configuration R2 facilitates “negative

feedback”
R1 regulates
▪ question: level
what are twoofbasic closed-loop op amp configurations which
this
employ feedback
op-amp and resistors alone?
▪ answer: inverting and non-inverting op amp
▪ note: here we examine the inverting type
non-inverting input is
grounded
source is applied to
inverting
Microelectronic input
Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)
2.2.1.
Closed-Loop Gain
▪ Q: How does one analyze closed-loop

gain for inverting configuration of an
ideal op-amp?
▪ step #1: Begin at the output
terminal
▪ step #2: If vOut is finite, then because A in infinite
differential input must equal 0 vOut

v2 − v1 = =0
▪ virtual short circuit btw v1 and v2 A

▪ virtual ground exists at v1
2.2.1.
Closed-Loop Gain
▪ step #3: Define current in to inverting input (i1).

▪ step #4: Determine where this current flows?
▪ refer to following slide…
virtual
ground
(vIn ) − (v1 ) vIn − 0 vIn

i1 = = =
R1 R1 R1

2.2. The
Figure 2.5:Inverting
The inverting closed-loop configuration.
Configuration
i1
▪ question: what are two basic closed-loop op amp configurations which
employ op-amp and resistors alone?
▪ answer: i
1 inverting and non-inverting op-amp i=0
▪ note: here we examine the inverting type

2.2.1.
Closed-Loop Gain
▪ step #5: Define vOut in virtual

ground
terms of current flowing
vOut = (v1 ) − (i1R2 ) = −i1R2
across R2.
▪ step #6: Substitute vin / R1 R2
for i1. vOut = − vIn
R1
solution
note: this expression is one of the fundamentals of

electronics
Figure 2.6: Analysis
2.2.1. of the inverting configuration. The circled
numbers indicate the order of the analysis steps.
Closed-Loop Gain
▪ question: how will we…

▪ step #4: define vOut in terms of closed-loop
current flowing across R2
▪ step #5: substitute vin / R1 for i1. gain
G = -R2/R1

2.2.1. Effect of Finite
Open-Loop Gain
▪ Q: How does the gain expression change if open loop

gain (A) is not assumed to be infinite?
▪ A: One must employ analysis similar to the
previous, result is presented below…
GA =
vOut −R2 / R1 R2
GA = = −
vIn  1 + (R2 / R1 )  R1
1+ 
 A 
if A= then the previous
gain expression is yielded
non-ideal gain Oxford University Publishing
ideal gain
2.2.1. Effect of Finite
Open-Loop Gain
▪ Q: Under what condition can G = -R2 / R1 be

employed over the more complex expression?
▪ A: If 1 + (R2/R1) << A, then simpler expression may
be used.
R2 R2 −R2 / R1
if 1 +  A then GA= = − else GA =
R1 R1  1 + (R2 / R1 ) 
1+ 
 A 
ideal gain Oxford University Publishing

Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033) non-ideal gain
Example 2.1: Simple
Inverting Amplifier
▪ Problem Statement: Consider an inverting configuration

with R1 = 1kOhm and R2 = 100kOhm.
▪ Q(a): Find the closed-loop gain (G) for the cases below.
In each case, determine the percentage error in the
magnitude of G relative to the ideal value.
▪ cases are A = 103, 104, 105…
▪ Q(b): What is the voltage v1 that appears at the inverting
input terminal when vIn = 0.1V.
▪ Q(c): If the open loop gain (A) changes from 100k to 50k,
what is percentage change in gain (G)?
2.2.3. Input and
Output Resistances
▪ Q: What is input resistance for inverting op-amp? How is it

defined mathematically?
▪ A: R1 (refer to math below)
▪ Q: What does this say?
▪ A: That, for the combination of ideal op-amp and external
resistors, input resistance will be finite…
action:
simplify
action: simplify
this assumes that
ideal op-amp and v vIn v
Ri = In = = In = R1
external resistors are iIn (vIn − v1 )/ R1 vIn / R1
considered “one same virtual
as i1 ground
unit” Oxford University Publishing
=0
Example 2.2:
Another Inverting
Op-Amp
▪ Problem Statement: Consider the

circuit below...
▪ Q(a): Derive an expression for the
closed-loop gain vOut/vIn of this
circuit.
▪ Q(b): Use this circuit to design an
inverting amplifier with gain of 100
and input resistance of 1Mohm.
▪ Assume that one cannot use any
resistor with resistance larger
than 1Mohm. Figure 2.8: Circuit for Example 2.2. The
▪ Q(c): Compare your design with that circled numbers indicate the sequence
based on traditional inverting of the steps in the analysis.
configuration. Oxford University Publishing
Example 2.2:
Figure 2.9: A current amplifier based on the circuit of Fig. 2.8. The
PART B: Use this circuit to design
an inverting amplifier with gain
of 100 and input resistance of
Another
amplifier Inverting
delivers its output current to R4. It has a current gain of (1 + 1Mohm. Assume that one
cannot use any resistor with
R2 /R3), a zero input resistance, and an infinite output resistance. The resistance larger than 1Mohm.
Op-Amp
load (R4), however, must be floating (i.e., neither of its two terminals
can be connected to ground).
▪ The largest resistor on may choose is 1Mohm
▪ Q: Where does one begin (in choosing the resistor
values)? Which resistor would you define to be 1Mohm?
▪ A: The input resistance (R1) should be set as high as
possible, therefore 1Mohm
▪ Q: What other resistor values should be defined?
▪ A: R2 = 1Mohm, R4 = 1Mohm, R3 = 10.2kohm

2.2.4. An Important
Application –
The Weighted Summer
▪ weighted summer - is a closed-loop amplifier

configuration which provides an output voltage which
is weighted sum of the inputs.
Figure 2.10: A weighted

summer.

vOut = 2.2.4. An Important
-[ (Rf./R In1)vIn1 + (Rf./RIn2)vIn2 + (Rf./RIn3)vIn3 + … ]
Application –
The Weighted Summer
▪ weighted summer - is a closed-loop amplifier

configuration which provides an output voltage which
is weighted sum of the inputs.
RIn1 Rf
vIn1
RIn2
vIn2 Figure 2.10: A weighted
RIn3 vOut
vIn3 summer.

2.3. The
Non-Inverting
Configuration
▪ non-inverting op-amp configuration – is one which

utilizes external resistances (like the previous) to
effect voltage gain. However, the polarity / phase of
the output is same as input.

Figure 2.12: The non-inverting configuration.
2.3. The Non-Inverting
Configuration R1 and R2 act as voltage divider,
regulating negative feedback to the
inverting input
inverting input is
grounded
through R1
node #1
node #2
source is applied to
Oxford University Publishing non-inverting input
Characteristics of Non-Inverting Op-Amp
Configuration
vOut
vIn
 R  R2 1 + (R2 / R1 )
ideal gain  A  1 + 2  : GA= = 1 +
 R1  R1 1 + 1 + (R2 / R1 )
A
1 + (R2 / R1 )
non - ideal gain : . GA =
1 + (R2 / R1 )
vOut 1+
vIn A
1 + (R2 / R1 ) 1 + (R2 / R1 )
percent gain error : pge = 100
A + 1 + (R2 / R1 ) 1 + 1 + (R2 / R1 )
A
 R1  1 + (R2 / R1 )
inverting input potential : .v1 = vOut  
Microelectronic Circuits by Adel S. Sedra and Kenneth C. Smith (0195323033)  R1 + R2  1 + 1 + (R2 / R1 )
Configuration and Characteristics of Buffer /
Voltage-Follower Op-Amp Configuration
Figure 2.14: (a) The unity-gain buffer or follower amplifier. (b) Its
equivalent circuit model.
MainConfiguration and Characteristics
point? For the buffer of Buffer
amp, output voltage /
is equal
Voltage-Follower
(in both Op-Amp
magnitude and phase) Configuration
to the input source.
However, any current supplied to the load is drawn from
amplifier supplies (VCC, VEE) and not the input source (vI).
Figure 2.14: (a) The unity-gain buffer or follower amplifier. (b) Its
equivalent circuit model.
2.4. Difference
Amplifiers
▪ difference amplifier – is a closed-loop configuration

which responds to the difference between two
signals applied at its input and ideally rejects signals
that are common to the two.
▪ Ideally, the amp will amplify only the differential
signal (vdfi) and reject completely the common-
mode input signal (vcmi). However, a practical
circuit will behave as below…
vOut = Avdfi + Acmvcmi
2.4. Difference
Amplifiers
common-mode input
common-mode gain
differential input
differential gain
vOut = Avdfi + Acmvcmi

2.4. Difference
Amplifiers
▪ common-mode rejection ratio (CMRR) – is the

degree to which a differential amplifier “rejects” the
common-mode input.
▪ Ideally, CMRR = infinity…
A
CMRR = 20 log10
ACm

2.4.Representing
Figure 2.15: Difference the input signals to a differential amplifier
in terms Amplifiers
of their differential and common-mode components.
ADi
CMMR = 20 log10
ACm

2.4. Difference
Amplifiers
▪ Q: The op amp itself is differential in nature, why

cannot it be used by itself?
▪ A: It has an infinite gain, and therefore cannot be
used by itself. One must devise a closed-loop
configuration which facilitates this operation.

2.4. Difference
Figure 2.16: A difference amplifier.
Amplifiers

2.4.1. A Single
Op-Amp
Difference Amp
▪ Q: What are the characteristics of the difference

amplifier?
▪ A: Refer to following equations…
(R2 + R1 )R4 R2
vOut = vIn2 − vIn1
(R4 + R3 )R1 R1
R1 = R3  R2
but if   then vOut = ( vIn2 − vIn1 )
R
 2 = R4 R1
A Shift in Notation
▪ Before this point…

▪ The parameter A is used to represent open-loop gain of an
op amp.
▪ The parameter G is used to represent ideal / non-ideal
closed-loop gain of an op amp.
▪ After this point…
▪ The parameter A is used to represent ideal gain of an op
amp in a given closed-loop configuration.
▪ The parameter G is not used.

2.4.2. The
Instrumentation
Amplifier
▪ Q: What is one problem associated with the

difference amplifier?
▪ A: Low input impedance.
▪ Q: And, what does this mean practically?
▪ A: That source impedance will have an effect on
gain.
▪ Q: What is the solution?
▪ A: Placement of two buffers at the input terminals,
amplifiers which transmit the voltage level but
draw minimal current.
2.4.2. The
Instrumentation
Amplifier
▪ Q: However, can one get “more” from these amps

than simply impedance matching?
▪ A: Yes, maybe additional voltage gain???

2.4.2. The
Instrumentation
Figure 2.20: A popular circuit for an instrumentation amplifier.
Amplifier
stage #1 stage #2
▪ question: however, can we get “more” from these amps than simply
non-inverting
impedance matching?
op amp (A1)
▪ answer: yes, maybe additional voltage gain???
difference op
vOut = (1 + R2/R1)vIn
amp (A3)
vOut = (R4/R3)vdfi
non-inverting
op amp (A2)
2.4.2. The
Instrumentation
Amplifier
▪ Q: However, can one get “more” from these amps

than simply impedance matching?
▪ A: Yes, maybe additional voltage gain???
transfer function for
instrumentation amplifier of figure 2.20.
R4  R2  additional voltage gain

vOut =  1 +  vdfi
R3  R1 
A Inst (R )

2.4.2. The
Instrumentation
Amplifier
▪ advantages of instrumentation amp

▪ very high input resistance
▪ high differential gain
▪ symmetric gain (assuming that A1 and A2 are matched)
▪ disadvantages of instrumentation amp
▪ ADi and ACm are equal in first stage – meaning that the
common-mode and differential inputs are amplified
with equal gain…

What is problem
with ACm = A?
vIn1 vIn1 A = 10
A = 25
A = 10 x 25
vIn2 vIn2
differential gain >> common-mode gain differential gain = common-mode gain

differential gain >>
common-mode gain
vIn1 = 10.03V
vOut= 250 x (10.03-10.02)V

A = 10 x 25
vOut = 2.5V no problem!!!
vIn2 = 10.02V
differential gain =
common-mode gain
vOut1= 10 x 10.03 = 15V saturation

vIn1 = 10.03V
A = 25
A = 10 vOut= 25 x (15-15)V
vOut = 0V problem!!!
vIn2 = 10.02V vOut2= 10 x 10.02 = 15V saturation

2.4.2. The
Instrumentation
Amplifier
▪ advantages of instrumentation amp

▪ very high input resistance
▪ high differential gain
▪ symmetric gain (assuming that A1 and A2 are matched)
▪ disadvantages of instrumentation amp
▪ ADi and ACm are equal in first stage – meaning that the
common-mode and differential inputs are amplified with
equal gain…
▪ need for matching – if two op amps which comprise stage
#1 are not perfectly matched, one will see unintended
effects Oxford University Publishing
2.4.2. The
Instrumentation
Amplifier
▪ Q: How can one fix this (alleviate these

disadvantages)?
▪ A: Disconnect the two resistors (R1) connected to
node X from ground, making the configuration
“floating” in nature…
▪ A: Refer to following slide…

Figure 2.20: A2.4.2. The
popular circuit for an instrumentation amplifier. (b)
The circuitInstrumentation
in (a) with the connection between node X and ground
removed and Amplifier
the two resistors R1 and R1 lumped together. This
simple wiring change dramatically improves performance.

2.4.2. The
Instrumentation
Amplifier
▪ Q: How can one analyze this circuit?

2.4.2. The for both op amp A1 and A2
Instrumentation v( + ) − v( − ) = 0
Amplifier ...therefore
v( + ) = v( − )
▪ step #1: note that virtual
short circuit exists across vInDi
terminals of op amp A1
vIn2 − vIn1
and A2 iR1 =
▪ step #2: define current 2R1
flow across the resistor 2R1
▪ step #3: define output of because no current will flow
into ideal op amp, all of iR1 will
flow across R2
A1 and A2
vOut 1 = vIn1 − iR1R2
vOut 2 = vIn2 + iR1R2
2.4.2. The
Instrumentation
Amplifier
short-ckt
vOut1
iR1
vOut2

2.4.2. The
Instrumentation action: define (from equations above) the
differential input vOut 2 −vOut 1 to stage #2
Amplifier   vIn2 − vIn1  

vOut 2 − vOut 1 = vIn2 +   R2  −
  2R1  
▪ step #4: Define vOut 2 =vIn 2 + iR 1R2
output of A1 and A2   vIn2 − vIn1  

− vIn1 −   R2 
in terms of input   2R1  
vOut 1 =vIn 1 −iR 1R2
alone action: combine terms
 vInDi 
 vIn2 − vIn1 
vOut 2 − vOut 1 = (vIn2 − vIn1 ) + 2   R2
vInDi  2R1 
 
 2R 
vOut 2 − vOut 1 =  1 + 2  vInDi
 2R1 
2.4.2. The
Instrumentation
Amplifier action: define in
terms of vdfi
R4
▪ step #5: Define output of vOut = (vOut 2 − vOut 1 )
R3
A3.
▪ step #6: Define gain of R4  2R2 
vOut = 1 +  vdfi
revised instrumentation R3  2R1 
amplifier.
vOut R4  2R2 
= ADi =  1 + 
vdfi R3  2R1 
solution
2.5. Integrators and
Differentiators
▪ integrator / differentiator amplifier – is one which

outputs an integral or derivative of the input signal.

2.5.1. The Inverting
Configuration
with General Impedances
▪ Q: Does the transfer function for the inverting op amp

change if the feedback and input impedances are not
purely resistive?
▪ A: No, not in form…

Example 2.4: Other
Op-Amp
Configurations
▪ Consider the circuit on next slide page.

▪ Q(a): Derive an expression for the transfer function vOut /
vIn.
▪ Q(b): Show that the transfer function is of a low-pass STC
circuit.
▪ Q(c): By expressing the transfer function in standard
form of Table 1.2, find the dc-gain and 3dB frequency.

Example 2.4: Other
Op-Amp
Configurations
Figure 2.23: Circuit for Example 2.4.

Integrator
▪ Q: How can inverting op-amp be adapted to perform

integration?
▪ A: Utilization of capacitor as feedback impedance.

2.5.2.
Figure 2.24:The Inverting
(a) The miller or inverting integrator. (b) Frequency
response of the integrator.
Integrator
initial
output
voltage
1  
t
transient description (dc): .vOut (t ) = −   vIn (t )dt  − vOut (t 0 )
R1C F  t =0 
vOut 1
steady-state description (ac): =−
vIn sR1C F
Integrator
▪ Q: What is the problem with this configuration (related

to dc gain)?
▪ A: At dc frequency (w = 0), gain is infinite
▪ Gain = 1 / (w.R1CF)
▪ Q: Solution?
▪ A: By placing a very large resistor in parallel with the
capacitor, negative feedback is employed to make dc
gain “finite.”

Figure 2.25: The Miller integrator with a large resistance RF
2.5.2. The
connected Invertingwith
in parallel Integrator
C in order to provide negative feedback
and hence finite gain at dc.
transient description (dc): depends on input signal???

vOut RF / R1
steady-state description (ac): =−
vIn 1 + sRF CF
Example 2.5: Miller
Integrator
▪ Consider the Miller integrator…

▪ Q(a): Find response of a Miller Integrator to input pulse
of 1V height and 1ms width.
▪ R1 = 10kOhm, CF = 10nF
▪ Q(b): If the integrator capacitor is shunted by a 1MOhm
resistor, how will the response be modified?
▪ note: the op amp will saturate at +/- 13V

2.5.3. The Op-Amp
Differentiator
▪ Q: How can one adapt integrator to perform

differentiation?
▪ A: Interchange locations of resistors and capacitors.
Figure 2.27: A differentiator.

2.5.3. The Op-Amp
Differentiator
dv In (t )
transient description (dc): vOut (t ) = −RF C1
dt
VOut (s)
steady-state description (ac): = − sRF C1
VIn (s)
Figure 2.27: A differentiator.

2.5.3. The Op-Amp
Differentiator
▪ filtering characteristic is high pass filter

▪ magnitude of transfer function is |VOut / VIn| = wRFC1
▪ phase of transfer function is f = -90O
▪ differentiator time-constant is frequency at which unity
gain occurs and defined as w = 1 / RFC1
▪ Q: What is the problem with differentiator?
▪ A: Differentiator acts as noise amplifier, exhibiting
large changes in output from small (but fast) changes
in input. As such, it is rarely used in practice.
2.6. DC
Imperfections
▪ Q: What will be discussed moving on?

▪ A: When can one NOT consider an op amp to be ideal,
and what effect will that have on operation?

2.6.1. Offset Voltage
▪ Q: What is input offset

voltage (VOS)?
▪ A: An imaginary
voltage source in series
with the user-supplied
input, which effects an
op amp output even
when idfi = 0.
Figure 2.28: circuit model for an
What will happen when short is op amp with input offset
applied?
Oxford University Publishing voltage VOS.
▪ Q: What causes VOS?

▪ A: Unavoidable mismatches in
the differential stage of the op offset dc offset
output voltage
amp. It is impossible to  RF 
perfectly match all transistors. VdcOut = VOS 1 + 
 R1 
▪ Q: Range of magnitude?
▪ A: 1mV to 5mV

This relationship between offset voltage (VOS) and offset dc output
(V OsOut) applies
2.6.1. Offset to Voltage
both inverting and non-inverting op amp.
However, only if one assumes that VOS is present at non-inverting
input.
▪ Q: What causes VOS?

▪ A: Unavoidable mismatches in
the differential stage of the op offset dc offset
output voltage
amp. It is impossible to  RF 
perfectly match all transistors. VdcOut = VOS 1 + 
 R1 
▪ Q: Range of magnitude?
▪ A: 1mV to 5mV

▪ Q: How can this offset be reduced?

▪ A: offset nulling terminals – A variable resistor (if
properly set) may be used to reduce the asymmetry
present and, in turn, reduce offset.
▪ A: capacitive coupling – A series capacitor placed
between the source and op amp may be used to
reduce offset, although it will also filter out dc signals.

Figure 2.30: The output dc offset voltage of an op-amp can be
trimmed to zero by connecting a potentiometer to the two
offset-nulling terminals. The wiper of the potentiometer is
connected to the negative supply of the op amp.

Figure 2.31: (a) A capacitively-coupled inverting amplifier. (b)
The equivalent circuit for determining its dc output offset
voltage VO.
dc signals cannot pass!

2.6.2. Input Bias Figure 2.32: The op-amp input
and Offset Currents bias currents represented by
two current sources IB1 and IB2.
▪ input bias current - is the

dc current which must be
supplied to the op-amp
inputs for proper
operation.
▪ Ideally, this current is
zero…
▪ input offset current - the
difference between bias
current at both terminals
2.6.2: Input Bias Figure 2.32: The op-amp input
bias current
and Offset Currents bias currentsatrepresented
terminals by
#1 and I#2
two current sources B1 and IB2.
IB1 + IB2
input
▪ input biasbias current:
current - is the . IB =
dc current which must be 2
supplied to the op-amp difference
between bias'
inputs for proper
operation.
input offset current: IOS = IB1 − IB2
▪ Ideally, this current
is zero…
▪ input offset current - the
difference between bias
resulting
current at bothoutput
terminalsvoltage: VBOut = IB1RF
2.6.2. Input Bias
and Offset Currents
▪ Q: How can this bias be resistor placed between

non-inverting input
reduced? and ground (R3 ) should
equal parallel connection
▪ A: Placement of R3 as of inverting input
resistance and feedback
additional resistor
between non-inverting R1RF
R3 =
input and ground. R1 + RF
▪ Q: How is R3 defined?
▪ A: Parallel connection
of RF and R1.
2.7.1. Frequency
Dependence
of the Open-Loop Gain
▪ The differential open-

loop gain of an op-amp
is not infinite.
▪ It is finite and
decreases with
frequency.
▪ It is high at dc, but falls
off quickly starting Figure 2.39: Open-loop gain of a
from 10Hz. typical general-purpose internally
compensated op amp.
2.7.1. Frequency
Dependence
▪ internal compensation – is the

presence of internal passive
components (caps) which cause
op-amp to demonstrate STC low-
pass response.
▪ frequency compensation – is the
process of modifying the open- Figure 2.39: Open-loop
loop gain. gain of a typical general-
purpose internally
▪ The goal is to increase
compensated op amp.
stability… Oxford University Publishing
2.7.1: Frequency
▪ The gain of an internally compensated op-amp may be
Dependence
expressed as shown below…
A0
transfer function in Laplace domain: A(s) =
1 + s / wb
A0
transfer function in frequency domain: A( jw ) =
1 + jw / wb
A0wb
transfer function for high frequencies: A( jw ) 
jw
wb is break frequency
A0wb wt
magnitude gain for high frequencies: A( jw)  
jw w
unity gain occurs at wt :
wt = A0wb
2.7.2. Frequency Response
of
Closed-Loop Amplifiers VOut −R2 / R1
=
VIn 1 + (1 + R2 / R1 )/ (A)
open
loop
gain
VOut −R2 / R1 −R2 / R1

▪ Q: How can we create a more = =
VIn 1 + 1 + R2 / R1  1 + R2 / R1 
accurate description of closed  A0 
1+  (1 + s / wb )
 A 
loop gain for an inverting-type   0
 1 + s / w0  action: split these terms

op-amp? A from two
slides back
▪ step #1: Define closed-loop VOut −R2 / R1

=
gain of an inverting amplifier VIn  1 + R2 / R1  s  1 + R2 / R1 
1+   +  
with finite open-loop gain (A)  A0  w b  A0 
▪ step #2: Insert frequency- action: replace with 0
because A0 1+R2 / R1
action: replace with...
dependent description of A VOut −R2 / R1

=
from last slide VIn s (1 + R2 / R1 )
1+
▪ step #3: Assume A0 >> 1 + wt
R2/R1 solution

2.7.2. Frequency
Response of
Closed-Loop Amplifiers
▪ Q: How can we create a more accurate description of

closed loop gain for an both inverting and non-
inverting type op-amps?
inverting op amp non-inverting op amp
VOut −R2 / R1 VOut 1 + R2 / R1

= =
VIn s (1 + R2 / R1 ) VIn s (1 + R2 / R1 )
1+ 1+
wt wt

2.7.2. Frequency
Response of
Closed-Loop Amplifiers
▪ 3dB frequency – is the

frequency at which the
amplifier gain is wt
w3dB =
attenuated 3dB from 1 + R2 / R1
maximum (aka. dc ) value.

2.8. Large-Signal
Operation of Op-
Amps
▪ 2.8.1. Output Voltage ▪ 2.8.2. Output Current

Saturation Limits
▪ If supply is +/- 15V, ▪ iOut current of op-amp,
then vOut will saturate including that which
around +/- 13V. facilitates feedback,
cannot exceed X.
▪ The book
approximates X at
20mA.
2.8.3. Slew Rate
▪ slew rate – is maximum

rate of change of an op-
amp (V/us) slew rate (SR)
▪ Q: How can this be dvOut

problematic? SR =
dt max
▪ A: If slew rate is less
than rate of change of
input.

2.8.3. Slew Rate
▪ Q: Why does slewing

occur?
▪ A: In short, the
bandwidth of the op-
amp is limited – so the
output at very high
frequencies is
attenuated…

2.8.4. Full-Power
Bandwidth
▪ Op-amp slewing will vIn = VIn sin (wt )

cause nonlinear distortion
of sinusoidal waveforms…
dvIn
▪ sine wave = w VIn cos (wt )
dt
▪ rate of change

2.8.4. Full-Power
Bandwidth
rated
▪ full-power bandwidth (fM) – the output
FP voltage
band. = A*vIn
maximum frequency at which amplitude SR = wM VOutMax
of a sinusoidal input and output are equal
▪ maximum output voltage (VOutMax) – is SR
fM =
equal to (A*vIn) 2 VOutMax
▪ note: an inverse relationship exists full-power bandwidth
between fM and VOutMax this value
▪ note: beyond wM, output may be

cannot be
greater
than one
defined in terms of w VOut

 wM 
= VOutMax  
 w 
relationship between
Oxford University Publishing actual output and maximum
Conclusion
▪ The IC op-amp is a versatile circuit building block. It is

easy to apply, and the performance of op-amp circuits
closely matches theoretical predictions.
▪ The op-amp terminals are the inverting terminal (1), the
non-inverting input terminal (2), the output terminal (3),
the positive-supply terminal (4) to be connected to the
positive power supply (VCC), and the negative-supply
terminal (5) to be connected to the negative supply (-
VEE).
Conclusion (2)
▪ The ideal op-amp responds only to the difference input

signal, that is (v2 - v1). It yields an output between
terminals 3 and ground of A(v2 - v1). The open-loop gain
(A) is assumed to be infinite. The input resistance (Rin) is
infinite. The output resistance (Rout) is assumed to be
zero.
▪ Negative feedback is applied to an op-amp by connecting
a passive component between its output terminal and its
inverting (aka. negative) input terminal.
Conclusion (3)
▪ Negative feedback causes the voltage between the two

input terminals to become very small, and ideally zero.
Correspondingly, a virtual short is said to exist between
the two input terminals. If the positive input terminal is
connected to ground, a virtual ground appears on the
negative terminal.

Conclusion (4)
▪ The two most important assumptions in the analysis of

op-amp circuits, assuming negative feedback exists, are:
▪ the two input terminals of the op-amp are at the
same voltage potential.
▪ zero current flows into the op-amp input terminals.
▪ With negative feedback applied and the loop closed, the
gain is almost entirely determined by external
components: Vo/Vi = -R2/R1 or 1+R2/R1.

Conclusion (5)
▪ The non-inverting closed-loop

configuration features a very high input
resistance. A special case is the unity-
gain follower, frequently employed as a
buffer amplifier to connect a high-
resistance source to a low-resistance
load. Figure 2.16
▪ The difference amplifier of Figure 2.16
is designed with R4/R3 = R2/R1, resulting
in vo = (R2/R1)(vI2 - vI1).
Conclusion (6)
▪ The instrumentation amplifier of Figure

2.20(b) is a very popular circuit. It
provides vo = (1+R2/R1)(R4/R3)(vI2 - vI1).
It is usually designed with R3 = R4 and
R1 and R2 selected to provide the
required gain. If an adjustable gain is
needed, part of R1 can be made Figure 2.20(b)
variable.

Conclusion (7)
▪ The inverting Miller Amplifier of Figure

2.24 is a popular circuit, frequently
employed in analog signal-processing
functions such as filters (Chapter 16)
and oscillators (Chapter 17).
▪ The input offset voltage (VOS) is the
magnitude of dc voltage that when Figure 2.24
applied between the op-amp input
terminals, with appropriate polarity,
reduces the dc offset at the output.
Chapter #3:
Semiconductors
by Sedra and Smith
Oxford Publishing
Introduction
▪ IN THIS CHAPTER WE WILL LEARN:

▪ The basic properties of semiconductors and, in
particular, silicone – the material used to make
most modern electronic circuits.
▪ How doping a pure silicon crystal dramatically
changes its electrical conductivity – the
fundamental idea in underlying the use of
semiconductors in the implementation of
electronic devices.
Introduction
▪ IN THIS CHAPTER WE WILL LEARN:

▪ The two mechanisms by which current flows in
semiconductors – drift and diffusion charge
carriers.
▪ The structure and operation of the pn junction – a
basic semiconductor structure that implements
the diode and plays a dominant role in
semiconductors.

3.1. Intrinsic
Semiconductors
▪ semiconductor – a material whose conductivity lies

between that of conductors (copper) and insulators
(glass).
▪ single-element – such as germanium and silicon.
▪ compound – such as gallium-arsenide.

3.1. Intrinsic
Semiconductors
▪ valence electron – is an electron that participates in the

formation of chemical bonds.
▪ Atoms with one or two valence electrons more than a
closed shell are highly reactive because the extra
electrons are easily removed to form positive ions.
▪ covalent bond – is a form of chemical bond in which two
atoms share a pair of atoms.
▪ It is a stable balance of attractive and repulsive forces
between atoms when they share electrons.
3.1. Intrinsic
Semiconductors
▪ silicon atom
▪ four valence electrons
▪ requires four more to
complete outermost
shell
▪ each pair of shared
forms a covalent bond
Figure 3.1 Two-dimensional representation of the silicon crystal. The
▪ the atoms form a circles represent the inner core of silicon atoms, with +4 indicating
its positive charge of +4q, which is neutralized by the charge of the
lattice structure four valence electrons. Observe how the covalent bonds are formed
by sharing of the valence electrons. At 0K, all bonds are intact and
Oxford University Publishing no free electrons are available for current conduction.
3.1.ofIntrinsic
The process freeing electrons, creating holes, and filling them
Semiconductorsfacilitates current flow…
▪ silicon at low temps

▪ all covalent bonds – are intact
▪ no electrons – are available for conduction
▪ conducitivity – is zero
▪ silicon at room temp
▪ some covalent bonds – break, freeing an electron and creating
hole, due to thermal energy
▪ some electrons – will wander from their parent atoms,
becoming available for conduction
▪ conductivity – is greater than zero
Figure 3.2: At room temperature, some of the covalent bonds are
3.1: Intrinsic
broken by thermal generation. Each broken bond gives rise to a free
Semiconductors
electron and a hole, both of which become available for current
conduction.
▪ silicon at low temps: ▪ silicon at room temp:

▪ all covalent bonds are intact ▪ sufficient thermal energy exists
▪ no electrons are available for to break some covalent bonds,
conduction freeing an electron and creating
▪ conducitivity is zero hole
▪ a free electron may wander
the process of freeing electrons, creating
from its parent atomholes,
and filling them facilitates current flow ▪ a hole will attract neighboring
electrons

3.1. Intrinsic
Semiconductors
▪ intrinsic semiconductor – is one which is not doped

▪ One example is pure silicon.
▪ generation – is the process of free electrons and holes
being created.
▪ generation rate – is speed with which this occurs.
▪ recombination – is the process of free electrons and
holes disappearing.
▪ recombination
Generation may be rate – is speed
effected with which
by thermal thisAsoccurs.
energy. such,
both generation and recombination rates will be (at least in
part) a function of temperature.
3.1. Intrinsic
Semiconductors
▪ thermal generation – effects a equal concentration of

free electrons and holes.
▪ Therefore, electrons move randomly throughout the
material.
▪ In thermal equilibrium, generation and recombination
rates are equal.

3.1. Intrinsic
Semiconductors
▪ In thermal equilibrium, the behavior below applies…

▪ ni = number of free electrons and holes / unit volume
▪ p = number of holes
▪ n = number of free electrons
3 / 2 − Eg / 2 kT
(eq3.1) ni = BT e
equal to p and n

3.1. Intrinsic
Semiconductors
▪ ni = number of free electrons and holes in a unit volume

for intrinsic semiconductor
▪ B = parameter which is 7.3E15 cm-3K-3/2 for silicon
▪ T = temperature (K)
▪ Eg = bandgap energy which is 1.12eV for silicon
▪ k = Boltzman constant (8.62E-5 eV/K)
3 / 2 − Eg / 2 kT
(eq3.1) ni = BT e
equal to p and n
Example 3.1
▪ Refer to book…

3.1. Intrinsic
Semiconductors
▪ Q: Why can thermal generation not be used to effect

meaningful current conduction?
▪ A: Silicon crystal structure described previously is not
sufficiently conductive at room temperature.
▪ Additionally, a dependence on temperature is not
desirable.
▪ Q: How can this “problem” be fixed?
doping – is the intentional introduction of impurities into
▪ A: doping
an extremely pure (intrinsic) semiconductor for the
purpose changing carrier concentrations.
3.2. Doped
Semiconductors
▪ p-type semiconductor ▪ n-type semiconductor

▪ Silicon is doped with ▪ Silicon is doped with
element having a element having a
valence of 3. valence of 5.
▪ To increase the ▪ To increase the
concentration of holes concentration of free
(p). electrons (n).
▪ One example is boron, ▪ One example is
which is an acceptor. phosophorus, which is
a donor.
3.2. Doped
Semiconductors

▪ Silicon is doped with ▪ Silicon is doped with
element having a element having a
valence of 3. valence of 5.
▪ To increase the ▪ To increase the
concentration of holes concentration of free
(p). electrons (n).
▪ One example is boron. ▪ One example is
phosophorus, which is
a donor.
3.2. Doped
Semiconductors
▪ p-type doped semiconductor

▪ If NA is much greater than ni …
▪ concentration of acceptor atoms is NA
▪ Then the concentration of holes in the p-type is
defined as below.
they will be equal...
(eq3.6) (pp )  (NA )

number number
holes acceptor
in atoms
Oxford University Publishing p -type
3.2. Doped
Semiconductors
▪ n-type doped semiconductor

▪ If ND is much greater than ni …
▪ concentration of donor atoms is ND
▪ Then the concentration of electrons in the n-type is
defined as below.
they will be equal...
(eq3.4) (nn )  (ND )

The key here is thatnumber
number of
number
free electrons (aka.
conductivity) is dependentfree ondonor
e-trons
doping concentration, not
atoms
temperature…
in n -type
3.2. Doped
Semiconductors
▪ p-type semiconductor action: combine this with equation

on previous slide
▪ Q: How can one find pp  np = ni2

the concentration? number number number
of holes of free of free
▪ A: Use the formula in p -type electrons electrons
in p -type and holes
to right, adapted for in thermal
equil.
the p-type
semiconductor. ni2
(eq3.7) np 
nA

3.2. Doped
Semiconductors
▪ n-type semiconductor action: combine this with equation

on previous slide
▪ Q: How can one find pn  nn = ni2

the concentration? number number number
of holes of free of free
▪ A: Use the formula in n-type electrons electrons
in n-type and holes
to right, adapted for in thermal
equil.
the n-type
semiconductor. ni2
(eq3.5) pn 
nD

3.2. Doped
Semiconductors

▪ np will have the same ▪ pn will have the same
dependence on dependence on
temperature as ni2 temperature as ni2
▪ the concentration of holes ▪ the concentration of free
(pp) will be much larger electrons (nn) will be much
than electrons larger than holes
▪ holes are the majority ▪ electrons are the majority
charge carriers charge carriers
▪ free electrons are the ▪ holes are the minority
minority charge carrier
charge carrier
Example 3.2: Doped
Semiconductor
▪ Consider an n-type silicon for which the dopant

concentration is ND = 1017/cm3. Find the electron and
hole concentrations at T = 300K.

3.3.1. Drift Current
▪ Q: What happens when an electrical field (E) is applied

to a semiconductor crystal?
▪ A: Holes are accelerated in the direction of E, free
electrons are repelled.
▪ Q: How is the velocity of these holes defined?
p =hole mobilityPpp n =electron mobilityPpp
E =electric fieldPpp E =electric fieldPpp
(eq3.8) v p−drift =  pE (eq3.9) vn−drift = − nE

note that electrons move with velocity 2.5 times higher
than holes
▪ Q: What happens
.E (volts / cm) when an electrical field (E) is applied
▪ A:.Holes
p (cm 2are
/Vs)accelerated
= 480 for silicon
in the direction of E, free
electrons are repelled.
.n (cm
▪ Q: How
2/Vs) = 1350 for silicon
is the velocity of these holes defined?
p =hole mobilityPpp n =electron mobilityPpp
E =electric fieldPpp E =electric fieldPpp
(eq3.8) v p−drift =  pE (eq3.9) vn−drift = − nE

Figure 3.5: An electric field E established in a bar of silicon causes
3.3.1.
the holes Drift
to drift Current
in the direction of E and the free electrons to drift
in the opposite direction. Both the hole and electron drift currents
are in the direction of E.
▪ Q: What happens when an electrical field (E) is applied

▪ A: Holes are accelerated in the direction of E, free
electrons are repelled. HOLES
▪ Q: How is the velocity of these holes defined?
ELECTRONS
p =hole mobility n =electron mobility
E =electric field E =electric field
v p−drift = p E vn−drift = − nE

▪ Assume that, for the single-crystal silicon bar on

previous slide, the concentration of holes is defined as p
and electrons as n.
▪ Q: What is the current component attributed to the flow
of holes (not electrons)?

PART A: What is the current
3.3.1. Drift Current component attributed to the

flow of holes (not electrons)?
▪ step #1: Consider a plane Ip = current flow attributed to holes

A= cross-sectional area of siliconp
perpendicular to the x q = magnitude of the electron chargep
p= concentration of holesp
direction. v p−drift = drift velocity of holesp
▪ step #2: Define the hole (eq3.10) Ip = Aqpv p−drift

charge that crosses this
plane.

PART A: What is the current
3.3.1. Drift Current component attributed to the

flow of holes (not electrons)?
▪ step #3: Substitute in pE. Ip = current flow attributed to holes

q = magnitude of the electron chargep
▪ step #4: Define current p= concentration of holesp
 p = hole mobilityp
density as Jp = Ip / A. E = electric field
Ip = Aqp p E
(eq3.11) Jp = qpp E
solution

In = current flow attributed to electrons

q = magnitude of the electron chargep
▪ Q: What is the current n= concentration of free electronsp
n = electron mobilityp
component attributed to E = electric field
the flow of electrons (not
In = − Aqvn−drift
holes)?
▪ A: to the right…
▪ Q: How is total drift (eq3.12) Jn = qnn E
current defined?
▪ A: to the right… (eq3.13) J = Jp + Jn = q(p p + nn ) E
this is conductivity ( )
▪ conductivity (.) – relates Ohm's Law

1
current density (J) and (eq3.14) J =  E
q(p p + nn )
electrical field (E)
▪ resistivity (r.) – relates (eq3.16)  = q(p p + nn )
current density (J) and q( p
electrical field (E) 1
(eq3.15) J = E / r
q(p p + nn
1
(eq3.17) r =
q(p p + nn )
Example 3.3: Doped
Semiconductors
▪ Q(a): Find the resistivity of intrinsic silicon using

following values – n = 1350cm2/Vs, p = 480cm2/Vs, ni =
1.5E10/cm3.
▪ Q(b): Find the resistivity of p-type silicon with NA =
1016/cm2 and using the following values – n =
1110cm2/Vs, p = 400cm2/Vs, ni = 1.5E10/cm3
note that doping reduces carrier mobility

Note…
▪ for intrinsic semiconductor – number of free electrons is

ni and number of holes is pi
▪ for p-type doped semiconductor – number of free
electrons is np and number of holes is pp
▪ for n-type doped semiconductor – number of free
electrons is nn and number of holes is pn
▪ What are p and n?
▪ generic descriptions of free electrons and holes
majority charge carriers
minority charge carriers
3.3.2. Diffusion
Current
▪ carrier diffusion – is the flow of charge carriers from

area of high concentration to low concentration.
▪ It requires non-uniform distribution of carriers.
▪ diffusion current – is the current flow that results from
diffusion.

Figure 3.6: A bar of silicon (a) into which holes are injected, thus
3.3.2. Diffusion creating the hole concentration profile along the x axis, shown in
(b). The holes diffuse in the positive direction of x and give rise to a
Current hole-diffusion current in the same direction. Note that we are not
showing the circuit to which the silicon bar is connected.
▪ Take the following example… inject

▪ inject holes – By some diffusion occurs
holes
unspecified process, one injects
holes in to the left side of a
silicon bar.
▪ concentration profile arises –
Because of this continuous hole
inject, a concentration profile
arises.
concentration
▪ diffusion occurs – Because of
profile arises
this concentration gradient,
holes will flow from left to right.

3.3.2. Diffusion
Current
▪ Q: How is diffusion current defined?

Jp = current flow density attributed to holesJpp
q = magnitude of the electron chargeJpp
Dp = diffusion constant of holes (12cm2 /s for silicon)Jpp
p ( x )= hole concentration at point xJpp
dp / dx = gradient of hole concentrationJpp
dp(x)
(eq3.19) hole diffusion current density : Jp = −qDp
dx
dn(x)
(eq3.20) electron diffusion current density : Jn = −qDn
dx
Jn = current flow density attributed to free electronsJpp
Dn = diffusion constant of electrons (35cm2 /s for silicon)Jpp
n( x )= free electron concentration at point xJpp
dn / dxC.=Smith
Microelectronic Circuits by Adel S. Sedra and Kenneth gradient of free electron concentrationJpp
(0195323033)
Example 3.4:
Diffusion
▪ Consider a bar of silicon in which a hole concentration

p(x) described below is established.
▪ Q(a): Find the hole-current density Jp at x = 0.
▪ Q(b): Find current Ip.
▪ Note the following parameters: p0 = 1016/cm3, Lp =
1m, A = 100m2
− x / Lp
p(x) = p0 e

3.3.3. Relationship
Between D and .?
▪ Q: What is the
the relationship between diffusion constant
relationship between and mobility is defined by thermal voltage
diffusion constant (D) and Dn Dp
mobility ()? (eq3.21) = = VT
n p
▪ A: thermal voltage (VT)
▪ Q: What is this value? known as Einstein
▪ A: at T = 300K, VT = Relationship
25.9mV

▪ drift3.3.3.
currentRelationship
density (Jdrift)
▪ effected by – an electric field (E).
Between D and .?
▪ diffusion current density (Jdiff)
▪ effected by – concentration gradient in free electrons and
holes.
▪ Q: What is the
relationship between the relationship between diffusion constant
and mobility is defined by thermal voltage
A= cross-sectional area of silicon, q = magnitude of the electron charge,J p
Dn Dpp
diffusion constant (D)
p= concentration and
of holes,
(eq3.21) p =
n= concentration of free electrons,Jpn  p
= VT
 = hole mobility,  = electron mobility, E = electric fieldJp
mobility ()? p n p
drift current density : Jdrift = Jp−drift + Jn−drift = q(p p + nn )E

▪ A: thermal voltage (VT)
dp(x) dn(x)
▪ Q: What
diffusion curre isntthis
density
value? : Jdiff = Jp−diff + Jn−diff = −qDp − qDn
known as dx Einstein dx
D▪ pA: atconstant
= diffusion T = of300K,
holes (12cmV/Ts for= silicon), D = diffusion constantRelationship
2
n of electrons (35cm /s for silicon),J 2 p
p
p ( x )= hole concentration at point x , n( x )= free electron concentration at point x ,J p
25.9mVdp / dx = gradient of hole concentration, dn / dx= gradient of free electron concentrationJ

p
p
p

Figure 3.8: Simplified physical
3.4.1. Physical structure of the pn junction.
Structure (Actual geometries are given in
Appendix A.) As the pn junction
implements the junction diode,
▪ pn junction structure its terminals are labeled anode
and cathode.
▪ p-type semiconductor
▪ n-type semiconductor
▪ metal contact for connection

3.4.2. Operation with
Open-Circuit Terminals
▪ Q: What is state of pn junction with open-circuit

terminals?
▪ A: Read the below…
▪ p-type material contains majority of holes
▪ these holes are neutralized by equal amount of
bound negative charge
▪ n-type material contains majority of free electrons
▪ these electrons are neutralized by equal amount of
bound positive charge
3.4.2. Operation
with Open-Circuit
Terminals
▪ bound charge
▪ charge of opposite polarity to free electrons / holes of
a given material
▪ neutralizes the electrical charge of these majority
carriers
▪ does not affect concentration gradients

3.4.2. Operation
with Open-Circuit
Terminals
▪ Q: What happens when a pn-junction is newly formed –

aka. when the p-type and n-type semiconductors first
touch one another?
▪ A: See following slides…

Step #1: The p-type and n-type semiconductors are
joined at the junction.
p-type semiconductor n-type semiconductor

junction
filled with holes filled with free electrons
Figure: The pn junction with no applied voltage (open-circuited

terminals).
Step #1A: Bound charges are attracted (from environment) by
free electrons and holes in the p-type and n-type
semiconductors, respectively. They remain weakly “bound” to
these majority carriers; however, they do not recombine.
negative bound positive bound

charges charges

terminals).
Step #2: Diffusion begins. Those free electrons and holes
which are closest to the junction will recombine and,
essentially, eliminate one another.

terminals).
Step #3: The depletion region begins to form – as diffusion
occurs and free electrons recombine with holes.
The depletion region is filled with “uncovered” bound charges – who

have lost the majority carriers to which they were linked.

terminals).
3.4.2. Operation
with Open-Circuit
Terminals
▪ Q: Why does diffusion occur even when bound charges

neutralize the electrical attraction of majority carriers to
one another?
▪ A: Diffusion current, as shown in (3.19) and (3.20), is
effected by a gradient in concentration of majority
carriers – not an electrical attraction of these particles
to one another.

Step #4: The “uncovered” bound charges effect a voltage
differential across the depletion region. The magnitude of this
barrier voltage (V0) differential grows, as diffusion continues.
No voltage differential exists across regions of the pn-junction

outside of the depletion region because of the neutralizing effect of
positive and negative bound charges.
voltage potential
barrier voltage
(Vo)
location (x)

Step #5: The barrier voltage (V0) is an electric field whose
polarity opposes the direction of diffusion current (ID). As the
magnitude of V0 increases, the magnitude of ID decreases.
diffusion current drift current

(ID) (IS)

terminals).
Step #6: Equilibrium is reached, and diffusion ceases, once the
magnitudes of diffusion and drift currents equal one another –
resulting in no net flow.
Once equilibrium is achieved,

diffusion no netdrift
current current current
flow exists (Inet = ID – IS)
within the pn-junction
(I ) while under open-circuit
(I ) condition.
D S
p-type depletion n-type

region

3.4.2. Operation
with Open-Circuit
Terminals
▪ pn-junction built-in voltage (V0) – is

the equilibrium value of barrier V0 = barrier voltage
VT = thermal voltage
voltage. NA = acceptor doping concentration
ND = donor doping concentration
▪ It is defined to the right. ni = concentration of free electrons...
...in intrinsic semiconductor
▪ Generally, it takes on a value
 NA ND 
between 0.6 and 0.9V for silicon (eq3.22) V0 = VT ln  2 
at room temperature.  ni 
▪ This voltage is applied across
depletion region, not terminals of
pn junction.
▪ Power cannot be drawn from V0.
The Drift Current IS
and Equilibrium
▪ In addition to majority-carrier diffusion current (ID), a

component of current due to minority carrier drift exists
(IS).
▪ Specifically, some of the thermally generated holes in the
p-type and n-type materials move toward and reach the
edge of the depletion region.
▪ There, they experience the electric field (V0) in the
depletion region and are swept across it.
▪ Unlike diffusion current, the polarity of V0 reinforces
this drift current.Oxford University Publishing
3.4.2. Operation
with Open-Circuit
Terminals
▪ Because these holes are free electrons are produced by

thermal energy, IS is heavily dependent on temperature
▪ Any depletion-layer voltage, regardless of how small, will
cause the transition across junction. Therefore IS is
independent of V0.
▪ drift current (IS) – is the movement of these minority
carriers.
▪ aka. electrons from n-side to p-side of the junction

Note that the magnitude of drift current (IS) is
unaffected by level of diffusion and / or V0. It will be,
however, affected by temperature.
diffusion current drift current

(ID) (IS)

terminals).
3.4.2. Operation
with Open-Circuit
Terminals
▪ Q: Is the depletion region always symmetrical? As

shown on previous slides?
▪ A: The short answer is no.
▪ Q: Why?
▪ Typically NA > ND
▪ And, because concentration of doping agents (NA, ND)
is unequal, the width of depletion region will differ
from side to side.

3.4.2. Operation
with Open-Circuit
Terminals
▪ Q: Why?
▪ A: Because, typically NA > ND.
▪ When the concentration of doping agents (NA, ND)
is unequal, the width of depletion region will differ
from side to side.
▪ The depletion region will extend deeper in to the
“less doped” material, a requirement to uncover
the same amount of charge.
▪ xp = width of depletion p-region
▪Oxford
xnUniversity
= width Publishingof depletion n-region
3.4.2. Operation
with Open-Circuit
Terminals
The depletion region will extend further in to region with “less”
doping. However, the “number” of uncovered charges is the same.

3.4.2: Operation with
Open-Circuit Terminals
▪ Width of and Charge Stored in ▪ because concentration of

the Depletion Region doping charge
agentsis (N
equal, but
A, ND) is
▪ the question we ask here unequal,width
the is different
width of
is, what happens once the depletion region will differ
open-circuit pn junction from side to side
reaches equilibrium??? ▪ the depletion region will
dv/dx
▪ typically is dependent NA > ND of extend deeper in to the
▪ minority Q/W carrier “less doped” material, a
concentrations at requirement to uncover
equilibrium (no voltage the same amount of
applied) are denoted by charge
np0Circuits
Microelectronic and Oxford University Publishing
pS.n0Sedra and Kenneth C. Smith (0195323033)
by Adel
▪ xp = width of depletion
3.4.2. Operation
with Open-Circuit
Terminals
Q + = magnitude of charghe on n -side of junctionPpp
q = magnitude of electric chargePpp
A= cross-sectional area of junctionPpp
▪ Q: How is the charge xn = penetration of depletion region into n -sidePpp
stored in both sides of ND = concentration of donor atomsPpp
the depletion region (eq3.23) Q + = qAxn ND

defined?
▪ A: Refer to equations
to right. Note that (eq3.24) Q - = qAx p NA
these values should Q - = magnitude of charghe on n -side of junctionPpp
q = magnitude of electric chargePpp
equal one another. A= cross-sectional area of junctionPpp
x p = penetration of depletion region into p -sidePpp
NA = concentration of acceptor atomsPpp
3.4.2. Operation
with Open-Circuit
Terminals
▪ Q: What information can be derived from this equality?

▪ A: In reality, the depletion region exists almost
entirely on one side of the pn-junction – due to great
disparity between NA > ND.
x n NA
qAx pNA = qAxnND → (eq3.25) =
xp ND

3.4.2. Operation
with Open-Circuit
Terminals W = width of depletion regionP
 = electrical permiability of silicon (11.7 =1.04 E−12F / cm )P
S 0
p
p
p
p
q = magnitude of electron chargePpp
▪ Note that both xp and ND = concentration of donor atomsPpp
V0 = barrier / junction built-in voltagePpp
xn may be defined in
terms of the depletion 2 S  1 1 
region width (W). (eq3.26) W = xn + x p =  + V0
q  NA ND 
NA
(eq3.27) xn = W
NA + ND
ND
(eq3.28) x p = W
NA + ND
3.4.2. Operation
with Open-Circuit
Terminals
▪ Note, also, the charge on either side of the depletion

region may be calculated via (3.29) and (3.30).
 NA ND 
(eq3.29) QJ = Q  = Aq  W
 NA + ND 
 NA ND 
(eq3.30) QJ = A 2 S q  V0
 NA + ND 

Example 3.5
▪ Refer to book…

3.4.2. Operation
with Open-Circuit
Terminals
▪ Q: What has been learned about the pn-junction?

▪ A: composition
▪ The pn junction is composed of two silicon-based
semiconductors, one doped to be p-type and the
other n-type.
▪ A: majority carriers
▪ Are generated by doping.
▪ Holes are present on p-side, free electrons are
present on n-side.
3.4.2. Operation
with Open-Circuit
Terminals

▪ A: bound charges
▪ Charge of majority carriers are neutralized
electrically by bound charges.
▪ A: diffusion current ID
▪ Those majority carriers close to the junction will
diffuse across, resulting in their elimination.

3.4.2. Operation
with Open-Circuit
Terminals

▪ A: depletion region
▪ As these carriers disappear, they release bound
charges and effect a voltage differential V0.
▪ A: depletion-layer voltage
▪ As diffusion continues, the depletion layer voltage
(V0) grows, making diffusion more difficult and
eventually bringing it to halt.

3.4.2. Operation
with Open-Circuit
Terminals

▪ A: minority carriers
▪ Are generated thermally.
▪ Free electrons are present on p-side, holes are
present on n-side.
▪ A: drift current IS
▪ The depletion-layer voltage (V0) facilitates the flow
of minority carriers to opposite side.
▪ A: open circuit equilibrium ID = IS
3.5.1. Qualitative
Description of
Junction Operation
▪ Figure to right shows pn-

junction under three
conditions:
▪ (a) open-circuit – where a
barrier voltage V0 exists.
▪ (b) reverse bias – where a
dc voltage VR is applied. Figure 3.11: The pn junction in:
▪ (c) forward bias – where a (a) equilibrium; (b) reverse bias;
dc voltage VF is applied. (c) forward bias.

1) no voltage 1) negative voltage 1) positive voltage
applied applied applied
2) voltage differential 2) voltage differential 2) voltage differential
across depletion zone across depletion zone across depletion zone
is V0 is V0 + VR is V0 - VF
▪ 3)Figure
ID = IS to right shows pn-
3) ID < IS 3) ID > IS
junction under three
conditions:
▪ (a) open-circuit – where a
barrier voltage V0 exists.
▪ (b) reverse bias – where a
dc voltage VR is applied. Figure 3.11: The pn junction in:
▪ (c) forward bias – where a (a) equilibrium; (b) reverse bias;
dc voltage VF is applied. (c) forward bias.

3.5.1. Qualitative
Description of
Junction Operation
▪ reverse bias case ▪ forward bias case

▪ the externally applied voltage VR ▪ the externally applied voltage VF
adds to (aka. reinforces) the subtracts from the barrier
barrier voltage V0 voltage V0
▪ …increase effective barrier ▪ …decrease effective barrier
▪ this reduces rate of diffusion, ▪ this increases rate of diffusion,
reducing ID increasing ID
▪ if VR > 1V, ID will fall to 0A ▪ k
▪ the drift current IS is unaffected, ▪ the drift current IS is unaffected,
but dependent on temperature but dependent on temperature
▪ result is that pn junction will ▪ result is that pn junction will
conduct current
minimal small driftflows
currentin IS conduct significant
significant current current ID - IS
flows in
reverse-bias case
Oxford University Publishing forward-bias case
Forward-Bias Case
W = width of depletion regionPpp
 S = electrical permiability of silicon (11.7 0 =1.04 E−12 F / cm)Ppp
▪ Observe that decreased ND = concentration of donor atomsPpp
barrier voltage will be VF = externally applied forward-bias voltagePpp
accompanied by…
2 S  1 1 
▪ (1) decrease in stored W = xn + x p =  +  (V0 − VF )
q  NA ND  action:
uncovered charge on both replace V0
with V0 −VF
sides of junction
▪ (2) smaller depletion
 NN 
region QJ = A 2 S q  A D  (V0 − VF )
 NA + ND  action:
▪ Width of depletion region replace V0
with V0 −VF
shown to right.
QJ = magnitude of charge stored on either side of depletion regionPpp

Reverse-Bias Case
W = width of depletion regionPpp
 S = electrical permiability of silicon (11.7 0 =1.04 E−12 F / cm)Ppp
▪ Observe that increased ND = concentration of donor atomsPpp
barrier voltage will be VR = externally applied reverse-bias voltagePpp
accompanied by…
2 S  1 1 
▪ (1) increase in (eq3.31) W = xn + x p =  +  (V0 + VR )
q  NA ND  action:
stored uncovered replace V0
with V0 +VR
charge on both sides
of junction
 NA ND 
▪ (2) wider depletion (eq3.32) QJ = A 2 S q   (V0 + VR )
region  NA + ND  action:
replace V0
with V0 +VR
▪ Width of depletion
QJ = magnitude of charge stored on either side of depletion regionPpp
region shown to right.
3.5.2. The Current-
Voltage Relationship
of the Junction
▪ Q: What happens, exactly, when a forward-bias voltage

(VF) is applied to the pn-junction?
▪ step #1: Initially, a small forward-bias voltage (VF) is
applied. It, because of its polarity, pushes majority
carriers (holes in p-region and electrons in n-region)
toward the junction and reduces width of the
depletion zone.
▪ Note, however, that this force is opposed by the
built-in voltage built in voltage V0.

step #1: Initially, a small forward-bias voltage (VF) is applied. It,
Note that, in
because ofthis figure, the
its polarity, smaller
pushes circles(holes
majority represent minority
in p-region and
carriers and not
electrons bound charges
in n-region) toward–the
which are not
junction considered
and here.of
reduces width
the depletion zone.
VF
Figure: The pn junction with applied voltage.

step #2: As the magnitude of VF increases, the depletion zone
becomes thin enough such that the barrier voltage (V0 – VF)
cannot stop diffusion current – as described in previous slides.
VF
Note that removing barrier voltage does not facilitate diffusion, it

only removes the electromotive force which opposes it.

step #3: Majority carriers (free electrons in n-region and holes
in p-region) cross the junction and become minority charge
carriers in the near-neutral region.
VF
diffusion drift
current (ID) current (IS)

step #4: The concentration of minority charge carriers
increases on either side of the junction. A steady-state
gradient is reached as rate of majority carriers crossing the
For the open-circuit condition, minority carriers are evenly
junction equals that of recombination.
distributed throughout the non-depletion regions. This
concentration is defined asVeither
F np0 or pn0.
minority carrier
concentration
location (x)

step #4: The concentration of minority charge carriers
increases on either side of the junction. A steady-state
gradient is reached as rate of majority carriers crossing the
junction equals that of recombination.
VF
minority carrier
concentration
location (x)
terminals).
step #5+: Diffusion current is maintained – in spite low
diffusion lengths (e.g. microns) and recombination – by
constant flow of both free electrons and holes towards the
junction.
recombination
VF
flow of diffusion current (ID)
flow of holes flow of electrons

terminals).
3.5.2.
The key aspectThe Current-
of (3.33) is that it relates the minority-charge carrier
VoltageatRelationship
concentration the junction boundary in terms of majority-charge
carrier on the opposite side.
of the Junction
ni2
(eq3.7) pn 0 =
NA
▪ Q: How is the relationship
between forward-bias voltage
pn ( xn ) = concentration of holes in n -region as function of xn Ppp
applied (V.) and minority- pn 0 = thermal equilibrium concentrationPpp
carrier holes and electrons V = applied foward-bias voltagePpp
VT = thermal voltagePpp
defined?
▪ step #1: Employ (3.33). (eq3.33) pn (xn ) = pn 0 eV / VT
▪ This function describes
maximum minority carrier excess
concentration at junction. (eq3.34) = pn 0 eV / VT − pn 0
concentration
▪ step #2: Subtract pn0 from excess
pn(x) to calculate the excess (eq3.34) = pn 0 (eV / VT − 1)
concentration
minority charge carriers.
3.5.2. The Current-
of the Junction
▪ Q: How is the relationship between forward-bias voltage applied

(V.) and minority-carrier holes and electrons defined?
▪ step #3: Refer to (3.35).
▪ This function describes the minority carrier concentration
as a function of location (x), boundary of depletion region
(xn), and diffusion length (Lp).
pn ( xn ) = concentration of holes in n -region as function of xn , pn 0 = thermal equilibrium concentration
x = point of interest, xn = edge of depletion region, LP = diffusion length
− ( x − xn ) / Lp
(eq3.35) pn (xn ) = pn 0 + (excess concentration) e
pn 0 ( eV / VT −1)
− ( x − xn ) / Lp
(eq3.35) p ( x ) =
n Publishing
Oxford University n pn0 + pn0 (eV / VT
− 1)e
3.5.2: The Current-Voltage
steady-state minority carrier concentration on both
Relationship of the
sides of a pn-junction for which NA >> ND
Junction
“base” excess
concentration concentration

3.5.2: The Current-Voltage
These excess concentrations
Relationship of the effect steady-state diffusion
current.Junction
However, how is this diffusion current
defined?

3.5.2. The Current-
Voltage Relationship action: take derivative of pn ( x )
dp n ( x ) d
of the Junction =  pn 0  +
dx dx
0
d
▪ Q: For forward-biased +  pn 0 (eV / VT − 1)e −( x −xn ) / Lp 
dx  
case, how is diffusion −
pn 0 V / VT
(e −1) e
− ( x − xn ) / Lp
current (ID) defined? Lp

action: substitute in value from above
▪ step #1: Take  pn 0 V / VT 
−( x−x ) / L
derivative of (3.35) to (eq3.36) Jp = −qDp  − (e − 1)e n p 
 L
define component of  p 
dpn ( x )
diffusion current dx
attributed to flow of
holes. action: calculate maximum
Dp
▪ step #2: Note that this max( Jp ) = q pn 0 (eV / VT − 1)
value is maximum at x Lp
= xn. Oxford University Publishing
Q: For forward-biased case,
how is diffusion current
defined?
▪ step #3: Define the component of maximum diffusion

current attributed to minority-carrier electrons – in
method similar above.
(eq3.37) maximum hole - diffusion concentration:
Dp
Jp (+ xn ) = q pn 0 (eV / VT − 1)
Lp
(eq3.38) maximum electron - diffusion concentration:
Dn
Jn (− x p ) = q np 0 (eV / VT − 1)
Ln
Q: For forward-biased case,
how is diffusion current maximum
total current (I ) through junction is equal to area (A ) times
hole (Jp ) and electron-diffusion (Jn ) current densities
defined?
I = A  Jp (+ xn ) + Jn (− x p )
 Dp Dn  V / VT
▪ step #4: Define total I = A q pn 0 + q np 0  (e − 1)
 Lp Ln 
diffusion current as
action: subtitute in values
sum of components for Jp ( + xn ) and Jn (- x p )
attributed to free  Dp Dn  V / VT
I = Aqn  2
+  (e − 1)
electrons and holes. i
 Lp ND Ln NA 
action: subtitute
pn 0 =ni2/ ND and np 0 =ni2 / NA
I = IS (eV / VT − 1)
action: subtitute
 Dp D 
Is = Aqni2  + n 
 Lp ND Ln NA 
3.5.2. The Current-
of the Junction
▪ Q: For forward-biased case, how is diffusion current (ID)

defined?
▪ A: Refer to (3.40). This is an important equation
which will be employed in future chapters.
  Dp Dn   V / VT
(eq3.40) I =  Aqni 
2
+   (e − 1) = I (e V / VT
− 1)
  L N L N   S
  p D n A  
IS

3.5.2. The Current-
of the Junction
▪ Q: Why is diffusion current (ID) dependent on the

concentration gradient of minority (as opposed to
majority) charge carriers?
▪ A: Essentially, it isn’t.
▪ Equation (3.33) defines the minority-charge carrier
concentration in terms of the majority-charge carrier
concentrations in “other” region.
▪ As such, the diffusion current (ID) is most dependent on two
factors: applied forward-bias voltage (VF) and doping.

3.5.2. The Current-
of the Junction
(eq3.40) I = IS (e V / VT
− 1)
▪ saturation current (IS) – is

the maximum reverse
current which will flow
through pn-junction.
▪ It is proportional to
cross-section of
junction (A).
▪ Typical value is 10-18A. Figure 3.13: The pn junction I–V
characteristic.
Example 3.6: pn-
Junction
▪ Consider a forward-biased pn junction conducting a

current of I = 0.1mA with following parameters:
▪ NA = 1018/cm3, ND = 1016/cm3, A = 10-4cm2, ni =
1.5E10/cm3, Lp = 5um, Ln = 10um, Dp (n-region) =
10cm2/s, Dn (p-region) = 18cm2/s
▪ Q(a): Calculate IS .
▪ Q(b): Calculate the forward bias voltage (V).
▪ Q(c): Component of current I due to hole injection and
electron injection across the junction
Summary (1)
▪ Today’s microelectronics technology is almost entirely

based on the semiconductor silicon. If a circuit is to be
fabricated as a monolithic integrated circuit (IC), it is
made using a single silicon crystal, no matter how large
the circuit is.
▪ In a crystal of intrinsic or pure silicon, the atoms are held
in position by covalent bonds. At very low
temperatures, all the bonds are intact; No charge
carriers are available to conduct current. As such, at
these low temperatures, silicone acts as an insulator.
Summary (2)
▪ At room temperature, thermal energy causes some of

the covalent bonds to break, thus generating free
electrons and holes that become available to conduct
electricity.
▪ Current in semiconductors is carried by free electrons
and holes. Their numbers are equal and relatively small
in intrinsic silicon.
▪ The conductivity of silicon may be increased drastically
by introducing small amounts of appropriate impurity
materials into the silicon crystal – via process called
doping. Oxford University Publishing
Summary (3)
▪ There are two kinds of doped semiconductor: n-type in

which electrons are abundant, p-type in which holes are
abundant.
▪ There are two mechanisms for the transport of charge
carriers in a semiconductor: drift and diffusion.
▪ Carrier drift results when an electric field (E) is applied
across a piece of silicon. The electric field accelerates
the holes in the direction of E and electrons oppositely.
These two currents sum to produce drift current in the
direction of E. Oxford University Publishing
Summary (4)
▪ Carrier diffusion occurs when the concentration of

charge carriers is made higher in one part of a silicon
crystal than others. To establish a steady-state diffusion
current, a carrier concentration must be maintained in
the silicon crystal.
▪ A basic semiconductor structure is the pn-junction. It is
fabricated in a silicon crystal by creating a p-region in
proximity to an n-region. The pn-junction is a diode and
plays a dominant role in the structure and operation of
transistors. Oxford University Publishing
Summary (5)
▪ When the terminals of the pn-junction are left open, no

current flows externally. However, two equal and
opposite currents (ID and IS) flow across the junction.
Equilibrium is maintained by a built-in voltage (V0).
Note, however, that the voltage across an open junction
is 0V, since V0 is cancelled by potentials appearing at the
metal-to-semiconductor connection interfaces.
▪ The voltage V0 appears across the depletion region,
which extends on both sides of the junction.
Summary (6)
▪ The drift current IS is carried by thermally generated

minority electrons in the p-material that are swept
across the depletion region into the n-side. The
opposite occurs in the n-material. IS flows from n to p, in
the reverse direction of the junction. Its value is a strong
function of temperature, but independent of V0.
▪ Forward biasing of the pn-junction, that is applying an
external voltage that makes p more positive than n,
reduces the barrier voltage to V0 - V and results in an
exponential increase in ID (while IS remains unchanged).
Summary (7)
▪ The drift current IS is carried by thermally generated

minority electrons in the p-material that are swept
across the depletion region into the n-side. The
opposite occurs in the n-material. IS flows from n to p, in
the reverse direction of the junction. Its value is a strong
function of temperature, but independent of V0.
▪ Forward biasing of the pn-junction, that is applying an
external voltage that makes p more positive than n,
reduces the barrier voltage to V0 - V and results in an
exponential increase in ID (while IS remains unchanged).

Elo 1

Uploaded by

Copyright:

Available Formats

You might also like

Elo 1

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Elo 1

Uploaded by

Copyright:

Available Formats

Chapter #1: Signals and

▪ IN THIS CHAPTER YOU WILL LEARN…

Oxford University Publishing

▪ IN THIS CHAPTER YOU WILL LEARN…

Oxford University Publishing

▪ signal – contains information

▪ Q: How are signals represented?

Oxford University Publishing

Figure 1.1: Two alternative representations of a signal source: (a) the

▪ Consider two source / load combinations to upper-right.

Oxford University Publishing

▪ frequency spectrum – defines the a time-domain signal

Oxford University Publishing

▪ decomposition – of a periodic function into the

Fourier Series Representation of f( x)

▪ Q: How does one calculate Fourier Series of square

Oxford University Publishing

step #1: define ak for the square wave

Oxford University Publishing

step #2: define bk for the square wave if k is even

step #3: define Fourier Series

Figure 1.6: The frequency spectrum (also known as the

▪ Examine the sinusoidal wave below…

root mean square magnitude =

▪ Q: Can the Fourier Transform be applied to a non-

Oxford University Publishing

▪ analog signal – is continuous with respect to both value

Oxford University Publishing

Oxford University Publishing

Oxford University Publishing

▪ Q: Are digital and binary

▪ Q: Why is signal amplification needed?

Oxford University Publishing

▪ voltage amplifier – is used to boost voltage levels for

Oxford University Publishing

▪ Q: What is one main difference between an amplifier

load power (PL ) voio

Oxford University Publishing

▪ Q: How may gain be expressed in decibels?

voltage gain in decibels = 20 log Av dB

Oxford University Publishing

▪ supplies – an amplifier has two power supplies

Oxford University Publishing

▪ conservation of power – dictates that power input (Pi)

Oxford University Publishing

Figure 1.13: An amplifier that requires two dc supplies (shown as

▪ limited linear range – practically, amplifier operation is

Oxford University Publishing

▪ model – is the description of component’s (e.g.

Oxford University Publishing

model of amplifier input terminals model of amplifier output terminals

Oxford University Publishing

▪ Q: How can one model the amplifier behavior from

▪ Q: What is one “problem” with this behavior?

The ideal open-ckt

▪ ideal amplifier model – is function of vs and Avo only!!

key characteristics of ideal voltage amplifier model = high input

▪ ideal amplifier model – is function of vs and Avo only!!