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ES 18EC62 Module1 Notes
ES 18EC62 Module1 Notes
18 EC 6 2
32 - B I T M I C R O C O N T R O L L E R
Module-1
ARM-32 bit Microcontroller
About ARM
➢ Based on Client requirements ARM (ADVANCED RISC MACHINE) will lend its
architecture of Core + debug systems; the bus interface interfaces and peripherals are
designed by ARM in collaboration with semiconductor chip manufacturers.
➢ The phy sical ch ip manufactu rin g an d marketin g is done b y the Semiconducto r manufactu rers
who have licensed IP from ARM and can fbricate the Cortex-M3 processor in their silicon
designs, adding memory, peripherals, input/output (I/O), and other features.
➢ Cortex-M3 processor-based chips from different manufacturers will have different memory
sizes, types, peripherals, and features.
➢ Unlike many semiconductor companies, ARM does not manufacture processors or sell
the chips directly.
➢ Instead, ARM licenses the processor designs to business partners, including a majority
of the world’s leading semiconductor companies.
➢ Based on the ARM’s low-cost and power-efficient processor designs, these partners
create their processors, microcontro llers, and system-on-chip solutions. This business model
is commonly called Intellectual Property (IP) licensing.
➢ In addition to processor designs, ARM also licenses systems-level IP and various software
IPs.
➢ To support these products, ARM has developed a strong base of development tools,
hardware, and Software products to enable partners to develop their own products.
➢ The ARM Cortex™-M3 processor, the first of the Cortex generation of processors
released by ARM in 2006, was primarily designed to target the 32-bit microcontroller
market is the successor of earlier ARM7 variants.
➢ NXP (Philips), Texas Instruments, Atmel, OKI, and many other vendors delivering
robust 32-bit Microcon tro ller Units (MCUs) are the clients of ARM.
Important features of ARM architecture/ processors & controllers which use
ARM architecture
➢ Greater performance efficiency : Allowin g more work to be done without increasin g the
frequency or power requirements.
➢ Low power consumption: Enabling longer battery life, especially critical in portable
products including wireless networking applications.
➢ Enhanced determinism : Guaranteeing that critical tasks and interrupts are serviced as
quickly as possible and in a known number of cycles.
➢ Improved code density: Ensuring that code fits in even the smallest memory footprints.
➢ Ease of use : Pro v id in g easier p ro grammab ility and debu ggin g fo r th e gro win g nu mb er of
8-bit and 16-bit users migrating to 32 bits.
➢ Lower cost solutions: Reducing 32-bit-based system costs close to those of legacy 8-bit
and 16-bit devices and enabling low-end, 32-bit microcontrollers to be priced at less than
US$1 for the first time.
➢ Wide choice of development tools: From low-cost or free compilers to full-featured
development suites from many development tool vendors.
History of ARM
➢ ARM was fo rmed in 1990 as Adva nced RISC Machines Ltd., a jo int v enture o f Apple
Computer, Acorn Computer Group, and VLSI Technology.
➢ In 1991, ARM introduced the ARM6 processor family, and VLSI became the initial
licensee.
➢ Later on Texas Instruments, NEC, Sharp, and ST Microelectronics, licensed the
ARM processor designs, using ARM processors into mobile phones, computer hard
disks, personal digital assistants (PDAs), home entertainment systems, and many other
consumer products.
Architecture Versions
➢ Earlier different naming was done to different processor architectures. There were
different versions, family and numbering and suffixes. Ex: ARM_ family_numbered
suffix_other suffix;
➢ But from 5 th version onwards TDMI features (Thumb, JTAG, Fast Multipliers, ICE
module) were decided as basic requirements of ARM architecture and any additional
➢ Real-time, high-performan ce low latency processors targeted primarily at the higher end real-
time market
➢ Examples: high-end breaking system, Hard drive controllers, in which high processing
power, where high reliability are essential.
The M profile( Microcontroller)
➢ Processors for low-cost applications looking for processing efficiency, low cost, low
power consumption, low interrupt latency, and ease of use.
➢ Example: Industrial control applications, Real-time control systems.
Evolution of ARM architecture summarized below
1. It is Superset of both 32 bit ARM & 16-bit Thumb instruction set used in M3
and higher versions.
2. The switching b/w ARM & Thumb state isn’t required compared to earlier versions. Hence
overhead delay can be avoided.
3. Delivers significan t benefits in terms of ease of use, code size, and performance.
➢ Problem of Processor switching b/w ARM & Thumb mode in Lower versions like ARM7
produces over head delay is shown below.
In Thumb-2 this problem doesn’t exist at all as there is only one Superset Thumb-2 (IS).
Few power full instructions of Thumb-2 are:
➢ UFBX, BFI, and BFC: Bit field extract, insert, and clear instruction s
➢ UDIV and SDIV: Unsigned and signed divide instructions
➢ WFE, WFI, and SEV: Wait-For-Event, Wait-For-Interrupts, and Send-Event; these allow the
processor to enter sleep mode and to handle task synchronization on multipro cesso r systems.
➢ MSR and MRS: Move to special register from general-purpose register and move special
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32 - B I T M I C R O C O N T R O L L E R
thumb-2 IS only.
Privilege Level
➢ When we compare the two opertions, it can be see that after completion of handler the
processor returns to level if there is no change in CR
➢ The MPU blocks the user programs from corrupting memory reserved for Privileged threads
along with CR of NVIC during user program crashes.
➢ When the processor is running a main program (thread mode), it can be either in a privileged
state or a user state.
➢ But the exception handlers should be always in a privileged state.
➢ When the processor exits reset, it is in thread mode, with privileged access rights. In the
priv ileged state, a p ro gram has access to all memo ry ran ges (ex cep t when proh ib ited by MPU
settings) and can use all supported instructions.
➢ Sof tware in the priv ileged access level can switch the p ro gram in to the user access level u sin g
the control register.
➢ When an exception takes place, the processor will always switch back to the privileged state
and return to the previous state when exiting the exception handler.
➢ A user program cannot change back to the privileged state by writin g to the control register.
➢ It has to go through an exception handler that programs the control register to switch the
processor back into the privileged access level when returning to thread mode.
➢ The separation of privilege and user levels improves system reliability by preventing
system configuration registers from being accessed or changed by some untrusted
programs.
➢ If an MPU is available, it can be used in conjunction with privilege levels to p rotect
critical memory locations, such as programs and data for OSs.
➢ The privileged accesses, usually used by the OS kernel, all memory locations can be
accessed (unless prohibited by MPU setup).
➢ When the OS launches a user application, it is likely to be executed in the user access
level to protect the system from failing due to a crash of untrusted user programs.
function1
Program code for function 1
...
...
...
...
BX LR ; Return. PC=LR
➢ R15 PROGRAM COUNTER
➢ Points next inst. to executed.
➢ Example if PC= 0x1000 ,
➢ MOV R0, PC ; PUSH R0;
➢ Special Purpose Registers: PSR, IMR, CR
1. xPSR (Program Status Register- APSR, IPSR and EPSR)
➢ It is a 32-BIT REGISTER
➢ The following instruction s can be used to read PSR registers.
➢ MRS r0, APSR ; Read Flag state into R0
➢ MRS r0, IPSR ; Read Exception/Interrupt state
➢ MRS r0, EPSR ; Read Execution state
b) System bus accesses memory and peripherals including Static Random Access
Memory (SRAM), external RAM, external devices, and part of the system level
memory regions.
➢ Private peripheral bus accesses a part of the system-level memory dedicated to private
peripherals, such as debugging components.
Debugging Support
➢ Cortex-M3 provides the following debugging features (a)Program execution controls
(haltin g and stepp in g) (b ) In struction breakpo ints (c) Data watch po in ts (d ) Registers and
Memory accesses (e) Profiling (f) Traces.
➢ Various events like breakpoints, watchpoints, fault conditions, or external debugging
request input signals can make the Cortex-M3 enter halt mode or execute the debug
monitor exception handler.
➢ Data Watch point and Trace (DWT) unit provides data watchpoint function to stop the
processor and generate trace information that can be output via the TPIU.
➢ Flash Patch & Breakpoint (FPB) unit provides a simple breakpoint function or remaps
an instruction access from Flash to a different location in SRAM.
➢ conceptual diagram of Debug support is shown below.
➢ In ARM cortex M3 the Debug system is kept outside (decoupled) the core. Bus
interface called the Debug Access Port (DAP) is provided at the core level which is
controlled by Debug Port (DP) device.
➢ The Debug ports are:
1. Serial-Wire JTAG Debug Port (SWJ-DP) and which supports the traditional
JTAG protocol as well as the Serial-Wire protocol.
2. Serial-Wire Debug Port (SW-DP) which supports only the Serial-Wire
protocol.
➢ The Trace signal is received by Trace Port Interface Unit (TPIU) then transferred to
PC or display device.
Another approach is:
➢ An Instrumentation Trace Macrocell (ITM) provides a new way for developers to
output data to a debugger.
➢ By writing data to register memory in the ITM, a debugger can collect the data via a
trace interface and display or process them.
➢ To determin e the startin g add ress of th e excep tion hand ler, a vector tab le, an array of wo rd
data inside the system memory, each representing the starting address of one exception
type.
➢ The vector table is relocatable, and the relocation is controlled by a relocation register in
the NVIC.
➢ The address is (type number X 04) = result in Hex. One can check the vector of different
exceptions given above.
➢ LSB is shown as ‘1’ for vector handler location as it is written in thumb code.
Recommended Questions
1. Briefly discuss how Cortex-M3 address the requirements of the 32-bit embedded processor market
2. Briefly explain the Thumb-2 technology and its advantages over thumb instruction set with relevat
diagram.
3. Write a short note on the applicatios of Cortex-M3
4. With a neat diagram, explain the architecture of ARM cortex M3 microcontroller.
5. What are the various registers in ARM Cortex M3? Specify the function of each of them.
6. Briefly describe the Special Register of ARM cortex M3.
7. Briefly explain about the operation modes and levels with relevant diagrams in case of ARM Cortex -M3
8. Explain the features of Nested vector Interrupt controller of ARM cortex M3.
9. With neat diagram explain the predefined memory map of ARM Cortex -M3
10. Write a short note on a) Bus interface b) Memory Protection units of ARM cortex M3.
11. Describe the interrupts and exceptions supported by ARM Cortex M3.
12. Describe the debugging support in ARM Cortex M3.
13. Explain the stack operations using PUSH and POP instructions in ARM Cortex M3.
14. With relevant diagrams explain the reset sequence in ARM cortex M3.