VLSI DEVELOPER

FLIP-FLOPS
BY BANOTHU BAPUJI

BANOTHU BAPUJI: +91 7569446894

bapuji2214@gmail.com PRAHAS SURABHI: +91 7993253293
Flip Flops &
’ FlipFlop is
single bit memor eletento)
storage eement
’ FlipFlop (s a Sequential circuit, and it is q

edge triggered circuit.

t) positive edge triggered Fliptops (1)
2) Negathve edge tiggered Fip flops )
-’ The diference betoeen Latches and Fipfops
’ Latches a Ye level trigge Ye.
’ FipF (ops are edge triggered.
Fipfop ls also Called as Bistable Nulti
-vibrator.
It has t o stables states thOse

(logTc-4)
Posiive leve

Negative leve< Clogic-o)

Positive edge (^)- logic-A

k- T
Negative edge (VJ-togic-o

VLSIDeve lopevs Banothu Bapui

 Types of fiipFlop s;
>TheYe are Four types of Ftipttops .
A) s-R Flip Flop
2) D -Ftip Flop.
3) Jk FlipFlop,
4) T - FipFlop.
1)S-R Fip Flopo
SR Fip Fop 15 also called as sety
Reset FIipF(op
’ The Set indiaty the output as (ogie-i
’ The Rese t indicates the output as logic-o.
> The SR FlipFlep can be designed using
NAND qates and also sing NOR gcates
The
Eol Dwina table showsthe Tuth Table
of NAND gaee
-’1fang one inpat Ts logic
-o then othout etrna
another input the output
is diey (ogic-i
’The Follooing fia shousl
SR -FlipElop
-fli pF(op ciicuit diagram.
Piesentstate N t stata
present Do Qnt|

Qnt|

VLSS Developevs Bansthy Bapuji

 The operation of the sR Fip Flop Can be
SR
explained in the Follou ing Nas:
Case -i S=0 )

fNo-change state.
Case -i - s=0 3 R=| j cLk =|
Reset state

case -iti - s=Roj

nt|=
, Set state

Case-iy S=|| R=| CLK=|

Qnt| = Invalid state.

Truth Table of SR fliptop

Ps NS
Ps n Qt
S R
OnNc
X Reset Pleset
set
1nvalid
ID
thvaid

VSJ Developevs Barothy Bapuji

2D-ElipFlop
’ The D-FtipFlop s a Data FlipFlopit is also
called as Delay FipFlop (o) Tansparcnt Flipflop
’ The outpt of the p-Fip Fo p is saMe as
tnput but the diference is thct Delay in
the output with yespect to input.
’ The DElipFlop 7s ied tn the Registes
’ The D-Fip FHop îs obtained From the
sk Fip Flop by the s&R
with an
shortcircuiting
not gate
’ The D-Fip F(op crcuit is given in a below

RS Ns

-
The operation of the D FipFop Can be
explained in the following vway
Case-4
D=0 ’ S=oB R=| CL= 1

state.

VLSI Develo pevs Banoty Bapuji

 the
utili2e
’ the ’The SCientist
SClentst Case 2
inputs stato nputs
too Jk ’ 3) Truth
Table ßf D=|
Theoutputs The J-k
D
JE Flip
Sk SRJk JEFlP ’
1.1
the
FipFipFlop Flip Flop
FIUpF(op Fip s=[
Me
na Flop
Jack
F(op( Flop Ts flop &
as
R=o
s byCan and kilby.
derlve
tn Flop
FlpD-
valid as Set Reset
troduced inputs
tothe
preeut feed So it cuk=1
be invented
stato
inatin Comin back
obtained termed From the
) state.set
of AMe by
to the
asthe
Next fron The
of
 Case 2 Casei The
J=
0) CUk=1
k=0j
J=0
explained Cordition.
’The Hence, util|2ed
output iuoth ’But
me
diagram
ope
foloig ig it n
ration wil Tk
theTn of is
FCp
f suffers
JE Called Flop.that
,‘ the
follovoing F(ip
lop. shoes drawback.i.e..
thc
JE shoes as to
state.
Reset No
FlipF multipla
Combintion
qYound
Race
a change
state thethe
Roughook
I"|-Q n lop
cirCuit toggling
s
N'S
s
 Case 4: J=l Case-3
15isThe Inval'd
output wetoHere
nti =
1 C gi
ven Tuth get kzo
find fFirstty
k
be
Tate I- the
1 1
low Qnt CLK
Qrt|Qn we
of = Toggle
Jlk nt| as
then ne 1
FlpFlop o ed
(Toggle stat
staset te to
Reset
state changeNo ) t state
Set
state.
Toggle findthQhte
otheise, iF
gate-2 eaugh giwithvle eough
gate-i oit
'of
yatr)
 Casei ’ The 7 7The ’ 4)
nt
On
= inIhe Tot qoamdta The ’T-Fip
FlpF(op.Tk cOuntersofanoundevexy The T-
the
opeYation cicui
shovt
ting FR
kol Jol follovoing
Folloo
4ne cutput
cutput
T=0J=0
CLk<1
;k=o
followi Toggle Toggle hence
time,
of Flop
Cond+ton. oP
of Fip of is
Ftip of
the LQn Fg
Fi Flop
the FlipFlop.
Togsle a
Way HopFlipT- Flop Toggle
T-Fipflop shas is TE
state.
changeNo T&k can used Is
called
Flip
be
cirCuitthe in
cbtained
in lop F
s a 2 pute the as
explaned Race il
NS
o bydesin
chang
-
 Case 2
Table
Truthof

FE
T-state.
loggle
Rough
gate-1
work
1-1on
Toggle
state to-2ga
harge
sa
te
 On that
’In Occas ’The back
feedthe Condition
aroundBace
the ’ itsand the case
the be to -the Flo
togglingFp
p
The so The The

Follooi
e
itthutput Race Race Race
aTound
Race knon as signal.
putTn
causesinput 1e
thevelarou aroun state
ng arou
loTs
hg lohg
Tining
the wil fed statt of n
Condition. Race condiion Case
condition
nt duty dubyConditian Togge
(Rate
ntod).mtYgslCu i ipe diagraM multichange input
sdeto trl9gered
FlipFeps of
qYou cyee of
ple
<ya Tnput
n Tsoutputs is the îs
accordingy
togsling amultiplo
showsCondition of ofmaunly due
T; Jk
clock the kto to
 ’Duetheto ) The
Delay the Butthe ’ elfminate
the ’ the y
signal
Folooig
C(ock The The edge o) 1) Race
TE
edge
t4 t shavp
rgNNeedgethts Positive Positive
edge trigge arou
edge eice edge Mastey
Follouoing
trigge
cut triggeled ved no
Rise practical
off cond
Içal Negative qround
edoecondition
RaceFitpFlops; slave red
timeNegativedse edges. fig methods
ition
clock Ftp flp
delay shoos
ideal
the Flip Can

Flops Fop.flops,
ipFlop on (or) dono (dedaVObe

t Can
Fatt
time hag
 ’the ’The ’Tk 2)
mnimi2¢
as
Whenthe ’ nvevted
clock cock in eate
Note
The acts The
tateh. level toggling
minimal
K state cyeeactivewifloduty Tk
r
cock
state.
Active
and Nomal
cock
triggeredMasteY
then cycleMaster FF
Master
master
he
aYe
slave acts
it
slave
lock c
theofclock will Slave
thefor slave Race
is Gated
FlipFlops.
thcaled
e also as
acHve Fip
Called the latches Master aroqnd
On
R for Tk
Floo
dave cawhen Masten FlipFlopo
ON
Negative and for
the (ateh
as Cons+sts
the the the otth and Condi
memory state and
MasteslaYe
FE ion
level Positjve
slave Gated of
Tsitts ts level
state OFF called and the to
duty given biggr sR
level the
.
 ’The Fo llowing Imaqe predicts vohey the Maste
ON ,OF dod slave oN, OFF,
MastooN,
slave oFF!

Masbo
Save oN
k

The operatio of the Master slave flipFlop

is given folloos.
Case-1 o- J=D ; K*0 CLK=1(ostive cyclu)
Maste - ON
Slave -OFF
The outpul of
oF Lk aYe unchaned and
Slave -OFF the ojp ef slave are
* clk =0 nocharge
CNegatve cycley
MasteY- OFF
slave -OFF
The output of se ss unchanged due to
No-change s,P inputs.
Case-2 J= o; k=|; CLk =1
Master -ON slave -OFF
S=0
=0’s No

VLSJ Developess Banoths Bapuji

 Mastey - OFF Qn =o Reset state
slave -ON

Case-3 J=k=0j CLKEl

Marter - oN slave -oFF

Qndonot
GJchange

Maste -oFF
slave -oN Set state

Case- 4- J= k=| CLk |

Master-oN slave -OFF

Toggle R Togsley nn chae

No

VLST Developers Barothu Bapuji

 Mastey- OFF
slave - oN

’The output gn y Gr ae also toggy

but it toill hot toggle multiple times
beauw the tput s fed back to the
tnput ff Tk Flip Flcp and t is in
DFF state due to cock 0
’Hence by this we can avoid the Race around
Condticn.
’ The Follooing fig shows the timing diagram
.oF the 1kJk Mater slave Flip flop.
M-ON S-ON SoN M-ON
S-ON

S slave!
| fobys
mastey
VLSI Deve lorer Banothy Bapuyi
 Characteistic ea cnd Excitation taba s8
characteuistiç
’characteristc
sg"def
eal TsS a alge braic eq,7t
Is sepre sented n Combination o
the prcsent sta a next state and pyesent
input
Next state = present inpat + present stat
(revious
NS outpat)

1.

characteristic el.

VLsT Develo pexs Banothy Bapyi

 Excitation table def
’ Thìs table epiesents the input con bingtay
for the Tequired outputs.
characteistictable
The excitation tabk and
both are used Tn the fip f(op (onveYsirnd.

characteristic ta ble. excitation ta ble.

nt

characteristYc e and excitatin table of D

chara cteristic ea?
D
D
D

ri= D

WST Develo pers Banoths Bapuy

Excitatim Table of D-FF:
Qn
C

characteristie
Tk Flip Flop
ea and Exatain Tate ¢
Jk

VLSI Develo pers Bangthy Bapy)

 Fxcitu in Ta b of Tk FF!
characterisic eq excitatiÝn Tablo
k
3

X
X

X
1

charactevisie eq" and Excitatin Ta ble of

T-Flipflop
o nt T

To
1
T1

VLSI Developers Banothy Bapi

Exitatin Table of T-FF:

VLST Deelopevs Banothu Bapuyi