Birla Institute of Technology & Science, Pilani

Work Integrated Learning Programmes Division

Second Semester 2022-2023
Comprehensive Exam
(EC-3 Regular)

Course No. : MEL ZG621

Course Title : VLSI DESIGN
Nature of Exam : Open Book
Weightage : 40% No. of Pages =
Duration : 2 Hours 30 minutes No. of Questions = 6
Date of Exam :
Note to Students:
1. Please follow all the Instructions to Candidates given on the cover page of the answer book.
2. All parts of a question should be answered consecutively. Each answer should start from a fresh
page.
3. Assumptions made if any, should be stated clearly at the beginning of your answer.

Q.1. Set A

An enhancement-type MOSFET is fabricated 0.4 µm process in with L = 0.8 µm and W= 16 µm.

Find the value of ID for VOV = 0.5 V and VDS = 1 V. Do not neglect CLM. If V DS is increased by 2 V
what is the corresponding change in ID.
Total 4 Marks

Q.2. Set A
Write the most simplified expression for output functions F(X,Y) and G(X,Y).

Total 4 Marks
Q.3. Size the given NAND using ‘worst path first sizing technique’ given that unit inverter NMOS
has width W and PMOS has width 2W. Write the node capacitance at nodes A, B, X and Y
(without external load), given that each MOSFET has a gate capacitance of ‘C’ per ‘W’ width.
(Length of all MOSFETS of the unit inverter and NAND gate are the same. The channel resistance
of the NMOS and the PMOS of the unit inverter is ‘R’. Find the best case (contamination tpLH)
and Worst case (Propagation delay tpLH ) of the NAND gate if it is driving similar four NAND
gates, in terms of ‘R’ and ‘C’ using Elmore Delay Model. Assume self-loading factor =1.

Total 8 Marks

Q.4 The circuit implementing Y= A(B+C)D with power supply of 1.2 V given below suffers from
maximum charge sharing problem, for a set of specific inputs during previous evaluation, followed
by a pre-charge cycle and then followed by specific inputs during current evaluation phase. The
inputs are derived from positive-edge-triggered flip-flops. The capacitances for nodes (Y,P,Q & R)
are indicated in the figure. The threshold voltage of the nMOSFETs is 0. 5 V. Neglect Body effect.
Given this condition,

(i) Identify these inputs during previous evaluation phase and inputs during the current
evaluation phase which can cause the maximum charge sharing problem.
(2+2 Marks)
(ii) Maximum drop in voltage at output node Y during current evaluation (2Marks)
(iii) Voltages at nodes Y,P,Q & R after charge sharing during current evaluation (2Marks)
Total 8 Marks
Q.5 Find minimum total delay in terms of delay of unit inverter and size the gates (both NMOS
and PMOS) accordingly. Consider unit inverter NMOS width as W and PMOS width as 2W.
Total 10 Marks
Q.6 A Sample ROM is shown below. The word line is driven by 2X4 active low decoder which
has A and B as inputs (both single bit). Modify the circuit by placing connecting transistors at
appropriate places to get sum of A and B at BL[0] and carry at BL[1].
Total 06 Marks