DCD LAB 4 Report

Design of Finite State Machine in „Alarm

System „Application

Prepared By: ADEYEMI MAYOWA

Contents
Design of Finite State Machine in "Alarm System" Application...................................................................3
Specifications...........................................................................................................................................3
Introduction.................................................................................................................................................5
Top level Design Of The Alarm System.........................................................................................................5
Implementation Lab 3 Components............................................................................................................6
VHDL CODE FOR TOP LEVEL.........................................................................................................................7
Finite State Machine....................................................................................................................................9
Implementation Of Buzzer And RGB Led...................................................................................................10
VHDL Code.................................................................................................................................................10
Reused Components for The Lab4 Finite State Machine in Alarm System.................................................13
RTL Schematic............................................................................................................................................13
Resource Utilization report........................................................................................................................14
Design of Finite State Machine in "Alarm System" Application
Overview:

In this task, you will be designing a Finite State Machine (FSM) for an "Alarm System" application, which
will be controlled by buttons, sliders, and various sensors. The alarm system will output an alarm sound
through a buzzer and display its status using an RGB LED. The FSM will govern the transitions between
different states and control the alarm system's behavior based on the inputs from sensors and user
interactions.

Figure 1: Task Peripherals

Specifications:
1. FSM Design:

a. The core clock of the system is 125MHz, and a slider will be used as a global reset.

b. The alarm system can be turned on/off using a slider, acting as a power switch.

c. When the alarm system is in the ON-state, it can be armed for active monitoring.

d. If the alarm system is in the ARMED-state, it will transition to the ALARM-state when any of the
input sensors raise a trigger.

e. The ALARM-state can be manually cleared, and the system will return to the ON-state.

2. User Interaction:

a. Use a push-button to toggle the alarm system's state between ON and ARMED.

b. The same push-button will be used to clear the alarm, transitioning from the ALARM-state to the
ON-state.

3. Sensor Integration:

Use the following sensors in the alarm system:

 a. Motion Sensor: Provides a binary sensor signal to detect motion.

b. Light Sensor: Provides a binary sensor signal to detect illumination.

4. Alarm System Status Display:

a. The status of the alarm system will be displayed using an RGB LED.

b. LED Status:

- RESET-state: LED turned off.

- OFF-state: LED turned off.

- ON-state: LED in green color, turned on permanently.

- ARMED-state: LED in blue color, with a 100msec pulse every 1 sec.

- ALARM-state: LED in red color, with a 500msec pulse every 1 sec.

5. Buzzer Output:

The buzzer will output an alarm signal, switching from 1kHz to 2kHz five times per second during the
ALARM-state.

Deliverables:

1. Top-Level Diagram: Provide a graphical representation of the top-level design of the Alarm System
FSM.

2. Test Bench Diagram: Create a test bench diagram to demonstrate the functionality and behavior of the
FSM.

3. Example Simulation Waveform: Include a screenshot of a simulation waveform to showcase the FSM's
operation.

4. Resource Utilization Report: Provide a report detailing the resource utilization of the FSM after
implementation in Vivado.

5. Textual Explanation of Design Architecture: Write a comprehensive explanation of the FSM design
architecture, detailing the state transitions, input handling, and output generation.

6. Re-Used Components Explanation: Explain how many components in the design could be re-used from
previous designs to improve design efficiency and reduce redundancy.

7. Library Archive (.zip): Submit a .zip archive containing the necessary libraries used in the FSM design.

The successful completion of this task will result in a well-designed FSM that efficiently controls the
"Alarm System" application, providing accurate state transitions, proper sensor integration, and reliable
user interactions. Please seek clarification from the project manager or team lead if you have any
questions during the design process.
Introduction
To create an alarm system with user-controlled buttons and sliders, integrated with various sensors. The
system should activate a buzzer for alarms and show status using an RGB LED.

Top level Design Of The Alarm System

The Top Level Design integrates essential components for Lab3: sync_fpga, alarm control FSM, PWM
modulo counter for RGB LED, and buzzer generating 1kHz and 2kHz frequencies at 5x per second. The
sync_fpga ensures efficient communication, while the FSM manages alarm states. The PWM counter
controls RGB LED blinking, and the buzzer produces two distinct frequencies. This design facilitates
synchronized functionality and robust performance in the Lab3 project.

Figure 2: Top Level Diagram

Implementation Lab 3 Components

Figure XX: Top Level Diagram Of Lab 3

The Lab 3 top-level design incorporates various components to implement a versatile system. It starts
with an input mechanism that allows users to enter a 4-bit parameter through either two buttons or a
rotary encoder. This parameter can be incremented or decremented using the rotary encoder, providing
a user-friendly interface for value adjustment.

The design also includes four LEDs that can be dimmed to display the 4-bit parameter in binary form or
to visualize other information. Additionally, two buzzers are included, and their frequencies can be
adjusted dynamically. The frequencies can be modified using the input mechanism or sliders, providing
audio feedback to users.

A single button is dedicated to turning on/off the entire peripheral system, making it convenient to
control the overall functionality. Furthermore, three sliders are incorporated to address specific
peripherals or functionalities within the system. Users can slide these controls to select a particular
peripheral or setting, offering enhanced configurability and interactivity.

Overall, the Lab 3 top-level design offers a feature-rich and user-friendly system with multiple inputs and
outputs, allowing users to interact with and control various peripherals efficiently. The combination of
buttons, sliders, rotary encoder, LEDs, and buzzers ensures a seamless and engaging user experience in
the lab project.
VHDL CODE FOR TOP LEVEL

-- VHDL Architecture Lab2_lib.sync_fpga.rtl

--
-- Created:
-- by - m47i23.UNKNOWN (R001703)
-- at - 14:18:52 07/20/2023
--
-- using Mentor Graphics HDL Designer(TM) 2017.1a (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

entity sync_fpga is
port(
clk : in STD_LOGIC;
but : in STD_LOGIC_Vector (3 downto 0);
sliders : in STD_LOGIC_Vector (3 downto 0);
encoder : in STD_LOGIC_Vector (1 downto 0);
sliders_s : out STD_LOGIC_Vector (3 downto 0);
encoder_s : out STD_LOGIC_Vector (1 downto 0);
but_stb : out STD_LOGIC_Vector (3 downto 0);
sliders_stb : out STD_LOGIC_Vector (3 downto 0);
encoder_stb : out STD_LOGIC_Vector (1 downto 0);
but_s : out std_logic_vector (3 downto 0)
);

-- Declarations

end sync_fpga ;

--
architecture rtl of sync_fpga is
signal q0, q1, q2, q3, stb : std_logic_vector (9 downto 0);
signal counter: std_logic_vector(23 downto 0) := (others=>'0');
signal strobe: std_logic;

begin
process(clk)
begin
if rising_edge(clk) then
q0 <= but & sliders & encoder;
q1 <= q0;
 if strobe = '1' then
q2 <= q1;
end if;
q3<= q2;
end if;
end process;

but_s <= q2(9 downto 6);

sliders_s <= q2(5 downto 2);
encoder_s <= q2(1 downto 0);
stb <= not q3 and q2;
but_stb <= stb(9 downto 6);
sliders_stb <= stb(5 downto 2);
encoder_stb <= stb(1 downto 0);
process(clk)
begin
if rising_edge(clk) then
if strobe='1' then
counter<= (others=>'0');
else
counter<=counter+1;
end if;
end if;
end process;
strobe<= '1' when counter= 1250000-1 else '0';

end architecture rtl;

Finite State Machine

Figure 3: Finite State Machine

The Finite State Machine (FSM) designed for the "Alarm System" application includes five states: S_reset
(global reset), S_off (turning off the system), S_On (turning on the system), S_armed (arming the
system), and S_alarm (alarm triggered state). The FSM controls the system's behavior, allowing smooth
transitions between states based on user inputs, sensor triggers, and manual clearing of alarms, while
displaying the status using an RGB LED.
Implementation Of Buzzer And RGB Led

Figure 4: Lab 4 Buzzer And RGB Led Components

The "buzzer_component" block in the Alarm System design is responsible for controlling the buzzer. It
includes a clock reset, an std_logic vector "status" (2 down to 0) to represent system states, and an RGB
LED. The block generates output signals for the buzzer, providing relevant information based on the
system's current state.

VHDL Code
--
-- VHDL Architecture Lab1_lib.buzzer.rtl
--
-- Created:
-- by - m47i23.UNKNOWN (R001703)
-- at - 16:43:46 07/26/2023
--
-- using Mentor Graphics HDL Designer(TM) 2017.1a (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;

entity buzzer_comp is
port(
clk : in std_logic;
reset : in std_logic;
status : in std_logic_vector ( 2 downto 0);
rgb : out std_logic_vector ( 2 downto 0);
output : out std_logic_vector (1 downto 0)
);
-- Declarations

end buzzer_comp ;
architecture rtl of buzzer_comp is
signal aux, aux_1,tc, tc_2, pwm_r, pwm_b, red, green, blue: std_logic :='0';
signal buzzer1: integer;
signal cnt, cnt_1, cnt_2: std_logic_vector(31 downto 0) := (others => '0');
begin

process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
cnt <= (others => '0');
else
cnt <= cnt+1;
if cnt = buzzer1 then
aux <= NOT aux;
cnt <= (others => '0');
end if;
end if;
end if;
end process;

process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
cnt_1 <= (others => '0');
else
cnt_1 <= cnt_1+1;
if tc = '1' then
aux_1 <= NOT aux_1;
cnt_1 <= (others => '0');
end if;
end if;
end if;
end process;
buzzer1 <= 31_250-1 when aux_1 = '1' else 62_500-1;
tc <= '1' when cnt_1 = 12_500_000-1 else '0';

process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
cnt_2 <= (others => '0');
 else
cnt_2 <= cnt_2 +1;
if tc_2 = '1' then
cnt_2 <= (others => '0');
end if;
end if;
end if;
end process;

tc_2 <= '1' when cnt_2 = 125_000_000-1 else '0';

pwm_b<= '1' when cnt_2 < 12_500_000 else '0';

pwm_r<= '1' when cnt_2 < 62_500_000 else '0';

red<= status(1);
blue <= status(2);
green<= status(0);

--connect internal signal to output port

output(0) <= aux when red = '1' else '0';
output(1) <= not aux when red = '1' else '0';

rgb <= (blue and pwm_b) & (red and pwm_r) & (green);
end architecture rtl;
Reused Components for The Lab4 Finite State Machine in Alarm
System
In the design of the "Lab4 Finite State Machine in Alarm System," a total of three components, namely
lab1, lab2, and lab3, have been re-used from previous designs. These components likely handle
functionalities such as clock reset, slider control, push-button control, and RGB LED display. By leveraging
these existing components, the design achieves greater efficiency, reduces redundancy, and ensures
consistency across the Alarm System application.

RTL Schematic

Figure 5: The Vivado RTL Schematic

Resource Utilization report
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------
----
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date : Mon Jul 31 21:50:22 2023
| Host : R001703 running 64-bit major release (build 9200)
| Command : report_utilization -file top_alarmsystem_utilization_synth.rpt -pb
top_alarmsystem_utilization_synth.pb
| Design : top_alarmsystem
| Device : 7z010clg400-1
| Design State : Synthesized
---------------------------------------------------------------------------------------------------------------------
----

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking
6. Specific Feature
7. Primitives
8. Black Boxes
9. Instantiated Netlists

1. Slice Logic
--------------

+-------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------+------+-------+-----------+-------+
| Slice LUTs* | 79 | 0 | 17600 | 0.45 |
| LUT as Logic | 79 | 0 | 17600 | 0.45 |
| LUT as Memory | 0| 0| 6000 | 0.00 |
| Slice Registers | 151 | 0 | 35200 | 0.43 |
| Register as Flip Flop | 151 | 0 | 35200 | 0.43 |
| Register as Latch | 0 | 0 | 35200 | 0.00 |
| F7 Muxes | 0| 0| 8800 | 0.00 |
| F8 Muxes | 0| 0| 4400 | 0.00 |
+-------------------------+------+-------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is
typically lower. Run opt_design after synthesis, if not already completed, for a more realistic
count.

1.1 Summary of Registers by Type

--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
|0 | _| -| -|
|0 | _| -| Set |
|0 | _| -| Reset |
|0 | _| Set | -|
|0 | _| Reset | -|
|0 | Yes | -| -|
|0 | Yes | -| Set |
|0 | Yes | -| Reset |
|0 | Yes | Set | -|
| 151 | Yes | Reset | -|
+-------+--------------+-------------+--------------+

2. Memory
---------

+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| Block RAM Tile | 0 | 0 | 60 | 0.00 |
| RAMB36/FIFO* | 0 | 0 | 60 | 0.00 |
| RAMB18 | 0| 0| 120 | 0.00 |
+----------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can
accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block
RAM Tile, that tile can still accommodate a RAMB18E1

3. DSP
------

+-----------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------+------+-------+-----------+-------+
| DSPs | 0| 0| 80 | 0.00 |
+-----------+------+-------+-----------+-------+
4. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 18 | 0 | 100 | 18.00 |
| Bonded IPADs | 0| 0| 2 | 0.00 |
| Bonded IOPADs | 0| 0| 130 | 0.00 |
| PHY_CONTROL | 0| 0| 2 | 0.00 |
| PHASER_REF | 0| 0| 2 | 0.00 |
| OUT_FIFO | 0| 0| 8 | 0.00 |
| IN_FIFO | 0| 0| 8 | 0.00 |
| IDELAYCTRL | 0| 0| 2 | 0.00 |
| IBUFDS | 0| 0| 96 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0| 0| 100 | 0.00 |
| OLOGIC | 0| 0| 100 | 0.00 |
+-----------------------------+------+-------+-----------+-------+

5. Clocking
-----------

+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0| 0| 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 48 | 0.00 |
| BUFR | 0| 0| 8 | 0.00 |
+------------+------+-------+-----------+-------+

6. Specific Feature
-------------------

+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0| 0| 2 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0| 0| 1 | 0.00 |
+-------------+------+-------+-----------+-------+

7. Primitives
-------------

+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| FDRE | 151 | Flop & Latch |
| CARRY4 | 41 | CarryLogic |
| LUT2 | 40 | LUT |
| LUT4 | 16 | LUT |
| LUT5 | 15 | LUT |
| LUT1 | 14 | LUT |
| IBUF | 9 | IO |
| LUT6 | 8 | LUT |
| LUT3 | 8 | LUT |
| OBUF | 7 | IO |
| OBUFT | 2 | IO |
| BUFG | 1 | Clock |
+----------+------+---------------------+

8. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+

9. Instantiated Netlists
-----------------------

+----------+------+
| Ref Name | Used |
+----------+------+

Adeyemi Mayowa

31st July, 2023