VLSI Design : Review Lecture 1-14

By Dr. Sanjay Vidhyadharan

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 MOSFET Current
Linear Region- Small VDS
µ𝑛𝐶𝑜𝑥 𝑊(𝑉𝐺𝑆 − 𝑉𝑇 )𝑉𝐷𝑆
𝐼𝐷 =
𝐿
Saturation Region
𝑊
𝑘𝑛′ = µ𝑛𝐶𝑜𝑥 𝑘𝑛 = µ𝑛𝐶𝑜𝑥
𝐿

Linear Region as VDS is Increased

𝑉𝐷𝑆
𝑘𝑛′ 𝑊(𝑉𝑜𝑣 − 2 )𝑉𝐷𝑆
𝐼𝐷 =
𝐿

Saturation Region

𝑘𝑛′ 𝑊(𝑉𝐺𝑆 − 𝑉𝑇 )2
𝐼𝐷 =
2𝐿
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 Channel Length Modulation

When the VDS is increased beyond VOV , the pinch-off point is moved slightly away from the drain,
toward the source. The additional voltage applied to the drain appears as a voltage drop across the narrow
depletion region between the end of the channel and the drain region. This voltage accelerates the
electrons that reach the drain end of the channel and sweeps them across the depletion region into the
drain.

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 Channel Length Modulation

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 Channel Length Modulation

𝑉𝐴 𝐸𝑎𝑟𝑙𝑦 𝑉𝑜𝑙𝑡𝑎𝑔𝑒
1
𝜆= λ ∝ 1/L
𝑉𝐴

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 Resistive Load Inverter

Calculation of VOH
VOut = VDD - RL IR
VOH = VDD

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 Resistive Load Inverter

Calculation of VOL

Ratioed logic

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 Resistive Load Inverter
Calculation of VIL

Differentiating both sides with respect to Vin

𝑑𝑉0
[ 𝑑𝑉𝑖 = -1]

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 Resistive Load Inverter
Calculation of VIH

Differentiating both sides with respect to Vin

𝑑𝑉0
[ 𝑑𝑉𝑖 = -1]

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 Resistive Load Inverter

𝐾𝑛 (𝑉𝐺𝑆 − 𝑉𝑇 )2
𝐼𝐷 =
2

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 Enhancement-Load nMOS Inverter

➢ Relatively simple fabrication process ➢ Two separate power supply

➢ VOH level is limited to VDD - VT ➢ VOH = VDD

➢ High Static Power

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 Depletion-Load nMOS Inverter

Depletion-type nMOS load is more complicated & requires additional processing steps

➢ VOH = VDD
➢ Single power supply

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 Numerical

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 CMOS Inverter Switching Threshold
The Switching Threshold, VM , is the point where Vin = Vout .
This can be calculated:
» Graphically, at the intersection of the VTC with Vin = Vout

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 CMOS Inverter Switching Threshold

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 CMOS Inverter Switching Threshold

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 CMOS Inverter Switching Threshold

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 CMOS Inverter Switching Threshold
For Short Channel Devices

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 CMOS Inverter Switching Threshold

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 CMOS Inverter Switching Threshold
Increasing the width of the PMOS moves VM towards VDD
Increasing the width of the NMOS moves VM towards GND

𝞫 -> VM (250 nm VDD = 2.5 V)

3 -> 1.22 V
2.5 -> 1.18 V
2 -> 1.13 V
Since it not making much
difference

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 Noise Margin

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 Noise Margin
For VIL

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 Noise Margin
For VIH

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 Numerical

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 Numerical

3.3 – 1.43 Vout -1.17 - 0.7

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 CMOS Inverter: Delay-Time Calculation
Three Methods

1. Average Current Model

2. Differential Equation Model
3. 1st Order RC delay Model

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 CMOS Inverter: Delay-Time Calculation
Average Current Model 𝑞 𝑑𝑞 𝑑𝑣
𝑐= ≫𝑖= =c
𝑣 𝑑𝑡 𝑑𝑡

Note that the average current during high-to-low transition can be calculated by using the
current values at the beginning and the end of the transition.

𝑉𝐷𝑆
𝑘𝑛′ 𝑊(𝑉𝑜𝑣 − 2 )𝑉𝐷𝑆
𝐼𝐷 =
𝐿
𝑘𝑛′ 𝑊(𝑉𝐷𝐷 − 𝑉𝑇 )2 𝑉 𝑉𝐷𝐷
𝐼𝐷 = 𝑘𝑛′ 𝑊(𝑉𝐷𝐷 −𝑉𝑇 − 𝐷𝐷 )
2𝐿 4 2
𝐼𝐷 =
𝐿
180 nm: VGS = 1.8 V, VTH = 0.6 V VDS = 1.8 V VGS = 1.8 V, VTH = 0.6 V VDS = 0.9 V

Similarly, the average capacitance current during low-to-high transition is

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 CMOS Inverter: Delay-Time Calculation
Differential Equation Model
𝑄
𝐶=
𝑉
𝑑𝑉
𝑖 =𝐶
𝑑𝑡
𝑑𝑉
𝑑𝑡 = 𝐶
𝑖

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 CMOS Inverter: Delay-Time Calculation
Differential Equation Model

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 CMOS Inverter: Delay-Time Calculation
Differential Equation Model
Approximate by assuming in saturation:

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 CMOS Inverter: Transient Response
1st Order RC delay Model

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 CMOS Inverter: Transient Response
1st Order RC delay Model

Furthermore, it has been found that these values apply for a number of CMOS fabrication
processes including 0.25 μm, 0.18 μm, and 0.13 μm (see Hodges et al., 2004).

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 Numerical

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 Sizing of CMOS Chain of Inverters

ln(𝐹)
ln(𝑓) =
𝑁

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 Sizing of CMOS Chain of Inverters

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 Transistor Sizing for a Complex Gate
Shortest Path First Sizing

( )𝞫 = 0.75

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 Transistor Sizing for a Complex Gate
Worst Path First Sizing

1 1 1
+6=2
𝑋

( )𝞫 = 0.66

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 Capacitance of Complex Gate
Cout = 4C
Merged
uncontacted

Cout = 6C
Cout = 3C =1
Cin = =1
3C
Cin =
5C

C is capacitance per W width of MOSFFET.

Length is Contact for all devices
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 Capacitance of Complex Gate

Cout = 3C
Cin = =1
3C

Cout = 2C
Merged
uncontacted
C is capacitance per W width of MOSFFET.
Length is Contact for all devices
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 Capacitance of Complex Gate

Cout = 2C
Merged
uncontacted
C is capacitance per W width of MOSFFET.
Length is Contact for all devices
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 Transistor Sizing for a Complex Gate
Fanin considerations ( Contamination and Propagation Delays)

𝑇𝑝𝐿𝐻 = 0.69R(CL+2C3+3C2+4C1) WC
𝑇𝑝𝐿𝐻 = 0.69RCL BC 𝑇𝑝𝐻𝐿 = 0.69*4*RCL BC
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 Delay in a Logic Gates

Digital Integrated Circuits By Jan M Rabaey

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 Logical Effort
Paths that Branch

G =1 15
90
F = 90 / 5 = 18 5
GF = 18 15
90
f1 = (15 +15) / 5 = 6
f2 = 90 / 15 = 6
F <-> H
H = g1g2f1f2 = 36 = 2GF (B=2)
H = GBF
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 Logical Effort : Example

• Select gate sizes x and y for least delay from A to B

x

y
x
Critical path
45
A 8
x
y B
45

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 Logical Effort : Example
x

y
x
45
A 8
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort F = 45/8
Branching Effort B=3*2=6
Path Effort H = GBF = 125
3
Best Stage Effort ℎ= 𝐻=5
Parasitic Delay P = 2 + 3 + 2 = 7
Delay D = 3*5 + 7 = 22 = 4.4 FO4 Delay FO4 = 5

In multiples of pinv (1)

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 Logical Effort : Example
• Delay of a fanout-of-4 (FO4) inverter
d

Logical Effort: G=1

Electrical Effort: F=4
H = FG = 4
h=4
Parasitic Delay: p=1
Stage Delay: d=5

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 Logical Effort : Example

• Work backward for sizes

y = 45 * (5/3) / 5 = 15 h = 5 = fg the stage effort
f = 5/g the gate effort
x = (15*2) * (5/3) / 5 = 10

45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3

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 Euler Paths
See if you can “trace” transistor gates in same order, crossing each gate once, for N and P
networks independently Where “tracing” means path from source/drain of one to
source/drain of next Without “jumping” connections

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 Euler Paths

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 Euler Paths

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 Euler Paths

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 Area Estimation

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 Area Estimation

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 Area Estimation

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 Transition Activity

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 Dynamic Logic
➢ Dynamic Logic Suffers from Charge Sharing Phenomenon

Case1. ΔVout < VTn-Vout


Y VDD.CY = VY C Y + (VDD- VTn)CX
A x CY
(VDD− VTn)CX
Cx ΔVout = -
B=0 CY

CX << C Y

V= Q/C

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 Dynamic Logic
➢ Dynamic Logic Suffers from Charge Sharing Phenomenon

Case2. ΔVout > VTn-Vout


Y
A CY VDD.CY = VY C Y + VXCX
x
B=0 Cx VDD.CY = VY C Y + VYCX
VDD.CY = (VDD + ΔVout) (C Y + CX)

VDDCX
ΔVout = -
CY+CX

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 Dynamic Logic

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 Dynamic Logic

Solution to Charge Redistribution Keeper PMOS used to

restore high state

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 Dynamic Logic

➢ Cascading Dynamic Gates

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 Domino Logic

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 Domino Logic

➢ Cascading Domino Logic

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 Domino Logic

22T Domino Full Adder

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 Pass Transistor Logic

➢ Negligible Static Dissipation

➢ Lesser Dynamic Dissipation
Short Circuit
Switching Loss

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 Pass Transistor Logic
Full Adder

Sum = A•B’•Cin’ + A’•B•Cin’ + A’•B’•Cin + A•B•Cin

For Cin = 0 Sum = A•B’ + A’•B
For A = 0 Sum =B
For A = 1 Sum =B’
For Cin = 1 Sum = A’•B’ + A•B
For A = 0 Sum =B’
For A = 1 Sum =B
[8] L. Gao, “High performance Complementary Pass transistor Logic full adder,” in Proceedings of 2011 International
Conference on Electronic Mechanical Engineering and Information Technology, vol. 8, Aug. 2011, pp. 4306–4309.
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 Carry Look-Ahead Adder
C0
C4

3 Gate Delay for G3

2 Gate Delay for P3

4 Gate Delay for C4

4 Gate Delay for S3

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 Carry Look-Ahead Adder

8 Bit Full Adder

Delay = 4 + 4 = 8 Gate Delay for C8

= 4 + 4 = 8 Gate Delay for S7 67

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 Carry Look-Ahead Adder

16 Bit Full Adder

one unit of time

additional 2 units of time

6 Delays for C16

8
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 Carry Look-Ahead Adder

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 Carry Bypass or Carry Skip Adder

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 Linear Carry-Select Adder

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 Square Root Carry-Select Adder

𝑡𝑎𝑑𝑑 = 𝑡𝑠𝑒𝑡𝑢𝑝 + 𝑀𝑡𝑐𝑎𝑟𝑟𝑦 + 2𝑁 𝑡𝑚𝑢𝑥 + 𝑡𝑠𝑢𝑚

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 Square Root Carry-Select Adder
𝑁 𝐵𝑖𝑡 𝑎𝑑𝑑𝑒𝑟, 𝑀 − 𝐵𝑖𝑡𝑠 𝑖𝑛 𝐹𝑖𝑟𝑠𝑡 𝑆𝑡𝑎𝑔𝑒 , 𝑃 − 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑆𝑡𝑎𝑔𝑒𝑠

𝑁 = 𝑀 + 𝑀 + 1 + 𝑀 + 2 + 𝑀 + 3 + ⋯ . +(𝑀 + 𝑃 − 1)

Series: a, a+d, a+2d,……,a+(n-1)d

𝑃(𝑃 − 1)
𝑁 = 𝑀𝑃 + sn = n/2(2a + (n-1)d)
2
𝑃 2 1
𝑁= + 𝑃(𝑀 − )
2 2

𝑀 ≪ 𝑁 𝑒. 𝑀 = 2 𝑎𝑛𝑑 𝑁 = 64

𝑃2
𝑁≈
2

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 Carry Save Adder

X: 1001 :9
Y: 1001 :9
Z: 1 0 1 1 : 11
S: 1011
C: 1001
Sum: 1 1 1 0 1 : 29

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 Serial Adder
Initialize to
0

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 Serial Adder
Initialize to
0

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 6T SRAM

Write bit bit_b

word
➢ Drive one bitline high, the other low P1 P2
N2 N4
➢ Then turn on wordline
➢ Bitlines overpower cell with new value A A_b
N1 N3
➢ Writability
➢Must overpower feedback inverter
A_b
➢N2 >> P1
1.5 A

Ex: A = 0, A_b = 1, bit_b

1.0
bit = 1, bit_b = 0
Force A_b low, then A rises high
0.5
word

0.0
0 100 200 300 400 500 600 700
time (ps)

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 3-Transistor DRAM Cell

No constraints on device ratios Reads are non-destructive

Value stored at node X when writing a “1” = VWWL-VTn

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 1-Transistor DRAM Cell

Write: CS is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV

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 MOS OR ROM

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 MOS NOR ROM

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 MOS NAND ROM

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 Thank you

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