DEPARTMENT OF COMPUTER & SOFTWARE

ENGINEERING
COLLEGE OF E&ME, NUST, RAWALPINDI

Subject Name
Logic and Sequential Circuit Design

PROJECT REPORT

SUBMITTED TO:
Dr Soyiba

SUBMITTED BY:
Students Name
1. Muhammad Mussa Kazim -404047
2. Sikandar Hussain -405410
3. Osaid Amjad -410196

DE- 44 Dept C&SE

Syn-A
Submission Date:
14th Jan, 2023
 Project Name:
Digital Stopwatch Design

Project Components:
Anodic 7 Segments (x4)
7447 ICs (x4)
74192 ICs (x4)
NOT GATES (x2)
RESISTOR 56,10K, 22k, 100k, 220(x28) Ohms
Capacitors (x3)
1 PUSH BUTTON
1 SWITCH
AND IC (x1), OR IC (x1)
Breadboard and Wires
Verilog Compiler

Working Principle:
A digital stopwatch made using integrated circuits (ICs) and logic gates relies on the principles of
digital electronics to measure and display elapsed time. Here is a simplified explanation of the
working principle:
Clock Pulse Generation: The stopwatch uses a stable clock signal as its timing reference. The
clock signal is used to synchronize the entire stopwatch circuit.
Counter Circuit: The heart of the stopwatch is a counter circuit. The counter increments its count
at each clock pulse. The count represents the elapsed time in some time unit.
Decoding and Segmentation: The count from the counter is then decoded to drive the seven-
segment displays. Decoders and display drivers are used to convert the binary count into signals
that can drive the individual segments of the seven-segment displays.
User Interface and Control Logic: The stopwatch typically has buttons for starting, stopping, and
resetting the timer. These buttons are connected to the control logic, which interprets the user's
input and controls the operation of the stopwatch. Flip-flops, gates, and other digital components
are used for this purpose.
Display: The elapsed time is shown on the seven-segment displays. These displays consist of seven
LEDs arranged in the shape of the numeral "8". Each segment can be individually lit to represent
different digits.
Power Supply and Reset Circuit: The stopwatch needs a stable power supply to operate.
Additionally, a reset circuit ensures that the stopwatch starts from zero when the user initiates a
reset operation.

Simulations Using Proteus:

RESET BUTTON
And/Not Logic:
Whenever the right most Segment moves to Nine, after that, the displays to the right increments
by One. Similarly, when the time reaches 60 seconds, the Displays on the left get incremented
and they behave in similar manner. This is done using NOT Gates and AND Gates.
Similarly, The Second IC Resets to 0 after reaching 6 in Binary because at 60 seconds, a minute
passes. This Reset Logic is applied Via combining the previous Gates with OR Gate.

1 Hz Pulse Generation Using 555 Timer IC:

Basically, we need to generate a 1Hz Pulse which is basically produces a high pulse after every
second. We are using a 555 Timer IC to generate a 1 second pulse. Alongside the 555 Timer IC,
we have used 2 Resistors and 3 Capacitors of appropriate values to generate the desired pulse.
The calculations for their values are given as follows:
Simulation Picture:

Hardware Implementation:
Hardware Implementation of this part of Circuit is given below:
74192 SYNCHRONOUS UP/DOWN DECADE COUNTER:
The output from the 1 Hz clock goes into the Pin 5 of the 74192 IC. Whenever the input at the
Pin 5 goes to ‘1’ from the clock. The output is incremented by one in a 4 bit Binary Number at
the Output Pins ‘QA, QB, QC, QD’.
Why is it called a decade counter:
This IC is called a Decade counter because after it counts up to 9 (1001 in Binary), The Carry
Output next generates a ‘1’ and the Counter goes back to 0.

Carry Logic:
The Count Up Pin of the First 74192 IC receives the input from the clock and it counts up to 9
in Binary according to the 1 second pulse of the clock. After 9, the output becomes 0 and a 1 is
generated at the Carry Output Pin. Now the second 74192 IC receives this Carry Output of the
first pin as an input to its Count up Pin, So whenever the first IC counts up to 9, the second IC
adds 1 to its output.
The third IC has to count by 1 whenever a minute passes by, so whenever the second IC counts
up to 6, the third IC should add 1 to its output. This is done by the logic that whenever the
second IC generates 6, that is 0110 at its output, these 4 outputs are put into an AND Gate with
the first and last bit passed through a NOT Gate. This produces a ‘1’ whenever the output is 6 in
Binary. This 1 is given to the Count Up Pin of the Third IC. Also whenever a 6 is generated, the
second IC should reset back to 0, so we trigger the Reset Pin whenever the second IC generates
a 6 in Binary.
The fourth IC receives the Carry Output of the third IC as an input to its Count Up Pin, similar
to the first and second IC.
Verilog Code of 74192 IC:
Behavioral Code:
module DDecade_counter(
input wire en, clock, load, up_down,
output reg [3:0] count
);

always @(posedge clock) begin

if (en) begin
if (load) begin
count <= 4'd0; // Load condition, reset the counter
end else begin
if (up_down) begin
// Up-count condition
if (count == 4'd9)
count <= 4'd0;
else
count <= count + 4'd1;
end else begin
// Down-count condition
if (count == 4'd0)
count <= 4'd9;
 else
count <= count - 4'd1;
end
end
end
end
endmodule

TestBench:
module decadecounter_tb;
reg en, clock, load, up_down;
wire [3:0] count;

DDecade_counter dut (
.en(en),
.clock(clock),
.load(load),
.up_down(up_down),
.count(count)
);
initial begin
$display($time, " << Starting the Simulation >>");
en = 1'b0;
clock = 1'b0;
load = 1'b1;
up_down = 1'b0;

#100 en = 1'b1;
#100 load = 1'b0;
#100 up_down = 1'b1;
end
 always #100 clock = ~clock;
endmodule

Output:

7447 IC:
The output from the Precious IC is put into the ‘A, B, C, D’ inputs of the 7447 IC which is a
BCD to Seven Segment Decoder IC.

It gives out 7 outputs according to the Seven Segments of the Anodic 7 Segment Display.

Other Pins:
- LT (Lamp Test): The LT (Lamp Test) pin on the 7447 IC enables a test mode, allowing the
user to check the functionality of the display lamps.
- RBI (Ripple Blanking Input): RBI (Ripple Blanking Input) is used to inhibit ripple blanking,
preventing the blanking of the display during certain operations.
- RBO (Ripple Blanking Output): RBO (Ripple Blanking Output) provides a ripple blanking
output, facilitating the cascading of multiple 7447 ICs by synchronizing the blanking signals.

Gate Level Implementation of 7447 IC:

Truth Table:

Verilog Code:
Gate Level Implementation:
module SevenSegDecoder(A,B,C,D,BI_RBO,LT,RBI,a,b,c,d,e,f,g);
input A,B,C,D,LT,RBI;
output a,b,c,d,e,f,g;
inout BI_RBO;

wire Awire1,Bwire1,Cwire1,Dwire1,LTwire;

assign LTwire = ~(~LT);

assign Awire1 = ~(A&LTwire);
assign Bwire1 = ~(B&LTwire);
assign Cwire1 = ~(C&LTwire);
assign Dwire1 = ~D;

wire BiRboWire;

assign BiRboWire = ~(~BI_RBO);

wire Awire2,Bwire2,Cwire2,Dwire2;

assign Awire2 = ~(Awire1&BiRboWire);

assign Bwire2 = ~(Bwire1&BiRboWire);
assign Cwire2 = ~(Cwire1&BiRboWire);
assign Dwire2 = ~(Dwire1&BiRboWire);

wire
And1,And2,And3,And4,And5,And6,And7,And8,And9,And10,And11,And12,And13,And14,And15,And16,
And17;
wire Buffer1;

wire RbiWire;
assign RbiWire = ~RBI;

assign BI_RBO = ~(RbiWire & LTwire & Dwire1 & Cwire1 & Bwire1 & Awire1);

assign And1 = Bwire2 & Dwire2;

assign And2 = Awire1 & Cwire2;
assign And3 = Awire2 & Bwire1 & Cwire1 & Dwire1;
assign And4 = Bwire2 & Dwire2;
assign And5 = Awire2 & Bwire1 & Cwire2;
assign And6 = Awire1 & Bwire2 & Cwire2;
assign And7 = Cwire2 & Dwire2;
assign And8 = Awire1 & Bwire2 & Cwire1;
assign And9 = Awire2 & Bwire1 & Cwire1;
assign And10 = Awire1 & Bwire1 & Cwire2;
assign And11 = Awire2 & Bwire2 & Cwire2;
assign And12 = Bwire1 & Cwire2;
assign And13 = Awire2 & Bwire2;
assign And14 = Bwire2 & Cwire1;
assign And15 = Awire2 & Cwire1 & Dwire1;
assign And16 = Awire2 & Bwire2 & Cwire2;
assign And17 = Bwire1 & Cwire1 & Dwire1 & LTwire;

assign Buffer1 = Awire2;

wire Nor1,Nor2,Nor3,Nor4,Nor5,Nor6,Nor7;
wire Notn1,Notn2,Notn3,Notn4,Notn5,Notn6,Notn7;

assign Nor1 = ~(And1|And2|And3);

assign Nor2 = ~(And4|And5|And6);
assign Nor3 = ~(And7|And8);
assign Nor4 = ~(And9|And10|And11);
assign Nor5 = ~(Buffer1|And12);
assign Nor6 = ~(And13|And14|And15);
assign Nor7 = ~(And16|And17);

assign Notn1 = ~(Nor1);

assign Notn2 = ~(Nor2);
assign Notn3 = ~(Nor3);
assign Notn4 = ~(Nor4);
assign Notn5 = ~(Nor5);
assign Notn6 = ~(Nor6);
assign Notn7 = ~(Nor7);

assign a = Notn1;
assign b = Notn2;
assign c = Notn3;
assign d = Notn4;
assign e = Notn5;
assign f = Notn6;
assign g = Notn7;

endmodule

TestBench:
module SevenSegDecoder_TestBench;
reg A,B,C,D,LT,RBI;
wire BI_RBO;
wire a,b,c,d,e,f,g;
SevenSegDecoder
uut(.A(A),.B(B),.C(C),.D(D),.BI_RBO(BI_RBO),.LT(LT),.RBI(RBI),.a(a),.b(b),.c(c),.d(d),.e(e),.f(f),.g(g));

initial begin
LT=1;RBI=1;
#5;

A=0;B=0;C=0;D=0;
#100;

D=0;C=0;B=0;A=1;
#100;

D=0;C=0;B=1;A=0;
#100;

D=0;C=0;B=1;A=1;
#100;

D=0;C=1;B=0;A=0;
#100;

D=0;C=1;B=0;A=1;
#100;

D=0;C=1;B=1;A=0;
#100;

D=0;C=1;B=1;A=1;
#100;
D=1;C=0;B=0;A=0;
#100;

D=1;C=0;B=0;A=1;
#100;

end
endmodule

Output:

All Results Agreed with the Truth Table Provided Above.

Anodic Seven Segment:
Outputs from the 7447 IC is put into an Anodic Seven Segment which displays the numbers.

All the Segments which are given a Low Input light up. The Anodic Seven Segment is given a
Common Vcc as shown in the figure.

Hardware Implementation and Result:

We have been able to achieve a working Stopwatch with Reset and Stop Buttons Included. Our
Project has been completed within the time assigned to us and is in working condition. Working
Project Pictures are shared below:
 Conclusion:
In conclusion, our digital stopwatch project, using the 74192 IC and seven segments, seamlessly
integrates hardware and software. The success of Proteus Simulations validates our circuit
design. This project not only deepens our understanding of digital circuits but also highlights its
real-world applicability for accurate time measurement. With the successful Proteus
Simulations, Verilog Codes and Hardware Implementation, we have completed out project
timely. The collaborative efforts of our three-member team have proven instrumental, and we
have completed our work in due time.