TS6566

MCP6566/6R/6U/7/9
1.8V Low-Power Open-Drain Output Comparator

Features: Description:
• Propagation Delay at 1.8VDD: The Microchip Technology, Inc. MCP6566/6R/6U/7/9
- 56 ns (typical) High-to-Low families of open-drain output comparators are offered
• Low Quiescent Current: 100 µA (typical) in single, dual and quad configurations.
• Input Offset Voltage: ±3 mV (typical) These comparators are optimized for low-power 1.8V,
• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V single-supply applications with greater than rail-to-rail
input operation. The internal input hysteresis eliminates
• Open-Drain Output
output switching due to internal input noise voltage,
• Wide Supply Voltage Range: 1.8V to 5.5V reducing current draw. The open-drain output of the
• Available in Single, Dual and Quad MCP6566/6R/6U/7/9 family requires a pull-up resistor
• Packages: SC70, SOT-23-5, SOIC, MSOP, and it supports pull-up voltages above and below VDD,
TSSOP which can be used to level shift. The output toggle
frequency can reach a typical of 4 MHz (typical) while
Typical Applications: limiting supply current surges and dynamic power
consumption during switching.
• Laptop Computers
This family operates with single supply voltage of 1.8V
• Mobile Phones to 5.5V while drawing less than 100 µA/comparator of
• Hand-held Electronics quiescent current (typical).
• RC Timers
• Alarm and Monitoring Circuits Package Types
• Window Comparators MCP6566 MCP6567
• Multivibrators SOT-23-5, SC70-5 SOIC, MSOP
OUT 1 5 VDD OUTA 1 8 VDD
Design Aids: VSS 2 -INA 2 - + 7 OUTB
+
-
• Microchip Advanced Part Selector (MAPS) +IN 3 4 -IN +INA 3 + - 6 -INB

• Analog Demonstration and Evaluation Boards VSS 4 5 +INB
• Application Notes
MCP6566R MCP6569
SOT-23-5 SOIC, TSSOP
Related Device:
OUT 1 5 VSS OUTA 1 14 OUTD
• Push-Pull Output: MCP6561/1R/1U/2/4 VDD 2 -INA 2 - + + - 13 -IND
+
-
+IN 3 4 -IN +INA 3 12 +IND

Typical Application VDD 4 11 VSS
+3VPU MCP6566U +INB 5 10 +INC
SOT-23-5 - + + -
+5VDD -INB 6 9 -INC
VIN
VIN+ 1 + 5 VDD OUTB 7 8 OUTC
VOUT VSS 2 -
VDD VIN– 3
MCP656X 4 OUT
R2
RF
R3
 2009-2013 Microchip Technology Inc. DS22143D-page 1

MCP6566/6R/6U/7/9
NOTES:
DS22143D-page 2  2009-2013 Microchip Technology Inc.

MCP6566/6R/6U/7/9
1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
CHARACTERISTICS a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
1.1 Maximum Ratings † operational listings of this specification is not implied. Expo-
VDD - VSS ....................................................................... 6.5V sure to maximum rating conditions for extended periods may
affect device reliability.
Open-Drain Output.............................................VSS + 10.5V
†† See Section 4.1.2 “Input Voltage and Current Limits”
All other inputs and outputs...........VSS – 0.3V to VDD + 0.3V
Analog Input (VIN) †† .....................VSS - 1.0V to VDD + 1.0V
Difference Input voltage ......................................|VDD - VSS|
Output Short Circuit Current .................................... ±25 mA
Current at Input Pins .................................................. ±2 mA
Current at Output and Supply Pins .......................... ±50 mA
Storage temperature ................................... -65°C to +150°C
Ambient temp. with power applied .............. -40°C to +125°C
Junction temp............................................................ +150°C
ESD protection on all pins (HBM/MM)4 kV/300V
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN- = VSS,
and RPull-Up = 20 k to VPU = VDD (see Figure 1-1).
Parameters Symbol Min Typ Max Units Conditions
Power Supply
Supply Voltage VDD 1.8 — 5.5 V
Quiescent Current per comparator IQ 60 100 130 µA IOUT = 0
Power Supply Rejection Ratio PSRR 63 70 — dB VCM = VSS
Input
Input Offset Voltage VOS -10 3 +10 mV VCM = VSS (Note 1)
Input Offset Drift VOS/T — 2 — µV/°C VCM = VSS
Input Offset Current IOS — 1 — pA VCM = VSS
Input Bias Current IB — 1 — pA TA = +25°C, VIN- = VDD/2
— 60 — pA TA = +85°C, VIN- = VDD/2
— 1500 5000 pA TA = +125°C, VIN- = VDD/2
Input Hysteresis Voltage VHYST 1.0 — 5.0 mV VCM = VSS (Notes 1, 2)
Input Hysteresis Linear Temp. Co. TC1 — 10 — µV/°C
Input Hysteresis Quadratic Temp. Co. TC2 — 0.3 — µV/°C2
Common-Mode Input Voltage Range VCMR VSS0.2 — VDD+0.2 V VDD = 1.8V
VSS0.3 — VDD+0.3 V VDD = 5.5V
Common-Mode Rejection Ratio CMRR 54 66 — dB VCM= -0.3V to VDD+0.3V, VDD = 5.5V
50 63 — dB VCM= VDD/2 to VDD+0.3V, VDD = 5.5V
54 65 — dB VCM= -0.3V to VDD/2, VDD = 5.5V
Common Mode Input Impedance ZCM — 1013||4 — ||pF
Differential Input Impedance ZDIFF — 1013||2 — ||pF
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
2: VHYST at different temperatures is estimated using VHYST (TA) = VHYST @ +25°C + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
3: Limit the output current to Absolute Maximum Rating of 50 mA.
4: The pull-up voltage for the open drain output VPULL_UP can be as high as the absolute maximum rating of 10.5V. In this
case, IOH_leak can be higher than 1 µA (see Figure 2-30).

MCP6566/6R/6U/7/9
DC CHARACTERISTICS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN- = VSS,
and RPull-Up = 20 k to VPU = VDD (see Figure 1-1).
Push-Pull Output
Pull-up Voltage VPULL_UP 1.6 — 5.5 V
High-Level Output Voltage VOH — — VPULL_UP V (see Figure 1-1) (Notes 3, 4)
High-Level Output Current Leakage IOH_leak — — 1 µA Note 4
Low-Level Output Voltage VOL — — 0.6 V IOUT = 3 mA/8 mA @ VDD = 1.8V/5.5V
Short Circuit Current (Notes 3) ISC — ±30 — mA Not to exceed Absolute Max. Rating
Output Pin Capacitance COUT — 8 — pF
Note 1: The input offset voltage is the center of the input-referred trip points. The input hysteresis is the difference between the
input-referred trip points.
2: VHYST at different temperatures is estimated using VHYST (TA) = VHYST @ +25°C + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
3: Limit the output current to Absolute Maximum Rating of 50 mA.
4: The pull-up voltage for the open drain output VPULL_UP can be as high as the absolute maximum rating of 10.5V. In this
case, IOH_leak can be higher than 1 µA (see Figure 2-30).
AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated,: Unless otherwise indicated,: VDD = +1.8V to +5.5V, VSS = GND,
TA = +25°C, VIN+ = VDD/2, VIN- = VSS, RPull-Up = 20 k to VPU = VDD, and CL = 25 pf (see Figure 1-1).
Propagation Delay
High-to-Low,100 mV Overdrive tPHL — 56 80 ns VCM= VDD/2, VDD = 1.8V
— 34 80 ns VCM= VDD/2, VDD = 5.5V
Output
Fall Time tF — 20 — ns
Maximum Toggle Frequency fTG — 4 — MHz VDD = 5.5V
— 2 — MHz VDD = 1.8V
Input Voltage Noise ENI — 350 — µVP-P 10 Hz to 10 MHz (Note 1)
Note 1: ENI is based on SPICE simulation.
2: Rise time tR and tPLH depend on the load (RL and CL). These specification are valid for the specified load only.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V and VSS = GND.
Temperature Ranges
Specified Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, SC70-5 JA — 331 — °C/W
Thermal Resistance, SOT-23-5 JA — 220.7 — °C/W
Thermal Resistance, 8L-MSOP JA — 211 — °C/W
Thermal Resistance, 8L-SOIC JA — 149.5 — °C/W
Thermal Resistance, 14L-SOIC JA — 95.3 — °C/W
Thermal Resistance, 14L-TSSOP JA — 100 — °C/W

MCP6566/6R/6U/7/9
1.2 Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
VDD MCP656X
VPU = VDD
200 k RPU
IOUT 20 k
200 k VOUT
25 pF
VIN = VSS
VSS = 0V
FIGURE 1-1: AC and DC Test Circuit for

the Open-Drain Output Comparators.

MCP6566/6R/6U/7/9
NOTES:

MCP6566/6R/6U/7/9
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN – = GND,
RL = 20 k to VPU = VDD , and CL = 25 pF.
50% 30%
VDD = 1.8V VDD = 5.5V VDD = 1.8V VDD = 5.5V
VCM = VSS VCM = VSS 25% Avg. = 3.4 mV Avg. = 3.6 mV
40% StDev = 0.2 mV StDev = 0.1 mV
Occurrences (%)
Occurrences (%)
Avg. = -0.1 mV Avg. = -0.9 mV

3588 units 3588 units
StDev = 2.1 mV StDev = 2.1 mV 20%
30% 3588 units 3588 units
15%
20%
10%
10% 5%
0% 0%
-10 -8 -6 -4 -2 0 2 4 6 8 10 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VOS (mV) VHYST (mV)
FIGURE 2-1: Input Offset Voltage. FIGURE 2-4: Input Hysteresis Voltage.
60% 60%
VCM = VSS
VDD = 5.5V VDD = 1.8V
50% Avg. = 0.9 µV/°C 50%
Avg. = 12 µV/°C
Occurrences (%)
Occurrences (%)
StDev = 6.6 µV/°C Avg. = 10.4 µV/°C

1380 Units StDev = 0.6 µV/°C StDev = 0.6 µV/°C
40% 40%
TA = -40°C to +125°C
30% 30%
20% 20%
1380 Units
10% 10% TA = -40°C to 125°C
VCM = VSS
0% 0%
-60 -48 -36 -24 -12 0 12 24 36 48 60 0 2 4 6 8 10 12 14 16 18 20
VOS Drift (µV/°C) VHYST Drift, TC1 (µV/°C)
FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-5: Input Hysteresis Voltage
Drift - Linear Temp. Co. (TC1).
7.0
VDD = 5.5V VIN+ = VDD /2 30%
6.0
VDD = 5.5V VDD = 1.8V
Occurrences (%)
5.0 Avg. = 0.25 µV/°C2 Avg. = 0.3 µV/°C

2
VIN - VOUT 20% StDev = 0.1 µV/°C

2
StDev = 0.2 µV/°C 2
4.0
VOUT (V)
3.0
10% 1380 Units
2.0
TA = -40°C to +125°C
1.0 VCM = VSS
0.0
0%
-1.0 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00
Time (3 µs/div) VHYST Drift, TC2 (µV/°C2)
FIGURE 2-3: Input vs. Output Signal, No FIGURE 2-6: Input Hysteresis Voltage
Phase Reversal. Drift - Quadratic Temp. Co. (TC2).

MCP6566/6R/6U/7/9
3.0 5.0
VCM = VSS VCM = VSS
2.0 VDD = 1.8V
4.0 VDD= 5.0V
1.0
VHYST (mV)
V OS (mV)
0.0 3.0
-1.0
2.0 VDD= 1.8V
VDD = 5.5V
-2.0
-3.0 1.0
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Temperature (°C) Temperature (°C)
FIGURE 2-7: Input Offset Voltage vs. FIGURE 2-10: Input Hysteresis Voltage vs.
Temperature. Temperature.
4.0 5.0
VDD = 1.8V TA= +125°C
TA= +125°C
2.0 TA= +85°C 4.0
V HYST (mV)
VOS (mV)
0.0 3.0
TA= +25°C
TA= -40°C
TA= +25°C
-2.0 2.0
TA= +85°C
VDD = 1.8V TA= -40°C
-4.0 1.0
-0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 -0.3 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1
VCM (V) VCM (V)
Common-mode Input Voltage. Common-mode Input Voltage.
3.0 5.0
VDD = 5.5V
2.0
TA= -40°C
4.0
1.0
V HYST (mV)
VOS (mV)
TA= +25°C
0.0 3.0
-1.0 TA= -40°C

2.0 TA= +25°C
TA= +85°C
-2.0 TA= +85°C
TA= +125°C TA= +125°C VDD = 5.5V
-3.0 1.0
-1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 -0.5 0.5 1.5 2.5 3.5 4.5 5.5
VCM (V) VCM (V)

MCP6566/6R/6U/7/9
3.0 5.0
TA= +125°C
2.0 TA= +85°C
4.0
TA= -40°C
1.0
V HYST (mV)
TA= +25°C
VOS (mV)
TA= +25°C
TA= +85°C
0.0 3.0
TA= +125°C TA= -40°C
-1.0
2.0
-2.0
-3.0 1.0
1.5 2.5 3.5 4.5 5.5 1.5 2.5 3.5 4.5 5.5
VDD (V) VDD (V)
Supply Voltage vs. Temperature. Supply Voltage vs. Temperature.
50% 140.0
VDD = 1.8V VDD = 5.5V 120.0
40% Avg. = 97 µA
Occurrences (%)
Avg. = 88 µA
StDev= 4 µA StDev= 4 µA 100.0
1794 units
30% 1794 units
80.0
IQ (µA)
20% 60.0 TA= -40°C
40.0 TA= +25°C
10% TA= +85°C
20.0 TA= +125°C
0% 0.0
60 70 80 90 100 110 120 130 0.0 1.0 2.0 3.0 4.0 5.0 6.0
IQ (µA) V DD (V)
FIGURE 2-14: Quiescent Current. FIGURE 2-17: Quiescent Current vs.

Supply Voltage vs Temperature.
130 130
VDD = 1.8V VDD = 5.5V
120 120
110 110 Sweep VIN+ ,VIN - = VDD/2
100
IQ (µA)
100
IQ (µA)
Sweep VIN+ ,VIN - = VDD/2
90 90
Sweep VIN - ,VIN+ = VDD/2
80 Sweep VIN- ,VIN+ = VDD /2 80
V /2
70 70
60 60
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
VCM (V) VCM (V)
FIGURE 2-15: Quiescent Current vs. FIGURE 2-18: Quiescent Current vs.

MCP6566/6R/6U/7/9
150 150
IDD Spike near VPU = 0.9V VDD = 5.5 V
VDD = 5.5V VDD = 4.5 V

125 VDD = 4.5V
125 VDD = 3.5 V
VDD = 3.5V
IQ (µA)
IQ (µA)
100 100
VDD = 2.5V VDD = 2.5 V

75 75
VDD = 2.0V VDD = 2.0 V
VDD = 1.8V
VDD = 1.8 V
50 50
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 -4.5 -2.5 -0.5 1.5 3.5 5.5 7.5 9.5
V PU (V) VPU - V DD (V)
FIGURE 2-19: Quiescent Current vs. FIGURE 2-22: Quiescent Current vs.
Pull-up Voltage. Pull-up to Supply Voltage Difference.
400 100,000
100 mV Over-Drive 0dB Output Attenuation TA =
350 VCM = VDD/2
RL = Open 10,000
300 VDD = 5.5V
IOH_leak (pA)
1,000
250
IQ (µA)
TA = +85°C
200 100 TA = +25°C
VDD = 1.8V
150
10
100
1
50
10 100 1k 10k 100000
100k 100000
1M 10M 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5
10 100 1000 10000 1E+07
Toggle Frequency (Hz) 0 VPU (V)
FIGURE 2-20: Quiescent Current vs. FIGURE 2-23: Output Leakage Current vs.
Toggle Frequency. Pull-up Voltage.
1000 1000
VDD= 1.8V VDD= 5.5V
800 800
TA = +125°C
125°C
TA = +85°C
VOL (mV)
VOL (mV)
600 600
TA = +25°C
TA = -40°C
400 TA = +125°C 400
TA = +85°C
TA = +25°C
200 TA = -40°C 200
0 0
0.0 3.0 6.0 9.0 12.0 15.0 0 5 10 15 20 25
IOUT (mA) IOUT (mA)
FIGURE 2-21: Output Headroom vs Output FIGURE 2-24: Output Headroom Vs Output
Current. Current.

MCP6566/6R/6U/7/9
50% 50%
VDD = 1.8V VDD= 5.5V
tPHL
100 mV Over-Drive 100mV Over-Drive
40% VCM = VDD /2 40% Avg. = 33 ns VCM = VDD/2
Occurrences (%)
Occurrences (%)
StDev= 1 ns
tPHL
198 units
30% Avg. = 54.4 ns 30%
StDev= 2 ns
198 units
20% 20%
10% 10%
0% 0%
30 35 40 45 50 55 60 65 70 75 80 30 35 40 45 50 55 60 65 70 75 80
Prop. Delay (ns) Prop. Delay (ns)
FIGURE 2-25: High-to-Low Propagation FIGURE 2-28: High-to-Low Propagation

Delays. Delays.
260 80
VCM = VDD/2 100 mV Over-Drive
70 VCM = VDD/2
210
Prop. Delay (ns)
Prop. Delay (ns)

tPHL , VDD = 1.8V
60
160 tPHL , VDD = 1.8V
50
110 tPHL , VDD = 5.5V
40
60 30
tPHL , VDD = 5.5V
10 20
1 10 100 1000 -50 -25 0 25 50 75 100 125
Over-Drive (mV) Temperature (°C)
FIGURE 2-26: Propagation Delay vs. Input FIGURE 2-29: Propagation Delay vs.
Over-Drive. Temperature.
120
140 TA= -40°C
VCM = VDD /2 TA= +25°C
80
120 TA= +85°C
Prop. Delay (ns)
TA= +125°C
100 40
ISC (mA)
tPHL , 10 mV Over-Drive
80 0
60 -40 TA= -40°C

tPHL , 100 mV Over-Drive
TA= +25°C
40 -80 TA= +85°C
TA= +125°C
20 -120
1.5 2.5 3.5 4.5 5.5 0.0 1.0 2.0 3.0 4.0 5.0 6.0
V DD (V) VDD (V)
FIGURE 2-27: Propagation Delay vs. FIGURE 2-30: Short Circuit Current vs.
Supply Voltage. Supply Voltage vs. Temperature.

MCP6566/6R/6U/7/9
80 80
VDD= 1.8V
70 70 VDD= 5.5V
100 mV Over-Drive
100 mV Over-Drive
Prop. Delay (ns)
Prop. Delay (ns)

tPHL
60 60
tPHL
50 50
40 40
30 30
20 20
0.00 0.50 1.00 1.50 2.00 0.0 1.0 2.0 3.0 4.0 5.0 6.0
VCM (V) VCM (V)
FIGURE 2-31: Propagation Delay vs. FIGURE 2-34: Propagation Delay vs.
1000 10000
100mV Over-Drive 100 mV Over-Drive
VCM = VDD /2 VCM = VDD/2
100
VDD = 1.8V, tPHL
Prop. Delay (µs)
Prop. Delay (ns) 1000 tPLH

10
VDD = 5.5V, tPHL
tPHL
1
100
0.1
0.01 10
0.001
1 0.01
10 0.1
100 1
1000 10
10000 100 1E+06
100000 1000 0.1 1.0 10.0 100.0
Capacitive Load (nf) RPU (kΩ)
FIGURE 2-32: Propagation Delay vs. FIGURE 2-35: Propagation Delay vs.
Capacitive Load. Pull-up Resistor.
10m
1E+11 10000
100 mV Over-Drive
VCM = VDD /2
1E+09
1m
Input Current (A)
Prop. Delay (ns)
tPLH, VDD = 5.5V

10µ
1E+07 1000
100n
1E+05 TA= -40°C tPLH, VDD = 1.8V
TA= +25°C
1n TA= +85°C tPHL, VDD = 1.8V
1E+03 100
TA= +125°C
10p
1E+01
tPLH, VDD = 5.5V
0.1p
1E-01 10
-0.8 -0.6 -0.4 -0.2 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V) V PU (V)
FIGURE 2-33: Input Bias Current vs. Input FIGURE 2-36: Propagation Delay vs.
Voltage vs Temperature. Pull-up Voltage.

MCP6566/6R/6U/7/9
80 30%
Input Referred VCM = VDD/2 to VDD+ 0.2V VCM = -0.2V to VDD + 0.2V
Avg. = 0.7 mV Avg. = 0.6 mV
78 VCM = VSS StDev= 0.1 mV
CMRR/PSRR (dB)
StDev= 1 mV
Occurrences (%)
VDD = 1.8V to 5.5V
20%
76 PSRR
VCM = -0.2V to VDD /2
74 Avg. = 0.5 mV
CMRR 10% StDev= 0.1 mV VDD = 1.8V
3588 units
72 VCM = -0.3V to VDD + 0.3V
VDD = 5.5V
70 0%
-50 -25 0 25 50 75 100 125 -5 -4 -3 -2 -1 0 1 2 3 4 5
Temperature (°C) CMRR (mV/V)
FIGURE 2-37: Common-mode Rejection FIGURE 2-40: Common-mode Rejection

Ratio and Power Supply Rejection Ratio vs. Ratio (CMRR).
Temperature.
30% 30%
VCM = VSS VCM = VDD/2 to VDD+ 0.3V V CM = -0.3V to V DD + 0.3V
Avg. = 200 µV/V Avg. = 0.03 mV Avg. = 0.1 mV
25% StDev= 0.7 mV StDev= 0.4 mV
StDev= 94 µV/V
Occurrences (%)
Occurrences (%)
3588 units
20% 20%
15% VCM = -0.3V to VDD/2

Avg. = 0.2 mV
10% 10% StDev= 0.4 mV VDD = 5.5V
3588 units
5%
0% 0%
-600 -400 -200 0 200 400 600 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
PSRR (µV/V) CMRR (mV/V)
FIGURE 2-38: Power Supply Rejection FIGURE 2-41: Common-mode Rejection

Ratio (PSRR). Ratio (CMRR).
1000 10000
IB @ TA= +125°C VDD = 5.5V
1000
100 IB @ TA= +85°C
100
IOS and IB (pA)
IOS and IB (pA)
IB
10
10
1
|IOS| @ TA= +125°C
1 0.1
|I OS|
0.01 |IOS|@ TA= +85°C
0.1 0.001
25 50 75 100 125 0 1 2 3 4 5 6
Temperature (°C) V CM (V)
FIGURE 2-39: Input Offset Current and FIGURE 2-42: Input Offset Current and
Input Bias Current vs. Temperature. Input Bias Current vs. Common-mode Input
Voltage vs. Temperature.

MCP6566/6R/6U/7/9
10000
VDD = 5.5V
Output Jitter pk-pk (ns)
1000 VIN+ = 2Vpp (sine)
100
10
0.1
100
100 1k
1000 10k
10000 100k
100000 1M
100000 10M
1E+07
Input Frequency (Hz) 0
FIGURE 2-43: Output Jitter vs. Input

Frequency.

MCP6566/6R/6U/7/9
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE

MCP6566 MCP6566R MCP6566U MCP6567 MCP6569
SC70-5, MSOP, SOIC, Symbol Description
SOT-23-5 SOT-23-5
SOT-23-5 SOIC TSSOP
1 1 5 1 1 OUT, OUTA Digital Output (comparator A)
4 4 3 2 2 VIN–, VINA– Inverting Input (comparator A)
3 3 1 3 3 VIN+, VINA+ Non-inverting Input (comparator A)
5 2 4 8 4 VDD Positive Power Supply
— — — 5 5 VINB+ Non-inverting Input (comparator B)
— — — 6 6 VINB– Inverting Input (comparator B)
— — — 7 7 OUTB Digital Output (comparator B)
— — — — 8 OUTC Digital Output (comparator C)
— — — — 9 VINC– Inverting Input (comparator C)
— — — — 10 VINC+ Non-inverting Input (comparator C)
2 5 2 4 11 VSS Negative Power Supply
— — — — 12 VIND+ Non-inverting Input (comparator D)
— — — — 13 VIND– Inverting Input (comparator D)
— — — — 14 OUTD Digital Output (comparator D)
3.1 Analog Inputs 3.3 Power Supply (VSS and VDD)

The comparator non-inverting and inverting inputs are The positive power supply pin (VDD) is 1.8V to 5.5V
high-impedance CMOS inputs with low bias currents. higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
3.2 Digital Outputs between VSS and VDD.
Typically, these parts are used in a single (positive)
The comparator outputs are CMOS, open-drain digital
supply configuration. In this case, VSS is connected to
outputs. They are designed to make level shifting and
ground and VDD is connected to the supply. VDD will
wired-OR easy to implement.
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These can share a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.

MCP6566/6R/6U/7/9
NOTES:

MCP6566/6R/6U/7/9
4.0 APPLICATIONS INFORMATION 4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The MCP6566/6R/6U/7/9 family of open-drain output
comparators are fabricated on Microchip’s The ESD protection on the inputs can be depicted as
state-of-the-art CMOS process. They are suitable for a shown in Figure 4-2. This structure was chosen to
wide range of high speed applications requiring low- protect the input transistors, and to minimize input bias
power consumption. current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
4.1 Comparator Inputs
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
4.1.1 NORMAL OPERATION
events within the specified limits.
The input stage of this family of devices uses two
differential input stages in parallel. This configuration
provides three regions of operation, one operates at VDD Bond
low input voltages, one at high input voltages, and one Pad
at mid input voltage. With this topology, the input
voltage range is 0.3V above VDD and 0.3V below VSS,
while providing low offset voltage throughout the Bond Input Bond
common mode range. The input offset voltage is VIN+ VIN–
Pad Stage Pad
measured at both VSS - 0.3V and VDD + 0.3V to ensure
proper operation.
The MCP6566/6R/6U/7/9 family has internally-set
hysteresis VHYST that is small enough to maintain input VSS Bond
Pad
offset accuracy and large enough to eliminate output
chattering caused by the comparator’s own input noise FIGURE 4-2: Simplified Analog Input ESD
voltage ENI. Figure 4-1 depicts this behavior. Input Structures.
offset voltage (VOS) is the center (average) of the
(input-referred) low-high and high-low trip points. Input In order to prevent damage and/or improper operation
hysteresis voltage (VHYST) is the difference between of these amplifiers, the circuits they are in must limit the
the same trip points. currents (and voltages) at the VIN+ and VIN– pins (see
Section 1.1 “Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
8 25 shows the recommended approach to protecting these
VDD = 5.0V
7 20 inputs. The internal ESD diodes prevent the input pins
Input Voltage (10 mV/div)
6 VIN– 15 (VIN+ and VIN–) from going too far below ground, and
Output Voltage (V)
5 10 the resistors R1 and R2 limit the possible current drawn

4 VOUT 5
out of the input pin. Diodes D1 and D2 prevent the input
3 0
2 -5
pin (VIN+ and VIN–) from going too far above VDD.
Hysteresis When implemented as shown, resistors R1 and R2 also
1 -10
0 -15 limit the current through D1 and D2.
-1 -20
-2 -25
VDD
-3 -30 VPU
Time (100 ms/div)
D1 R4
FIGURE 4-1: The MCP6566/6R/6U/7/9 V1 +
comparators’ internal hysteresis eliminates VOUT
R1 MCP656X
output chatter caused by input noise voltage.
–
D2
V2
R2 R3
VSS – (minimum expected V1)
R1 
2 mA
VSS – (minimum expected V2)

R2 
2 mA
FIGURE 4-3: Protecting the Analog
Inputs.

MCP6566/6R/6U/7/9
It is also possible to connect the diodes to the left of the 4.3.1 NON-INVERTING CIRCUIT
resistors R1 and R2. In this case, the currents through
Figure 4-4 shows a non-inverting circuit for
the diodes D1 and D2 need to be limited by some other
single-supply applications using just two resistors. The
mechanism. The resistor then serves as in-rush current
resulting hysteresis diagram is shown in Figure 4-5.
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
VPU
A significant amount of current can flow out of the VDD
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 4-3. Applications that are VREF - RPU
high-impedance may need to limit the usable voltage
range. MCP656X VOUT
+
4.1.3 PHASE REVERSAL
The MCP6566/6R/6U/7/9 comparator family uses VIN
CMOS transistors at the input. They are designed to
R1 RF
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage FIGURE 4-4: Non-Inverting Circuit with
exceeding both supplies with no resulting phase Hysteresis for Single-Supply.
inversion.
4.2 Open-Drain Output VOUT

VDD
The open-drain output is designed to make
VOH
level-shifting and wired-OR logic easy to implement.
The output stage minimizes switching current High-to-Low Low-to-High
(shoot-through current from supply-to-supply) when
the output changes state. See Figures 2-15, 2-18, VOL VIN
2-35 and 2-36, for more information. VSS
VSS VTHL VTLH VDD
4.3 Externally Set Hysteresis
FIGURE 4-5: Hysteresis Diagram for the
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
Non-Inverting Circuit.
Hysteresis reduces output chattering when one input is The trip points for Figures 4-4 and 4-5 are:
slowly moving past the other. It also helps in systems
where it is best not to cycle between high and low EQUATION 4-1:
states too frequently (e.g., air conditioner thermostatic
control). Output chatter also increases the dynamic  R1   R1 
VTLH = V REF  1 + -------  – V OL ------- 
supply current.  R F RF 
 R1  R 1 
VTHL = V REF  1 + -------  – V OH ------- 
 RF  RF 
Where:
VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low

MCP6566/6R/6U/7/9
4.3.2 INVERTING CIRCUIT Where:
Figure 4-6 shows an inverting circuit for single-supply R2 R3
using three resistors. The resulting hysteresis diagram R 23 = -------------------
R2 + R3
is shown in Figure 4-7.
R3
VPU V 23 = -------------------  VDD
VDD R 2 + R3
VIN RPU Using this simplified circuit, the trip voltage can be
VDD calculated using the following equation:
MCP656X VOUT
EQUATION 4-2:
R2
 R 23  RF
V THL = V OH  ----------------------- + V 23  ----------------------
 23  
RF
R + R F R 23 + R F
R3
 R23  RF
V TLH = V OL  ----------------------- + V 23  ----------------------
 23
R + R F R 23 + R F
FIGURE 4-6: Inverting Circuit with Where:

Hysteresis. VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low
VOUT
VDD Figure 2-21 and Figure 2-24 can be used to determine
VOH typical values for VOH and VOL.
Low-to-High High-to-Low 4.4 Bypass Capacitors
VOL With this family of comparators, the power supply pin

VIN
VSS (VDD for single supply) should have a local bypass
VTLH VTHL VDD capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
VSS
edge rate performance.
FIGURE 4-7: Hysteresis Diagram for the
Inverting Circuit. 4.5 Capacitive Loads
In order to determine the trip voltages (VTHL and VTLH) Reasonable capacitive loads (e.g., logic gates) have
for the circuit shown in Figure 4-6, R2 and R3 can be little impact on propagation delay (see Figure 2-32).
simplified to the Thevenin equivalent circuit with The supply current increases with increasing toggle
respect to VDD, as shown in Figure 4-8. frequency (Figure 2-20), especially with higher
capacitive loads. The output slew rate and propagation
VPU delay performance will be reduced with higher
VDD capacitive loads.
RPU
-
MCP656X VOUT
+
VSS
V23
R23 RF
FIGURE 4-8: Thevenin Equivalent Circuit.

MCP6566/6R/6U/7/9
4.6 PCB Surface Leakage 4.7 PCB Layout Technique
In applications where low input bias current is critical, When designing the PCB layout, it is critical to note that
PCB (Printed Circuit Board) surface leakage effects analog and digital signal traces are adequately
need to be considered. Surface leakage is caused by separated to prevent signal coupling. If the comparator
humidity, dust or other contamination on the board. output trace is at close proximity to the input traces,
Under low humidity conditions, a typical resistance then large output voltage changes from, VSS to VDD or
between nearby traces is 1012. A 5V difference would visa versa, may couple to the inputs and cause the
cause 5 pA of current to flow. This is greater than the device output to oscillate. To prevent such oscillation,
MCP6566/6R/6U/7/9 family’s bias current at +25°C the output traces must be routed away from the input
(1 pA, typical). pins. The SC70-5 and SOT-23-5 are relatively immune
The easiest way to reduce surface leakage is to use a because the output pin OUT (pin 1) is separated by the
guard ring around sensitive pins (or traces). The guard power pin VDD/VSS (pin 2) from the input pin +IN (as
ring is biased at the same voltage as the sensitive pin. long as the analog and digital traces remain separated
An example of this type of layout is shown in throughout the PCB). However, the pinouts for the dual
Figure 4-9. and quad packages (SOIC, MSOP, TSSOP) have OUT
and -IN pins (pin 1 and 2) close to each other. The
recommended layout for these packages is shown in
IN- IN+ Figure 4-10.
VSS
OUTA VDD
-INA OUTB
+INA -INB
Guard Ring VSS +INB

FIGURE 4-9: Example Guard Ring Layout
for Inverting Circuit. FIGURE 4-10: Recommended Layout.
1. Inverting Configuration (Figures 4-6 and 4-9):
a) Connect the guard ring to the non-inverting
4.8 Unused Comparators
input pin (VIN+). This biases the guard ring An unused amplifier in a quad package (MCP6569)
to the same reference voltage as the should be configured as shown in Figure 4-11. This
comparator (e.g., VDD/2 or ground). circuit prevents the output from toggling and causing
b) Connect the inverting pin (VIN–) to the input crosstalk. It uses the minimum number of components
pad without touching the guard ring. and draws minimal current (see Figure 2-15 and
2. Non-inverting Configuration (Figure 4-4): Figure 2-15).
a) Connect the non-inverting pin (VIN+) to the
input pad without touching the guard ring. ¼ MCP6569
b) Connect the guard ring to the inverting input
VDD
pin (VIN–).
FIGURE 4-11: Unused Comparators.

MCP6566/6R/6U/7/9
4.9 Typical Applications 4.9.3 BISTABLE MULTIVIBRATOR
A simple bistable multivibrator design is shown in
4.9.1 PRECISE COMPARATOR
Figure 4-14. VREF needs to be between the power
Some applications require higher DC precision. An supplies (VSS = GND and VDD) to achieve oscillation.
easy way to solve this problem is to use an amplifier The output duty cycle changes with VREF.
(such as the MCP6291) to gain-up the input signal
before it reaches the comparator. Figure 4-12 shows
an example of this approach.
VPU
VDD R1 R2
VREF RPU
VREF
VDD
MCP6291 VPU
VDD MCP656X
RPU VOUT
VIN
R1 R2 MCP656X VOUT
VREF
C1 R3
FIGURE 4-12: Precise Inverting

FIGURE 4-14: Bistable Multivibrator.
Comparator.
4.9.2 WINDOWED COMPARATOR

Figure 4-13 shows one approach to designing a
windowed comparator. The AND gate produces a logic
‘1’ when the input voltage is between VRB and VRT
(where VRT > VRB).
VPU
1/2
MCP6567
VRT RPU
VOUT
VIN
VRB 1/2
MCP6567
FIGURE 4-13: Windowed Comparator.

MCP6566/6R/6U/7/9
NOTES:

MCP6566/6R/6U/7/9
5.0 DESIGN AIDS 5.3 Application Notes
The following Microchip Application Note is available
5.1 Microchip Advanced Part Selector on the Microchip web site at www.microchip.com and is
(MAPS) recommended as a supplemental reference resource:
MAPS is a software tool that helps semiconductor • AN895, “Oscillator Circuit For RTD Temperature
professionals efficiently identify Microchip devices that Sensors”, DS00895.
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for data sheets,
purchase, and sampling of Microchip parts.
5.2 Analog Demonstration and

Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools. Three of our boards that are especially
useful are:
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
• 5/6-Pin SOT23 Evaluation Board, P/N VSUPEV2

MCP6566/6R/6U/7/9
NOTES:

MCP6566/6R/6U/7/9
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
5-Lead SC70 (MCP6566) Example:
XXNN BJ25
5-Lead SOT-23 (MCP6566, MCP6566R) Example:

Device Code
MCP6566T JYNN
XXNN MCP6566RT JZNN JY25
MCP6566UT WLNN
Note: Applies to 5-Lead SOT-23.
8-Lead MSOP (MCP6567) Example:
XXXXXX 6567E
YWWNNN 302256
8-Lead SOIC (150 mil) (MCP6567) Example:
XXXXXXXX MCP6567E
XXXXYYWW e3
SN^^1302
NNN 256
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP6566/6R/6U/7/9
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6569) Example:
XXXXXXXXXX MCP6569
XXXXXXXXXX e3
E/SL^^
YYWWNNN 1302256
14-Lead TSSOP (MCP6569) Example:
XXXXXXXX MCP6569E
YYWW 1302
NNN 256

MCP6566/6R/6U/7/9

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MCP6566/6R/6U/7/9
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MCP6566/6R/6U/7/9
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MCP6566/6R/6U/7/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9
" #$%!&'()*

. # #$ # /! - 0 # 1/ %# #!#
## +22--- 2 /

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9
. # #$ # /! - 0 # 1/ %# #!#
## +22--- 2 /

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9

MCP6566/6R/6U/7/9
APPENDIX A: REVISION HISTORY
Revision D (February 2013)

The following is the list of modifications:
1. Added the Analog Input (VIN) parameter in
Section 1.0 “Electrical Characteristics”.
Revision C (February 2011)

1. Replaced the MCP5468 package name with the
correct MCP6567 package name on page 1 and
in Table 3-1.
Revision B (August 2009)

1. Added MCP6566U throughout the document.
2. Updated package outline drawings.
Revision A (March 2009)

• Original Release of this Document.

MCP6566/6R/6U/7/9
NOTES:

MCP6566/6R/6U/7/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. – X /XX Examples:

a) MCP6566T-E/LT: Tape and Reel,
Device Temperature Package Extended Temperature,
Range 5LD SC70 package.
b) MCP6566T-E/OT: Tape and Reel
Device: MCP6566T: Single Comparator (Tape and Reel) Extended Temperature,
(SC70, SOT-23) 5LD SOT-23 package.
MCP6566RT: Single Comparator (Tape and Reel)
(SOT-23 only) a) MCP6566RT-E/OT: Tape and Reel
MCP6566UT: Single Comparator (Tape and Reel) Extended Temperature,
(SOT-23 only) 5LD SOT-23 package.
MCP6567: Dual Comparator
MCP6567T: Dual Comparator (Tape and Reel) a) MCP6566UT-E/OT: Tape and Reel
MCP6569: Quad Comparator Extended Temperature,
MCP6569T: Quad Comparator (Tape and Reel) 5LD SOT-23 package.
Temperature E = -40C to +125C a) MCP6567-E/MS: Extended Temperature

Range: 8LD MSOP package.
b) MCP6567-E/SN: Extended Temperature
8LD SOIC package.
Package: LT = Plastic Small Outline Transistor (SC70), 5-lead
OT = Plastic Small Outline Transistor (SOT-23), 5-lead a) MCP6569T-E/SL: Tape and Reel
MS = Plastic Micro Small Outline Transistor, 8-lead Extended Temperature
SN = Plastic Small Outline Transistor, 8-lead
14LD SOIC package.
ST = Plastic Thin Shrink Small Outline Transistor, 14-lead
b) MCP6569T-E/ST: Tape and Reel
SL = Plastic Small Outline Transistor, 14-lead
Extended Temperature
14LD TSSOP package.

MCP6566/6R/6U/7/9
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
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WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
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and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
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All other trademarks mentioned herein are property of their
respective companies.
© 2009-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-030-6
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MCP6566/6R/6U/7/9

1.8V Low-Power Open-Drain Output Comparator

• Microchip Advanced Part Selector (MAPS) +IN 3 4 -IN +INA 3 + - 6 -INB

+IN 3 4 -IN +INA 3 12 +IND

 2009-2013 Microchip Technology Inc. DS22143D-page 1

DS22143D-page 2  2009-2013 Microchip Technology Inc.

 2009-2013 Microchip Technology Inc. DS22143D-page 3

DS22143D-page 4  2009-2013 Microchip Technology Inc.

FIGURE 1-1: AC and DC Test Circuit for

 2009-2013 Microchip Technology Inc. DS22143D-page 5

DS22143D-page 6  2009-2013 Microchip Technology Inc.

Avg. = -0.1 mV Avg. = -0.9 mV

StDev = 6.6 µV/°C Avg. = 10.4 µV/°C

5.0 Avg. = 0.25 µV/°C2 Avg. = 0.3 µV/°C

VIN - VOUT 20% StDev = 0.1 µV/°C

 2009-2013 Microchip Technology Inc. DS22143D-page 7

-1.0 TA= -40°C

DS22143D-page 8  2009-2013 Microchip Technology Inc.

FIGURE 2-14: Quiescent Current. FIGURE 2-17: Quiescent Current vs.

Sweep VIN+ ,VIN - = VDD/2

 2009-2013 Microchip Technology Inc. DS22143D-page 9

VDD = 5.5V VDD = 4.5 V

VDD = 2.5V VDD = 2.5 V

DS22143D-page 10  2009-2013 Microchip Technology Inc.

FIGURE 2-25: High-to-Low Propagation FIGURE 2-28: High-to-Low Propagation

Prop. Delay (ns)

60 -40 TA= -40°C

 2009-2013 Microchip Technology Inc. DS22143D-page 11

Prop. Delay (ns)

Prop. Delay (ns) 1000 tPLH

Prop. Delay (ns)

tPLH, VDD = 5.5V

DS22143D-page 12  2009-2013 Microchip Technology Inc.

FIGURE 2-37: Common-mode Rejection FIGURE 2-40: Common-mode Rejection

15% VCM = -0.3V to VDD/2

FIGURE 2-38: Power Supply Rejection FIGURE 2-41: Common-mode Rejection

IOS and IB (pA)

 2009-2013 Microchip Technology Inc. DS22143D-page 13

1000 VIN+ = 2Vpp (sine)

FIGURE 2-43: Output Jitter vs. Input

DS22143D-page 14  2009-2013 Microchip Technology Inc.

TABLE 3-1: PIN FUNCTION TABLE

3.1 Analog Inputs 3.3 Power Supply (VSS and VDD)

 2009-2013 Microchip Technology Inc. DS22143D-page 15

DS22143D-page 16  2009-2013 Microchip Technology Inc.

5 10 the resistors R1 and R2 limit the possible current drawn

VSS – (minimum expected V2)

 2009-2013 Microchip Technology Inc. DS22143D-page 17

4.2 Open-Drain Output VOUT

DS22143D-page 18  2009-2013 Microchip Technology Inc.

FIGURE 4-6: Inverting Circuit with Where:

Low-to-High High-to-Low 4.4 Bypass Capacitors

VOL With this family of comparators, the power supply pin

FIGURE 4-8: Thevenin Equivalent Circuit.

 2009-2013 Microchip Technology Inc. DS22143D-page 19

Guard Ring VSS +INB

FIGURE 4-11: Unused Comparators.

DS22143D-page 20  2009-2013 Microchip Technology Inc.

FIGURE 4-12: Precise Inverting

4.9.2 WINDOWED COMPARATOR

FIGURE 4-13: Windowed Comparator.

 2009-2013 Microchip Technology Inc. DS22143D-page 21

DS22143D-page 22  2009-2013 Microchip Technology Inc.

5.2 Analog Demonstration and

3# 44" "

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!

3# 44" "

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