T

he integrated dif-
ferential ring oscil-
l at o r ( DRO) i n
complement a r y
metal oxide semi-
conductor (CMOS) technol-
ogy has been used in numer-
ous products for a long time.
Its presence has been extended
to high-speed clock and data
recovery (CDR) circuits for opti-
cal communication, analog and
digitally controlled oscillators, fre-
quency dividers of high-frequency
synthesizers, clock generators of digi-
tal circuits, analog-to-digital convert-
ers (ADCs), and many more applications
[1]–[5]. Implementations of these ring oscilla-
tors are seen in emerging technologies such as
ultrawideband (UWB) and radio frequency iden-
tification (RFID) as well as wireless sensor networks
(WSNs) and short-range communication devices [6], [7].
The DRO is a good design choice for integrated circuit (IC)
designers because of its continued use in different bulk CMOS tech-
© digital vision
nologies. This article presents implementation techniques and performance
comparisons of the DRO as a CMOS voltage-controlled oscillator (VCO) in low radio

CMOS Differential
Ring Oscillators
Jubayer Jalil, Mamun Bin Ibne Reaz,
and Mohd Alauddin Mohd Ali

Jubayer Jalil (jubayer.jalil@gmail.com), Mamun Bin Ibne Reaz (mamun.reaz@gmail.com), and Mohd Alauddin
Mohd Ali (mama@eng.ukm.my) are with the Department of Electrical, Electronic and Systems Engineering,
Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia.

Digital Object Identifier 10.1109/MMM.2013.2259401

Date of publication: 11 July 2013

July/August 2013 1527-3342/13/$31.00©2013IEEE 97

Integrated oscillators in modern
optical and wireless communication
devices are fabricated using a variety
of technologies such as CMOS,
BiCMOS, SiGe, InP, and GaAs.
frequency (RF) bands, along with presentation and dis-
cussion of a number of circuit approaches.
Inductance-Capacitance (LC) Oscillators
Versus Ring Oscillators
Integrated oscillators in modern optical and wireless
communication devices are fabricated using a variety
of technologies such as CMOS, BiCMOS, SiGe, InP,
and GaAs. CMOS has dominated the semiconductor
industry for nearly three decades because of its rapid
evolution, continual downscaling of feature sizes, lower
power dissipation and reduced cost of fabrication. The
current trend of fully integrated inductance-capaci-
tance (LC) oscillators and ring oscillators (ROs) is being
exploited in phase-locked loop (PLL) based frequency
synthesizers in CMOS systems-on-chip (SoC) applica-
tions [8], [9]. In the LC oscillator, the on-chip monolithic
or planar spiral inductor is one of the key passive com-
ponents of the tank (resonator) circuit, along with the
resonating capacitor such as an MOS varactor for tun-
ing purposes. Unlike LC oscillators, the on-chip RO is
an inductor-free circuit. It is built using only amplifier
blocks (or delay cells) without an external frequency
selective network (resonant circuit). Still, the RO satis-
fies two of Barkhausen’s criteria for oscillation, namely
that the phase shift around the feedback loop must be
0° or an even multiple of 360° at some frequency and
that the magnitude of the loop gain at that frequency
be unity.
In the PLL, the spiral inductor of the LC oscilla-
tor performs with higher linearity and a low level of
phase noise (in frequency domain) or timing jitter
(in time domain) than its ring oscillator counterpart
[10], [11] but exhibits several limitations in standard
CMOS process. First, the ohmic loss of the inductor at
high frequencies yields a low quality factor [12] that
degrades the overall Q of the resonant circuit. Sec-
ond, compared with the RO, the LC oscillator is not
extremely compact and takes a significant amount
of die space [13], [14]. Third, the inductance (L) value
of a planar spiral inductor becomes low and fixed
when the number of the turns of the spiral is kept
constant [15]. Finally, the spiral inductor fills a large
portion of area in any IC and suffers from substrate
losses because of high conductivity of the silicon sub-
strate [10], [16]. Moreover, the LC oscillator does not
have as wide a tuning range as the RO [17]; because
integrated voltage dependent capacitors or varactors
98
used in it with the on-chip inductor have limited
capacitance change with a very low supply voltage in
deep-submicron CMOS process. In order to address
the design challenges of the LC oscillator in CMOS,
the DRO is widely used in PLL designs of low giga-
hertz and multistandard RF transceivers.
Phase Noise in DRO
The DRO-based VCO design involves many trad-
eoffs between frequency generation, phase noise,
tuning range, power, and multiphase output signals
(i.e. production of a number of multiple quadrature
phases), and the phase noise is the most vital design
concern among them. Now the question is: what is
phase noise? Phase noise is the power spectrum of
the oscillation frequency in real oscillators not being
concentrated at a single tone; rather it is spread into
adjacent frequencies around that tone and what is
commonly known as phase noise (PN). We use the
single-sided power spectral density (PSD) of the sig-
nal normalized to the power in the fundamental tone
as a measure of phase noise. In the classical Leeson’s
model for the linearized oscillator, the PN, L ^∆~h is
written as [18], [19]
= 10 log =) 1 + 3
S U (D~) 2
~o
L (D~) =
2 (2D~Q) 2

c m mE,
D~ 1/f3 2FKT
# 1+ c (1)
D~ PDC
where, S U = the PSD of PN; D~ = the frequency offset
from the carrier center frequency ^~ 0 h; D~ 31/f = flicker
corner frequency of the active devices used as the
oscillator; PDC = DC power consumption of oscillator;
F = noise factor of the active devices; K = Boltzmann’s
constant; T = absolute temperature in degrees Kelvin.
There are a few parameters that adversely affect
PN performance of the DRO: low Q factor, high out-
put frequency, low power consumption, high tem-
perature, high voltage gain, number of delay stages
of cascaded connections, and continuous conduction
of active and passive devices [13], [19]–[22]. Select-
ing proper delay cell topology for fast rail-to-rail
switching may reduce PN. Reducing flicker noise
up-conversion in the tuning current and white
noise in the delay cells can also provide better PN
performance. In practice, the DRO gain or sensitiv-
ity is much higher than the LC oscillator, and the
DRO overall PN quality can be further improved by
reducing tuning bandwidth and by using a noise-
free control path.
The figure of merit (FOM) is an overall performance
benchmark of the ring VCO and can be expressed
using the power consumption ^PDCh and the PN in the
oscillation frequency ^~ 0 h by
FOM dB = L (D~) + 10 log c m - 20 log ` j.
PDC ~ 0 (2)
1mW D~
July/August 2013
Single-Ended Versus Both single-ended and differential
Differential Ring Oscillators
A ring oscillator is formed by using an odd and even topologies can be used in designing
number (N) of open loop inverting amplifiers (A) or fully integrated CMOS VCOs.
delay cells (or stages) which are coupled in a positive
feedback loop (Figure 1). During operation, if one of
the nodes of the RO is excited, then the pulse propa-
gates through all the cells and eventually reverses N
the polarity of the initially excited node. It is worth
mentioning that previously stated Barkhausen crite- Vout
ria are necessary for stable oscillation but not suffi- A A A A
cient for the start-up conditions. To ensure any sort of
oscillator’s start-up in the beginning, the open-loop
gain of the oscillator should always be higher than
unity. Whenever this condition is satisfied, perhaps Figure 1. The RO structure with N number of cells or
the oscillator is kicked by noise of the circuit, an ini- amplifier blocks (A).
tial condition or a small current pulse in one of the
nodes of that oscillator or a short pulse to the supply
voltage. These phenomena are conspicuous in every Frequency Control
practical oscillator.
tp tp tp
In RO, the propagation signal passes twice through
the chain of N delay cells, for a total delay of 2Nt p, to VA 1 VB 0 VC 1
complete one period ^Tosc h; t p denotes the propagation
+ - + - + -
Output
time of a single delay cell. The frequency (f) of this - + - + - +
VA' VB' VC'
oscillator is a measure of the round trip time through
the loop and can be derived as
(a)

f = 1 = 1 . (3) Tosc
Tosc 2Nt P
tp Edge
Typically, t p of a RO is computed by a multiplica- tp X3
tion of the resistive load ^RLoadh and total capacitance
Edge tp
Edge X2
X1
^ C total h of load and parasitics of active devices in a
1 1

delay cell circuit with a constant factor of ln2. More-

over, ^R Lqad h can be represented by the output voltage
swing over total load (bias) current in each delay cell.
The delay cells of the RO can be single-ended or dif-
ferential [20]. The single-ended RO (SERO) is a chain of
inverters composed of an NMOS and PMOS transis-
tor, and the number of delay cells must be odd. Delay
cells of the DRO can be an odd or even number and
are constructed using a load (active or passive compo-
nents) with an input pair of NMOS differential pairs or
a push-pull inverter. The propagation time in this type
of cell is set by the charge in each node and the current
through the load that may consist of a resistor for fixed
frequency or PMOS transistors.
Both single-ended and differential topologies can
be used in designing fully integrated CMOS VCOs.
Based on the outputs of its delay cell architectures, the
DRO can be categorized in three ways: saturated type,
unsaturated type and nonsaturated type [21]. Com-
pared with the unsaturated DRO, the output stage of
the SERO is always saturated. For this reason, the SERO
exhibits better PN performance for an equal number of
stages while also consuming very low power [22] and
shows superior thermal noise performance [23]. Due
to better common-mode rejection of supply and sub-
VA 0
t = t1
Total Phase Shift in Loop = r
Total Propagation Time in Loop = 3tp
3t
` r = p ( Tosc = 6tp
2r Tosc
(b)
Figure 2. (a) A simple functional block diagram of
the three-stage DRO-based VCO. (b) A corresponding
waveform and period calculation.
strate noise, the DRO has outperformed the SERO in
both in digital and analog ICs [23]. Moreover, it is easy
to achieve very high-frequency performance with both
in-phase and quadrature outputs in DRO [24].
DRO-Based VCO: Working Principles
To explain the basic working principle of the DRO, let
us consider the circuit shown in Figure 2(a), illustrat-
ing a three-stage DRO (N = 3), in which at time t 1 the
output of the first stage, VA changes to logic 1 (denoted
by edge X 1 ) as shown in signal waveform in Figure 2(b)
[25]. When this logic 1 propagates to the end, it creates

July/August 2013 99
Recent developments of the DRO have
evolved based on various FD or PD
configurations of delay stages both
in single- and dual-delay loop ring
architectures.
a logic 1 at the third stage, which, when fed back to the
input of the first stage, creates a logic 0 in the first stage
output denoting edge X 2 . When this logic 0 is propa-
gated again through the loop, it toggles the output of
the first stage, VA and trigger edge X 3 . For every single
cycle, there are a downward as well as an upward tran-
sition, and the intrinsic propagation delay times of each
delay cell, high-to-low ^t PHL h and low-to-high ^t HPL h,
are associated with these transitions. Nevertheless,
^ t PHL h and ^ t HPL h could be equal or not depending on
the specific delay cell configurations, and so the aver-
age propagation delay can be implied by the arithmetic
mean of transition times, ^t PHL + t HPL h /2.
In order to vary the frequency of the RO, either the
number of stages (N) or the propagation time ^t p h must
be changed. The following frequency tuning mecha-
nisms are often employed in all ROs: by varying the
output capacitance load, by varying “on resistance”
of a linear MOSFET, by varying current handling
capability of the circuits driving the load and even by
changing the dc supply voltage of oscillators. Besides
these approaches, another unique method of tuning is
known as delay interpolation for the DROs, for which
wide tuning range and relatively linear volt-to-fre-
quency characteristics can be attained [26], [27]. In this
approach, a fast path and a slow path are operated in
parallel at each delay interpolation stage. Total propa-
gation delay is controlled by increasing the gain of one
path and decreasing that of the other, and consequently
their outputs are summed together at the end. There-
fore, the frequency of the DROs can be adjusted by
steering the current between the fast and slow paths.
Fully Differential Versus
Pseudodifferential DROs
The use of DRO circuit configurations such as true or
fully differential (FD) and pseudodifferential (PD) are
generally dominant in CMOS ICs [28]. The FD struc-
ture is based on a differential pair whereby the tail
current source has better common-mode noise rejec-
tion, reduced harmonic distortion, and enlarged output
voltage swing. The FD common-mode gain is lowered
by increasing the output resistance of the tail current
source. The PD configuration is based on two indepen-
dent inverters without tail current sources and results
in a larger common-mode gain [29]. Wider input range
is possible in PD structures due to avoidance of the tail
current source, making it suitable for low voltage appli-
100
cations. Most DRO topologies currently use one of these
two topologies.
Effects of Delay Stages in DROs
The VCO is a major and critical building block in high-
frequency PLLs, and employing fewer delay stages for
this module can reduce the power dissipation, chip
area and cost. In wired and wireless communication
systems, two, three or four stages of both fully and
pseudodifferential delay cells are usually adopted
for construction of high-frequency DROs. Though a
three-stage DRO cannot produce a quadrature output
compared to two- and four-stage DROs, the three-
stage DRO is faster than its four-stage counterpart.
It is desirable to design a two-stage DRO to reduce
power and improve phase noise performance, but
when designing a two-stage DRO, an additional phase
shift is required in each delay cell in order to satisfy
the Barkhausen criteria, and extra power is consumed
in order to achieve the excess phase shift. For all even
numbered DROs, latch-up or no oscillation may occur
if oscillators fail to fulfill the proper start-up conditions
or by not swapping input and output connections.
We find from (3) that the oscillation frequency of
the DRO is mainly determined by the propagation
time ^t P h of each stage and the number (N) of stages;
the maximum frequency of this type of oscillator
is limited by the propagation time of the delay cells,
in which only a set of primary inputs are used. This
type of DRO architecture is known as single-loop or
single-path. A technique initiated for the maximum
frequency levels of the DRO is called a dual-delay
loop. In a dual-delay loop (sometimes referred to as
a multiloop) structure, auxiliary or secondary inputs
are added, along with the primary inputs of existing
delay cells. These auxiliaries are in fact switched ear-
lier than the primary inputs and signals are fed from
the preceding stages during operation. Recent devel-
opments of the DRO have evolved based on various
FD or PD configurations of delay stages both in single-
and dual-delay loop ring architectures. The following
sections discuss a number of PD and FD delay cells
used in two, three and four stages of DROs in conjunc-
tion with their performance as VCOs in contemporary
CMOS technologies.
DRO by PD Delay Cells
Park-Kim Delay Cells and Their Modifications
A four-stage DRO based on PD amplifier delay cell,
proposed by Park-Kim, is fully switched: the output of
the DRO reaches the power rail within the period of
oscillation [30]. The DRO made by this fully switched
type delay cell is normally termed a saturated-type
oscillator. This delay cell includes an NMOS differen-
tial input pair (M1, M2), a pair of PMOS load transistors
(M3, M4) for providing a positive feedback latch and
July/August 2013
cross-coupled NMOS transistors (M5, M6) for control-
By employing a dual-delay scheme or
ling the gate voltage of the load transistors and limiting
the strength of the added latch (Figure 3). With the help loop, higher oscillation frequency can
of the positive feedback of the latch, the transition edges be managed.
of the output waveform of the oscillator remain sharp
in spite of slow delay time. Moreover, the positive feed-
back latch speeds up the transitions and offers a much delay cell, the cross-coupled PMOS transistors (M3,
higher oscillation frequency since the negative-skewed M4) are adopted as loads, but to control the oscilla-
cells turn on the PMOS devices before the low-to-high tion frequency, auxiliary PMOS transistors (M5, M6)
output transition, and turn off the PMOS devices before are placed parallel with these loads (Figure 5). Unlike
the high-to-low output transition. By employing a dual- conventional Lee-Kim delay cells, two NMOS tran-
delay scheme or loop, higher oscillation frequency can sistors (M7, M8) are added between the output nodes
be managed [31]. This delay structure has the drawback and ground. For biasing purposes, the gates of M7
of the existence of a dead zone in its voltage response. and M8 are connected to the diode-connected NMOS
This dead zone is the flat response of the output volt- transistor ^M 0 h and this transistor is biased by a pro-
ages with respect to the input voltages [32]. Adding two grammable current source ^I bh . The typical program-
PMOS transistors in parallel with the pull-up PMOS mable current source ^I bh could be controlled by a
load provides an additional charge path and overcomes digital-to-analog converter (DAC) in association with
the dead zone problem. Further increases in oscillation a successive approximation register (SAR) as shown in
frequency were realized by self-biased active inductors
as reported in [32], demonstrating better performance
than the original Park-Kim delay cell.
For low voltage operation, a delay cell with a com- VDD
plementary current control technique also based on
M5 M9 M10 M6
the Park-Kim delay cell is presented in [33] (Figure 4). Vin2- Vin2+
Here, a pair of PMOS complementary control transis- M7 M8
tors (M9, M10) is added, offering extra current to over-
come the restriction of low voltage control operation Vout- Vout+
Vc
and increasing the oscillation frequency by dual delay
loop structure. It has full supply voltage range control- M3 M4
lability and wide tuning range of 43.39%. Its better
phase noise performance is achieved at the expense of
high power dissipation of 100 mW. Vin1+ Vin1-
M1 M2
Compensated Lee-Kim Delay Cell
Wu et al. use another fully switched delay cell based
on the Lee-Kim delay cell stated in [34] for the four-
stage dual-delay loop DRO [35]. Like the Park-Kim Figure 4. A complementary current control delay cell [33].

VDD VDD

M5 M4 M0
M3 M4 Vc M3 M6 Vc

Vout- Vout+
Vb Vin+ Vin- Vb
M7 M1 M2 M8
M5 M6
Ib
Vout- Vout+ n: Digital Inputs
n
SAR: Successive Iout = Ib DAC
Appromixation S
M1 Vc M2 A
Register
Vin+ Vin- R
DAC: Digital-to-Analog
Converter

Figure 3. A Park-Kim delay cell for single delay path Figure 5. A compensated Lee-Kim delay cell with diode-
oscillator [30]. connected transistor and current source [35].

July/August 2013 101

 VDD Ip VDD
Vins+ M5 M3 M4 M6 Vins-
M7 M3 M9 M10 M8 M7 M8
Vins+ M4 V Vc
ins-
Vout- (Coarse) Vout+
M9 M10
M5 M6
M1 M2
Vout- Vout+ Vinp+ Vinp-
Vc (Fine)
M11
M1 Vc M2
Vinp+ Vinp-

Figure 8. A delay cell with positive feedback latch for

Figure 6. A voltage and current controlled delay cell [37]. coarse and fine tune [39].

VDD it suffers from poor phase noise of -99 dBc/Hz at

Vins+
M3 M4 M5 M6
Vc
M7 Vout+ Vout- M8
M1 M2
Vinp+
Figure 7. A PD delay cell with symmetric load [38].
Figure 5. This type of configuration is used to reduce
supply voltage sensitivity. In contrast to the Manea-
tis delay cell (described later), a replica bias circuit
and a current bias transistor are not required for both
conventional and compensated Lee-Kim delay cells.
For construction of the dual delay path architecture,
two PMOS transistors can be added in parallel with
M5 and M6. In spite of digital calibration techniques
to compensate for supply noise, this design requires
large and complex digital controllers.
Voltage and Current Controlled Delay Cell
In [36], a four-stage DRO was designed for the dual-
loop PLL, utilizing voltage control and current
control simultaneously to provide dual-controlled
inputs. Based on the delay latch proposed by Eken-
Uymera in [37] for the three-stage RO, the positive
feedback gain in the latch (M3, M4) of this circuit
increases with Vc (coarse tuning) by reducing the
MOS resistance of M5 and M6 (Figure 6). A pair
of PMOS transistors (M7, M8), the gates of which
are connected to ground to keep the devices in the
saturation region, provide an additional amount of
injected current ^I p h that splits into the output nodes
^ Vout-, Vout+ h . The injected current ^ I p h is fed by sepa-
rate voltage-to-current modules, which changes the
total injected current using the differential input
control signal. Even though this DRO generates a
higher frequency signal and widens tuning range,
Vins- 1 MHz offset from 5.5 GHz while consuming 58 mW
of power in comparison with [37].
Delay Cell with Symmetric Load
A delay cell demonstrated in [38] for a three-stage
dual-delay loop DRO is different from the preceding
Vinp-
delay cells. In this delay stage, input NMOS pair (M1,
M2) and input PMOS pair (M3, M6) are employed for
the primary loop and secondary loop, respectively
(Figure 7). This DRO combines composite loads of
two (M3 and M7, M6 and M8) in each cell and feed-
forward techniques rather single delay path to reduce
the propagation time of each cell. The size of M4 and
M5 determines the tuning range and controls the fre-
quency of oscillation by tuning the gate voltage. The
proposed composite loads behave as active inductors
at the drain of M3, M6 and M7, M8 by eliminating
conventional active loads, and these active inductors,
which cause the time constant reduction obtained
from inductive peaking, increase the oscillation
frequency of the DRO. Additionally, this oscillator
acquired wide tuning range due to moderately high
quality factor (Q) of the active inductor. The wide tun-
ing range of 180% attained at low voltage is the main
feature of this oscillator.
Coarse and Fine Tuning Pseudodifferential
Cell with Positive Feedback Latch
The delay cell mentioned in [39] can be used for the
multiloop three-stage DRO (Figure 8). In this cell,
NMOS transistors M1 and M2 form the input pair
of the primary loop, while PMOS M7 and M8 serve
as the input pair of the secondary loop. PMOS tran-
sistors M3 and M4 form the load of the delay cell.
In order to circumvent the loss of oscillation at the
extreme range of frequency tuning, extra PMOS
loads M5 and M6 are inserted in shunt with the con-
trollable load M3 and M4. In this design, the gates
of M5 and M6 are connected to bias the transistors
into the triode region of operation. Coarse tuning is

102 July/August 2013

accomplished by varying the load through changing
A DRO with a wide tuning range of
the gate voltage of M3 and M4. Fine-tuning is steered
by adjusting the amount of tail current flowing 130%, good linearity and low power
through the positive feedback latch, M9 and M10. In is proposed in [47] and is designed for
this oscillator, both coarse and fine tuning is applied
the applications like vital sign radar
to decrease the VCO tuning sensitivity and the low-
frequency noise-up conversion without impairing monitor, UWB impulse radio (IR), and
the tuning range. However, this DRO’s power dissi- clock recovery in broadband optical
pation of 60 mW and a phase noise of -103 dBc/Hz
communication.
at 1 MHz offset from 7.64 GHz are not suitable for
portable, high-data rated wireless devices.

Differential Cascode Voltage-Switch-Logic

with Resistance VDD
Compared to current mode logic (CML) or source- Vc Vf Vf Vc
M7 M5 M3 M4 M6 M8
coupled pair, differential cascode voltage-switch-
logic (DCVSL) circuits offer low transistor count, Vout- Vout+
Vf = Fine
no headroom limitation, rail-to-rail swing, and no Tuning R
static current consumption and can be used in ROs. Vc = Coarse
However, a DCVSL circuit suffers from a large low- Tuning
to-high propagation delay, limiting its speed and
resulting in asymmetrical output waveforms. In [40], M1 M2
Vin+ Vin-
a DCVSL-based delay cell with resistance (DCVSL-
R) is presented for three-stage RO (Figure 9). It can
overcome the delay asymmetry and reduce total Figure 9. A delay cell of differential cascode voltage-
propagation delay. The replacement of DCVSL delay switch-logic with resistance [40].
cells in DROs with DCVSL-R cells expedites circuit
speed for a given power budget without sacrificing
phase noise.
VDD

Latch Pair Based Delay Cell Vc

The circuit schematics of the delay cell performed in
[41] consists of one NMOS input pair (M1 and M2), one
PMOS pair (M7 and M8) for frequency tuning, and one
latch pair including two inverters made up of M3, M5
and M4, M6 (Figure 10). Because of this construction,
the delay cell can be turned on and off completely which
shortens transition time. Besides good phase noise and
wide tuning range, the latch pair delay cell reveals good
tuning linearity of the control voltage. This low fre-
quency, two-stage single delay path DRO’s power dissi-
pation of 65.5 mW is higher than that of the other DROs
developed in the 0.18 micron CMOS process [41].
Delay Cell of Injection Locking Technique
Another type of two-stage DRO formed by the PD
delay cells with three NMOS switches uses a subhar-
monic injection-locking technique generating a stable
harmonic of a pure reference signal [42]. In subhar-
monic injection (/n) [note: integer n stands for the
subharmonic factor], a free-running DRO is locked
onto the nth harmonic of the injected or incident
signal generated because of circuit nonlinearities.
When this injected signal inserts an additional phase
shift into the feedback loop of the DRO, it no longer
oscillates at the free-running frequency because the
total phase shift at this frequency deviates from 2r
M7 M5 M6 M8
Vout- Vout+
M3 M4
M1 M2
Vin+ Vin-
Figure 10. A latch pair based delay cell [41].
(Barkhausen criterion) by the additional phase shift.
If the amplitude and the frequency of the injected
signal are selected correctly, then the RO annuls the
effect of the phase shift by oscillating at the injection
frequency and eventually, injection-locking occurs.
Here, to carry out subharmonic injection-locking, two
of the NMOS switches (M1, M2) are connected at the
differential output node of each delay cell (Figure 11).
The rail-to-rail pulses are injected into M3 to initiate
injection-locking. The rail-to-rail pulses are created
by an external signal generator. In order to satisfy
the oscillation condition, the delay cell also includes
an NMOS latch created by M6 and M7 that gener-
ates a propagation delay through positive feedback.
The oscillation frequency is determined by the ratio

July/August 2013 103

The DROs based on the Maneatis transistors M8 and M9 to make the range of sensitive
voltages identical to the rail-to-rail voltage range. In
delay cell are popular among this circuit, the frequency tuning range is linear over
designers both in microprocessor a certain range of control voltage. Changes of the total
and RF oscillators. equivalent resistance of the two PMOS transistors
(M4 and M5) with the main control voltage (Vb) rang-
ing from 0 V to 0.4 V ensure frequency tuning from
10 GHz to 7.8 GHz, and this tuning range seems to
VDD be almost linear. By altering the control voltage from
Vb Vbn Vinj Vbn Vb 0.4 V to 1 V, the frequency decreases from 7.8 GHz to
M4 M8 M9 M5 2.4 GHz but the tuning range loses linearity. However,
M3 key advantages of this DRO are its scalability, wide-
Vout- Vout+
frequency-range and low noise. The VCO based on
Vin+ M2 Vin-
M1 M6 M7 this two-stage pseudodifferential DRO is suitable for
use the UWB of 2.4–10 GHz.

DRO by FD Delay Cells

Figure 11. An injection locking delay cell [42].
Classical Fully Differential Delay Cell
Like the PD delay cell, the FD delay cell is widely
used for the design DROs. The classical FD delay
VDD
cell is built by a differential pair loaded by two resis-
tors (either active or passive). In this delay cell, an
R R
RC equivalent is formed in each branch by the load
l2 /2 l2 /2 resistor and the parasitic capacitance of the transis-
V2 tors. The variation of the current flowing through
M1 M2
Vin+ Vin- the delay stage changes the propagation delay. This
l1 change ultimately results in the variation of the
V1 M3
(From Bias oscillation frequency of the ring. In addition, when
and Control changing the oscillation frequency, the variation of
Circuit) the tail bias current flowing through the delay stage
modifies the amplitude of the output signal and the
Figure 12. A modified classical FD delay cell [43]. average dc level of oscillation. To alleviate the use of
a replica bias circuit in FD delay cells for biasing, a
modified classical delay cell is explored in [43] (Fig-
ure 12). In this circuit, a constant value for the dc level
VDD
of the output signal is done without the need for a
replica bias circuit, thus saving area and reducing the
M3 M4
Vbias Vbias power dissipation for the four-stage DRO. To keep the
M6 average dc level of oscillation for a certain frequency
Vout- Vout+
range constant, the current flowing through the load
resistors at a fixed value needs to be held constant. In
M1 M2
Vin+ Vin- this delay cell topology, the variation of the bias cur-
rent that causes the change in frequency is balanced
at the resistors by the current carried through the
Vc M5 branches in parallel with the classical FD delay cell.
The current flowing through the delay stages form-
ing the DRO is reduced, resulting in enhanced phase
noise performance. Moreover, the dc-level stabiliza-
Figure 13. Delay cell with active load [44]. tion stage implemented in this DRO after forming
the ring allows inclusion of a one-stage output buffer,
and hence significant power is reduced for the DRO.
of the inverter sizes of the ring and the latch, and con-
trolled by varying the inverter size of the ring relative Delay Cell with Active Load
to that of the latch. PMOS resistive loads are assigned The FD amplifier-based delay cell depicted in [44]
for tuning the output oscillation frequency. The bias- is designed for a three-stage DRO (Figure 13). This
level-shifted control voltage ^V bn h controls the PMOS circuit can be divided into three parts in terms of

104 July/August 2013

its operation: load devices with bias
network, switching network, and tun- VDD
ing transistor. In this circuit, in order
to implement the linear relationship M11 M9 M7 M8 M10 M12
between the input control current and
Vout+ Vc Vout-
the output frequency, the PMOS tran-
sistors that act as loads in the delay cell
Vins+ M1 M5 M6 M2 Vins-
are biased in the linear region. A bias Vinp+ Vinp-
circuit with active feedback is used M3 M4
to provide the gate bias for these load
transistors. The variation of the oscil-
M13
lation frequency is achieved by chang- Vbias
ing the tail current flowing through the
delay cell.
Figure 14. A delay cell with push-pull inverters [45].
Delay Cell with
Push-Pull Inverters
By using two push-pull inverters as secondary inputs,
the delay cell proposed in [45] was used for high-speed VDD
optical communication and clock generation systems.
This three-stage, multiloop DRO helps to reduce both R Vc R
low-to-high and high-to-low propagation delays, result- M7 M9 M10 M8
ing in a higher operating frequency (Figure 14). In this
circuit, M1 and M2 form the input pair of the primary
loop, while inverters formed by M3–M11 and M4–M12 M3 M4
serve as the input pair of the secondary loop. PMOS M5 M6
M7-M8 forms the load of the delay cell. To avoid the loss
M1 M2
of oscillation at the extreme ranges of frequency tun- Vin+ Vin-
ing, extra transistors M9 and M10 are added in shunt to
Vbias
the controllable load M7 and M8. The gates of M9 and
M10 are connected to ground in order to bias the tran-
sistors in the triode region of operation. This ensures
sufficient current for charging the output node even
Figure 15. Shunt-shunt feedback delay cell [27].
when the control voltage approaches the supply voltage,
which shuts M7–M8 down completely. The cross-cou-
pled NMOS latch (M5 and M6) was introduced for two exhibit the property of inductive peaking so that the ac
purposes: first, to prevent the differential output nodes small signal gain at the oscillation frequency and the
from converging at the same voltage so that the differ- output signal swing can be boosted. Although the total
ential oscillation operation can become single-ended; power dissipation seems to be increased due to the
and second, the positive feedback caused by the latch addition of two more current paths organized by M5,
is able to reduce the slew time of the output nodes, both M6, M9 and M10, the property of shunt-shunt feedback
low-to-high and high-to-low, allowing better phase makes the required dc current associated with these
noise attribute. Achieving faster speed of operation at two paths very small compared to that of the main sig-
the expense of lowering the swing amplitude does not nal paths. This circuit shows lower power dissipation
really improve the phase noise performance, and its of 17 mW, large output signal swing, and wide tuning
power consumption of 72 mW is indeed very high due range of 75%.
to many transistors. Reference [46] reports that replac-
ing the push-pull inverter of this delay circuit by only Delay Cell with
one PMOS transistor pair can increase frequency oscil- Cross-Coupled Symmetric Load
lation up to 10 GHz. A DRO with wide tuning range of 130%, good lin-
earity, and low power is proposed in [47] and is
Shunt-Shunt Feedback Delay Cell designed for the applications like vital sign radar
In [27], a two-stage DRO is presented where excess monitor, UWB impulse radio (IR) and clock recov-
phase shift is provided by the shunt-shunt feedback ery in broadband optical communication. This
configuration using M3, M4, M5, and M6 (Figure 15). DRO employs cross-coupled symmetric load delay
The loading circuit, containing a resistor and an NMOS cell, and loads of each delay cell encompass PMOS
loading transistor (M7 or M8), can be designed to transistors M3, M5 and M4, M6 (Figure 16). In order

July/August 2013 105

The choice of the various Delay Cell with Programmable
Resistive Network
DRO topologies depends on the A two-stage DRO using a FD delay cell with a pro-
application, so it is necessary grammable resistive network is designed in [6] for a
to estimate the performance of digitally controlled oscillator (DCO) of UWB appli-
cation (Figure 17). This delay cell consists of a cross-
different DRO topologies prior to coupled PMOS load, a pair of NMOS as inputs, and
choosing them. a programmable resistive network (Rp) with a tail
current transistor (M5) for frequency tuning. Unlike
[47], this circuit is less power-efficient because of the
to cancel out resistive effects, these PMOS load tran- absence of a diode pair, which cancels the resistive
sistors are configured as diodes (M5 and M6) and load but does have a wide tuning range of 139%.
negative resistance by M3 and M4. A NMOS trans-
conductance pair (MN1 and MN2) and a tail current Maneatis Delay Cell of Symmetric Load
transistor (M7) operated in the deep triode region The DROs based on the Maneatis delay cell are
act as inputs and as a frequency tuning device, popular among designers both in microprocessor
respectively. Stringent supply voltage regulation is and RF oscillators. The delay topology for a giga-
necessary for frequency stability. hertz PLL proposed in [48] is based on the Maneatis
delay cell. In this modified delay cell, the incorpora-
tion of additional transistors with the conventional
Maneatis delay cell provides the necessary bias
conditions for DRO oscillation by means of posi-
tive partial feedback. According to [49], the original
VDD
Maneatis circuit consists of two symmetric loads,
a NMOS input pair (M1 and M2) and a tail current
M5 M3 M4 M6 source, NMOS transistor (M7) (Figure 18). A single
symmetric load comprises of a pair of equally sized
Vout- Vout+ PMOS transistors (M3 and M5), of which one tran-
sistor (M3) is biased at the control voltage and the
M1 M2 other transistor (M5) is diode connected. For cor-
Vin+ Vin-
rect operation of the delay cell, the diode is kept in
Vc saturation and the PMOS transistor is operated in
M7 the linear or triode region. To vary the frequency of
this DRO, the replica bias circuit creates a bias volt-
age, and this voltage compensates the delay current
changes due to process variations. The tuning range
Figure 16. Delay cell with cross-coupled load [47]. is controlled by adjusting the tail current. This cell
suffers from high sensitivity to voltage supply varia-
tions and requires stabilizing circuitry to eliminate
noise variation from the power source [50].
VDD

M3 M4

VDD
Vout- Vout+
Vc M5 M3 M4 M6 Vc
M1 M2
Vin+ Vin- Vout- Vout+

Rp M1 M2
Vin+ Vin-

M5 Vbias M7
Vc

Figure 17. Delay cell with programmable resistive network [6]. Figure 18. Maneatis delay cell of symmetric load [49].

106 July/August 2013

 Table 1. Performance comparison among various architectures of the DRO for high-frequency VCOs.

PN (dBc/ Power
Year Oscillation Tuning Hz) @ Offset Supply (mW) or FOM CMOS
Published Differential Frequency Range (MHz) or Voltage Current (dBc/ Process
[Ref. No.] Architecture Topology (GHz) (GHz) Jitter (ps rms) (V) (mA) Hz) (μm)
1998 [44] Three-stage, Fully — 1.3–1.8 0.3* 3 23 mW — 0.5
single-delay
loop
1999 [30] Four-stage, Pseudo 0.9 0.75–1.2 -117@0.6 3 3** -165.8 0.6
dual-delay
loop
2004 [37] Three-stage, Pseudo 5.79 5.16– -99.5@1 1.8 80 mW -155.72 0.18
multiple pass 5.93
loop
2004 [27] Two-stage, Fully 3.6 2.5–5.2 -90.1@1 1.8 17 mW -148.92 0.18
single-delay
loop
2005 [46] Three-stage, Fully 9.5 8.5–10.5 -92@1 1.8 30–38 — 0.18
multiloop mA
2006 [41] Two-stage, Pseudo 0.9 0.73– -106.1@0.6 1.8 65.5 -151.46 0.18
single-delay 1.43 mW
loop
2007 [35] Four-stage, Pseudo 1.4 0.5–2 3.9* 1.4 — — 0.13
dual-delay
loop
2007 [48] Two-stage, Fully 0.85 0.186– -113.5@0.6 1.8 11.38 -165.96 0.18
single-delay 1.5 mW
loop
2008 [45] Three-stage, Fully 7 6.24– -107@10 1.8 72 mW -145.1 0.18
multiloop 7.04
2008 [38] Three-stage, Pseudo 5 0.5–9.5 -85.3@1 1.2 9 mW -172.3 0.13
dual-delay (180%)
loop
2009 [36] Four-stage, Pseudo 5.5 4.2–5.9 -99.1@1 1.8 58 mW -156.28 0.18
dual-delay
loop
2009 [6] Two-stage, Fully 5.65 139.4% -121.7@10 1.3 5 mW — 0.13
single-delay
loop
2009 [39] Four-stage, Pseudo 7.64 7.3-7.86 -103.4@1 1.5 60 mW -163.3 0.13
multiloop
2010 [33] Four-stage, Pseudo 5.22 3.03– -107.7@1 1.8 100 mW -161.35 0.18
dual-delay 5.36
loop (43.39%)
2010 [47] Two-stage, Fully 6 1–9 -112.3@10 0.58-1.6 3.7 mA — 0.13
single-delay
loop
2011 [42] Two-stage, Pseudo 9 2.4–10 -125@1 1 9.5 mW -194.3 0.09
single-delay
loop
2011 [43] Four-stage, Fully 3.125 18% -91@1 1.8 12.6 mW -149.1 0.18
single-delay
loop
2011 [31] Four-stage, Pseudo — 1.77– -123.4@10 1.8 13 mW — 0.18
dual-delay 1.92
loop (continued )

July/August 2013 107

 Table 1. Performance comparison among various architectures of the DRO for high-frequency VCOs (continued ).
Year Oscillation
Published Differential Frequency
[Ref. No.] Architecture Topology (GHz)
2011 [40] Three-stage, Pseudo 2.4
single-delay
loop
*Timing jitter (ps rms)
**Current (nA)
Discussion and Concluding Remarks
This review article presented a variety of low giga-
hertz, inductorless DROs published in different sci-
entific papers in the last 15 years. Table 1 shows a
chronological summary of empirical results for VCOs
extracted from research papers of the previous DRO
by means of fully and pseudodifferential topologies
including phase noise, oscillation frequency, tuning
range, supply voltage, power dissipation, FOM, and
CMOS feature size. As the free running DRO is very
sensitive to process, supply voltage, and temperature
(PVT), strict design regulation is desirable to minimize
unwanted frequency variations [35], [42], [43], [49].
All major long-range and short-range wireless com-
munication standards such as GSM, DCS-1800, WLAN
IEEE 802.11a/b/g/n and IEEE 802.11 FH (Bluetooth)
operate in the frequency range of 0.8–5 GHz, where
the frequency range demands exceptional VCO PN
performance. Due to the inherent high PN of the DRO
compared to the LC oscillator, the signal-to-noise ratio
(SNR) of wireless transceivers is reduced, causing the
bit-error rate (BER) to increase. That is why for cellular
communication system, RF engineers adopt LC VCOs
at the outset for its better PN performance. For short-
range communication, the IEEE 802.11b protocol (Wi-
Fi) has to keep BER better than 10 -5 with a PN of -101
dBc/Hz at 1 MHz offset from the center frequency for
high data-rate application. Thus, to fulfill such a strin-
gent requirement of PN, the DRO based VCOs need to
consume a substantial amount of power as shown by a
number of circuits in Table 1. However, the DRO based
VCO running in 2.4 GHz illustrated by Turker et al.
[40] is suitable for low power, low data-rate Zigbee
application, in which the PN requirement is a more
relaxed than Wi-Fi and Bluetooth standards. Apart
from the PN concern, for CDR and clock distribution
circuits, where multiphase output signals and die area
are of more concern than low jitter/phase noise opera-
tion, the DRO is more preferred.
The choice of the various DRO topologies depends
on the application, so it is necessary to estimate the
performance of different DRO topologies prior to
choosing them. Currently, various DRO designers are
trying to overcome crucial design issues, such as low
108
PN (dBc/ Power
Tuning Hz) @ Offset Supply (mW) or FOM CMOS
Range (MHz) or Voltage Current (dBc/ Process
(GHz) Jitter (ps rms) (V) (mA) Hz) (μm)
2.34– -113@10 1.05 2 mW -157.6 0.13
3.11
noise, low power dissipation, low voltage operation,
high-speed oscillation, multiphase clock generation,
supply sensitivity reduction, wide tuning range, and
higher linearity. As advances in downsizing CMOS
feature sizes allow for smaller and faster transistors,
DROs are now competitive with LC resonators or even
other RC based oscillators. Besides their use in tradi-
tional analog charge-pumped PLLs or digital PLLs, the
topologies discussed in this article could be embraced
as viable candidates in emerging high-frequency
all-digital PLL (ADPLL) based frequency synthesiz-
ers. Research in this field, therefore, is, and will con-
tinue to be, extremely active for the development of
RF devices operating in a high-frequency range with
optimum power.
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