SAMPATH KUMAR R
Design and Verification Engineer
CONTACT
919980409429
sampatrajanna7952@gmail.com
https://www.linkedin.com/in/sa
mpath-kumar-r-436604254
EDUCATION
Government Engineering College,
Hassan. |BE(EEE)
2019-2023 (CGFA=7.61)
Vishwa Manava Comp PU Col,
Seebara-Guttinadu, Chitradurga.
|PUC 2017-2019 (73%)
Vishwa Manava Res High School,
Seebara-Guttinadu, Chitradurga.
|SSLC 2016-2017 (83.68%)
EDA TOOLS
Questa sim
VCS
Model sim
TECHNICAL SKILLS
Digital Electronics
Verilog
System Verilog
Universal Verification
Methodology
Linux
CAREER OBJECTIVE
Looking forward to building a career in VLSI domain.
Possessing a good knowledge in Design & Verification.
Focused on continuous improvement & learning. Ready to
learn and adapt new and relevant trends from the industry.
PROFESSIONAL TRAINING
Advanced VLSI design and verification course from Maven
Silicon VLSI Design and Training Center, Bangalore.
VLSI DOMAIN SKILLS
HDL: Verilog
HVL: System Verilog
Verification Methodologies: Constraint Random Coverage
Driven Verification Assertion Based Verification-SVA
TB Methodology: UVM
Protocols: AHB, APB
Domain: ASIC/FPGA Front-end Design and Verification
Operating System: Linux
Core skill: RTL Coding using synthesiable constructs of
verilog, code coverage, Functional coverage, synthesis,
static timing analysis.
Programming Languages: Good knowledge of OOPs
concept, class, Inheritance, Polymorphism, Digital
Electronics, Verilog, system verilog, UVM, Linux.
DESIGN SKILLS
Digital Electronics: Combinational and Sequential circuits, FSM,
Memories, CMOS implementation, Stick diagram.
Verilog Programming: Data types, Operators, Processes, BA &
NBA, Delays in Verilog, begin - end & fork join blocks, looping &
branching construct, System tasks & Functions, compiler
directives, FSM coding, Synthesis issues, Races in simulation,
pipelining RTL & TB Coding.
 PROJECT
1.ROUTER 1X3 - RTL DESIGN AND
VERIFICATION
HDL: Verilog
HVL: System Verilog
TB Methodology: UVM
EDA Tools : Questasim and ISE
Description : The router accepts
data packets on a single 8-bit
port and routes them to one of
the three output channels,
channel0, channel1, channel2.
2. AHB2APB Bridge IP Core
Verification
HDL:Verilog
HVL: System Verilog
TB Methodology: UVM
EDA Tools: Riviera Pro -Aldec
Description: The AHB to APB
bridge is an AHB slave which
works as an interface between
the
high speed AHB and the low
performance APB buses.
ACADEMIC PROJECT
POWER SAVER FOR INDUSTRIES AND
COMMERCIAL ESTABLISHMENT
STRENGTHS
Hardworking
Self learner
Creativity
LANGUAGES
Kannada
English
VERFICATIONS SKILLS
Memories: Dynamic array, Queue, Associative array,
Task & Function-Pass by reference.
Interface: Modport and clocking block.
Basic and advanced object-oriented programming:
Handle assignments, Copying the object contents,
Inheritance, polymorphism, static properties and
methods, virtual classes and parameterized classes.
Constraint Randomization: constraint overriding and
inheritance, Distribution and conditional constraints,
Soft, static and inline constraint.
Thread synchronization techniques: events,
semaphores and Mailbox-built-in methods.
Functional coverage: Cover groups, bins and cross-
coverage, CRCDV and regression testing.
System Verilog Assertions: Types of assertions,
assertion building blocks, sequences with edge
definitions and logical relationship. Sequences with
different timing relationships. clock definitions,
implication and repetition operators, different sequence
compositions, inline and binding assertions, advanced
SVA Features and assertion coverage.
UVM: UVM Objects & Components, UVM Factory &
overriding methods, Stimulus Modelling, UVM Phases,
UVM Configuration, TLM UVM Sequence, virtual
sequence & sequencer.
DECLARATION
I hereby declare that the above- mentioned information is
correct up to the best of my knowledge and I bear the
responsibility for the corrections of above mentioned
particulates.
DATE:
SAMPATH KUMAR R
PLACE: