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bprn01 Coding Test
bprn01 Coding Test
bprn01 Coding Test
During load, the counter shouldn’t load any data greater than 10. (Clock is active at
posedge, Reset is asynchronous active low). (Use tasks in the TB for relevant
operations)
RTL CODE
module mod11(input load,clk,reset,
input[3:0]data,
output reg[3:0]count);
always@(posedge clk)
begin
if(~reset)
clock<=4'd0;
else if(data)
clk<=data;
else if(count=4'd10)
else
count<=count+1'b1;
end
endmodule
TESTBENCH
module mod11_tb();
reg load,clk,rst;
reg [3:0]data;
wire[3:0]q;
integer i;
mod11 dut(load,clk,reset,data,count);
initial
begin
clk=1'b0;
forever
#5clk=~clk;
end
task initialize;
begin
load=1'b0;
clk=1'b0;
rst=1'b0;
end
endtask
task reset;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
begin
@(negedge clk)
load=m;
end
endtask
task data([3:0])n;
begin
data=n;
end
endtask
initial
begin
initialize
reset;
for(i=0;i<32;i=i+1)
begin
data(i)
end
end
initial
initial #250$finish;
endmodule