DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING

DIGITAL DESIGN
Dr. Alper SARIKAN
Spring 2023
 OUTLİNE

○ Synchronous Logic Circuits

○ Latch
○ Flip-Flop
○ Timing
○ Counters
○ Shift Register

Synchronous Logic Circuits 2

 SYNCHRONOUS LOGİC
CİRCUİTS
○ Synchronous logic circuits unlike the combinational logic
circuits remember previous inputs.
○ The basic memory elements are latch and flip-flop.
○ Clock signal is used to guarantee synchronous operation
among the memory elements.
○ In literature, there are asynchronous logic circuits which use
feedback to generate memory. But the performance of these
circuits depends on the gate delays. Therefore, it is not easy
to guarantee their performance with the changes of supply
voltage and temperature.

Synchronous Logic Circuits 3

 D-LATCH

○ Latches operate based on

the logic level of clock
signal.
○ Positive level triggered D-
Latch copies its input to its
output if the logic level of
the gate ( also called clock )
signal is high.
○ If the logic level of the gate
signal is low, it will keep the
last output at the falling
edge gate signal.

Synchronous Logic Circuits 4

 D-LATCH
Positive Level Triggered D-Latch

Negative Level Triggered D-Latch

Synchronous Logic Circuits 5

 D-LATCH

○ To synthesize D-Latch, a IF
or CASE statement without
fully defined outputs is
adequate.
○ If G is equal to 1, D input is
assigned to Q output.
○ However, if G is equal to 0,
the operations is not
defined.
○ Therefore, synthesizer
generates a latch to store
the Q output if G is 0.

Synchronous Logic Circuits 6

 D-LATCH

○ After the power-up and

before the logic level of
clock signal is high, the
output of D-Latch is
undefined.
○ To prevent this, a
asynchronous reset or set
signal is used.
○ The output is set to 0 if
reset is high, 1 if set is high.
○ During normal operation
reset and set signals are 0.

Synchronous Logic Circuits 7

 SR-LATCH

○ SR-Latch can be coded

using data flow statements.
○ However, the synthesizer
can not synthesize this
circuit because of the
asynchronous feedback.

Synchronous Logic Circuits 8

 SR-LATCH

○ Synthesizer friendly SR-

Latch can be written using
behavioral coding.
○ However, synthesizer uses
D-Latches to realize it.

Synchronous Logic Circuits 9

 JK-LATCH

○ The S=0 and R=0 problem

in SR-Latch is solved in JK-
Latch.
○ Since FPGA does not have
JK-Latch, synthesizer
realizes it using D-Latch

Synchronous Logic Circuits 10

 FLİP-FLOP

○ Using Latches in a feedback may create unwanted

oscillations.
○ For example, the output of the circuit below oscillates is clk is
1 and x is 1.
○ This unwanted operation is prevented by using edge
triggered flip-flop instead of using level triggered latch

Synchronous Logic Circuits 11

 D FLİP-FLOP

○ The widely used edge-

triggered flip-flop is D Flip-
Flop.
○ If the D input is sampled at
rising edge of clock, it is
called rising edge triggered
D Flip-Flop.
○ If the D input is sampled at
falling edge of clock, it is
called falling edge triggered
D Flip-Flop.

Synchronous Logic Circuits 12

 D FLİP-FLOP
Rising Edge Triggered D Flip-Flop

Falling Edge Triggered D Flip-Flop

Synchronous Logic Circuits 13

 D FLİP-FLOP

○ In VHDL, process is
sensitive to signal, so the
rising edge or falling edge
must be checked using a if
statement.
○ In Verilog, the edge of the
clock signal is checked in
the sensitivity list using
posedge or negedge
commands.
○ The process and always are
only sensitive to clock
signal.
Synchronous Logic Circuits 14
 D FLİP-FLOP

○ After the power-up the

output of D Flip-Flop is not
defined.
○ To guarantee proper
operation, asynchronous set
and reset signals are used

Synchronous Logic Circuits 15

 D FLİP-FLOP

○ If asynchronous set or reset signal

changes at the same time with
clock signal, it is possible that D
Flip-Flop samples incorrectly.
○ To prevent this issue a
synchronous set-reset D Flip-Flop
may be used.

Synchronous Logic Circuits 16

 D FLİP-FLOP

○ Since the clock signal is

routed to every flip-flop,
special logic buffers are used
on the clock signals.
○ If a flip-flop should be driven
with lower clock signal an
enable signal is used

Synchronous Logic Circuits 17

D FLİP-FLOP

Synchronous Logic Circuits 18

 T FLİP-FLOP

○ T Flip-flop is widely used in

counter design.
○ Since there is no T Flip-Flop
in the FPGA, the
synthesizer uses D Flip-Flop
to realize T Flip-Flop

Synchronous Logic Circuits 19

 TİMİNG

○ The output of a flip-flop requires some time to change once

the edge of the clock signal is applied.
○ Before and after the rising or falling edge of the clock signal
the D input must be kept constant.
○ The amount of these time values depends on the technology,
and must be satisfied for every flip-flop in a design.
Synchronous Logic Circuits 20
 TİMİNG

○ In a complex design, there are combinational circuits among

flip-flops.
○ The clock signal also arrives at different times due to the
delay on clock buffer circuits
○ The timing requirement of flip-flops must be guaranteed
even there is a delay due to the combinational circuits.
Synchronous Logic Circuits 21
 TİMİNG

○ Many digital circuits have thousands or millions of flip-flops.

○ The timing requirement of each must be satisfied.
○ To check timing automatically, static timing analyzer is used.
○ This tool calculates setup slack and hold slack for every flip-
flop in the design.
○ If the slack is below zero, an error is issued.
○ Synthesizer, place and route tool use static timing analyzer
results to change the circuit in order to meet timing.

Synchronous Logic Circuits 22

 TİMİNG

○ For successful operation,

setup slack and hold slack
must be greater than zero for
every specified temperature,
supply voltage and process
changes.
○ If the slack is below zero for
any condition, the circuit will
not work at that condition.
○ It is not easy to find timing
problems on the field, so all
digital circuits must be timing
closed before released to the
field.

Synchronous Logic Circuits 23

 TİMİNG WİTH VİVADO

○ Static timing analyzer in Vivado requires frequency of clocks

used in design and the relationship among clocks to calculate
setup slack and hold slack.
○ Clock signal is defined in XDC file using create_clock

○ If the rising edge time and falling edge time values are not
given, it is assumed that the clock has 50% duty cycle.

○ The frequency of the clock generator on BASYS3 is 100MHz.

Synchronous Logic Circuits 24

 TİMİNG WİTH VİVADO

○ If a lower frequency clock is generated using a clock defined

using create_clock command, the relationship between these
clocks must also be defined.

○ For example, clk_2 net is a clock signal and generated from

CLK signal by dividing its frequency by 2

○ If the CLK signal frequency is 100MHz, then clk_2 frequency

is 50MHz.

Synchronous Logic Circuits 25

 TİMİNG WİTH VİVADO

○ Defining only clock signal properties is not enough for

successful timing closure.
○ The relationship between input signals and clock signal must
be also defined.

○ For example, if there is a 5ns between input and clock

Synchronous Logic Circuits 26

 TİMİNG WİTH VİVADO

○ The delay between output and clock edge is defined using

○ For example, to define 2ns delay between output and clock

Synchronous Logic Circuits 27

 TİMİNG WİTH VİVADO

○ Some signals, such as reset, do not have any timing

requirement.
○ In this case they defined as

○ The time of the edge of clock signal changes due to noise.

○ This unwanted uncertainty is defined as

○ A system wide jitter is defined as

Synchronous Logic Circuits 28

 COUNTERS

○ Counters are used to

generate low frequency
clock, trigger an event after
a predetermined time, and
etc.
○ A N-Bit counter counts up
to 2 N -1.
○ After it reaches its
maximum value, it will
return to 0.

Synchronous Logic Circuits 29

 COUNTERS

○ If the counter needs to

count a value less than its
maximum value allowed by
number of bits, it should be
checked using a if
statement.
○ To calculate required
number of bits, chose
integer N using this formula

Synchronous Logic Circuits 30

 SHİFT REGİSTER

○ Shift register shifts input

data into the next flip-flop
at every clock cycle.
○ It is used to convert serial
data to parallel or parallel
data to serial.

Synchronous Logic Circuits 31