Câu 1: Choose correct set of registers for x86 processor in 16-bit real

mode:
a, Data pointer in data segment DS: BX
b, Data pointer to source memory in extra segment ES: SI
c, Pointer to variable in stack SS: BP
d, Instruction pointer CS: IP
1. BX
2. IP,
3. AX
4. SI
5. BP
Giải thích:
1. Data pointer in data segment DS: Đây là một con trỏ dữ liệu trong
phân đoạn dữ liệu (DS). Thanh ghi thường được sử dụng là BX.
2. Data pointer to source memory in extra segment ES: Đây là một con
trỏ dữ liệu nguồn trong phân đoạn bổ sung (ES). Thanh ghi thường được
sử dụng là SI.
3. Pointer to variable in stack SS: Đây là một con trỏ đến biến trong ngăn
xếp (SS). Thanh ghi thường được sử dụng là SP (Stack Pointer) hoặc BP
(Base Pointer).
4. Instruction pointer CS: Đây là con trỏ lệnh trong phân đoạn mã (CS).
Thanh ghi thường được sử dụng là IP.
Câu 2: Key parameters to consider when evaluating processor hardware
include:
Select one or more:
a. Size
b. Reliability
c. Address bus size
d. power consumption
e. databus size
f. cost
g. performance
Câu 8: In the RCL instruction, the contents of the destination operand
undergoes function as
Select one:
A, carry flag is pushed into LSB then MSB is pushed into carry flag
B, overflow flag is pushed into MSB then LSB is pushed into carry flag
C, auxiliary flag is pushed into LSB then MSB is pushed into carry flag

D, carry flag is pushed into MSB then LSB is pushed into carry flag

Giải thích:
Trong lệnh RCL (Rotate through Carry Left) của bộ xử lý x86, nội dung của
toán hạng đích sẽ trải qua các thay đổi theo cách sau:
 Bit ít quan trọng nhất (LSB) của toán hạng đích sẽ nhận giá trị từ cờ
Carry (CF).
 Bit quan trọng nhất (MSB) của toán hạng đích sẽ được đẩy vào cờ Carry
(CF).
Điều này có nghĩa là:
 Cờ Carry (CF) được đẩy vào LSB.
 MSB được đẩy vào cờ Carry (CF).
Câu 9: As a consequence of Moore's law: the number of transistors on a single
chip continues to grow year by year. Together with the increasing clock speed
to increase the performance, power consumption in processor chips rises fast.
What design engineers had made to increase processor performance but still
keep the heat dissipation at a proper level.

Select one:
a. produce on-chip and off-chip cache memory

b. lower internal clock speed of CPU

c. make wider data bus to increase the bandwidth between processor and
main memory

d. produce multicore processor chip

Câu 10: What is the meaning of Amdahl's law in processor performance

nation?

Select one:
a. the maximum speedup of a multicore processor

b. the speedup of a multicore processor when increasing system bus speed

c. the potential speedup of a program using multiple processor
compared to a single processor

d. the cost reduce when moving from single-core to multicore processor

Câu 14: Which ones are not correct for static RAM?

Select one or more:

a. Cost per bit is higher than dynamic RAM

b. faster than dynamic RAM because they are made from capacitor

c. Cheaper than dynamic RAM because simpler chip controller

d. Cost per bit is lower than dynamic RAM

Câu 15: Which of the following functions are basic to a computer system?

Select one or more:

a. Direct memory access

b. Control

c. Data processing

d. Data storage

e. Interrupt

f. Data movement

Câu 17: if the offset of the operand is stored in one of the index registers, then
it is
Select one:
a. based indexed addressing mode
b. indexed addressing mode

c. register indirect addressing mode

d. relative based indexed addressing mode

Câu 19: Which set of registers point to the next instruction?

Select one:
a. ES:IP

b. CS:IR

c. CS:IP
 d. CS:PC

Câu 22: Which one best describe cache hit and cache miss?

1. the number of memory accesses that the CPU can retrieve from the
cache per the total number of memory accesses (Cache hit)

2. the number of memory accesses that CPU must retrieve from the main
memory per the total number of memory accesses (Cache miss)

3. the number of memory accesses that hit the cache per the total access
Câu 24: Choose correct features for SRAM and DRAM

1. Slower access time, cheaper cost per bit, can manufacture with larger
size
2. Faster access time, cheaper cost per bit, can manufacture with larger size
3. Faster access time, cost more per bit, smaller size
4. Slow access time, cheaper cost per bit, can only manufacture at larger
size
• SRAM: Faster access time, cost more per bit, smaller size.
• DRAM: Slower access time, cheaper cost per bit, can manufacture
with larger size.
Câu 27: When many devices of different transmission speed connect to the
same bus, the overall system performance suffers. How did the design
engineers resolve this issue:

Select one:
a. Multiple-Bus hierarchy

b. Split system bus into local bus and memory bus

c. PCI Express bus

d. PCI bus

Câu 31: Match correct definitions of Computer Organization and Architecture

1. attribute of the system visible to a programmer such as instruction set,

bits, bytes...4

2. Operational units and their interconnections including hardware details

such as control signals, interfaces with peripherals or memory
technology

3. Interconnection among computer module such as processor, IO,

memory...

 Computer Organization: 2. Operational units and their interconnections

including hardware details such as control signals, interfaces with peripherals or
memory technology
 Architecture: 1. Attribute of the system visible to a programmer such as
instruction set, bits, bytes…
Câu 37:Match the correct definition of flag bits in PSW.

a. indicates the result of an arithmetic or comparison operation ZF

b. indicates the overflow of leftmost bit of data after an arithmetic

operation. OF

c. contains the carry from bit 3 to bit 4 following an arithmetic operation.

AF

d. shows the sign of the result of an arithmetic operation. SF

Step 1: Fetch opcode

Step 2: Decode

Step 3: Calculate operand address

Step 4: Fetch operand

Step 5: Execution

Step 6: Store result

Câu này ko bt làm theo thui