NCU-FRM-02

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FACULTY: TUTORIAL SHEET

School/ Department: EECE Tutorial sheet no: 6

Class: ECE, CSE
Subject Name: Digital Electronics & Name of Faculty: Dr. Sharda Vashisth
Computer Architecture
Subject Code: ECL255 Semester: III/IV
Unit/ Title: Unit 4 Sequential Circuits

Learning objectives:

1. Design Flip Flops

2. Design Registers
3. Design Counters

Q1. Convert D Flip flop to JK flip flop

Q.2 Convert JK Flip flop to SR Flip flop.
Q.3 What is lock out condition in counters? What is the solution to overcome this
problem?
Q.4 Write Boolean equation for JK Flip flop.
Q.5 Write Characteristics equation for T Flip flop.
Q.6 If at some instance prior to the occurrence of the clock edge, P, Q and R have a value
0, 1 and 0 respectively in Fig.1, what shall be the value of PQR after the clock edge?

Fig.1

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Q7. For the circuit shown in Fig.2, two 4-bit parallel-in serial-out shift registers loaded
with the data shown are used to feed the data to a full adder. Initially, all the flip-flops
are in clear state. After applying two clock pulses, what are the outputs S & C0 of the
full-adder?

Fig.2
Q8. Design a synchronous counter with the following repeated binary sequence using T
Flip flops.
2, 4, 6, 7, 1, 0, 2
Q9. The circuit shown in Fig. 3 is made with two D-type flip flops. Assume that Q0 and Q1
are both low initially. Sketch a timing diagram showing the waveforms of CLK, Q0
and Q1 for the next six clock pulses.

Fig. 3
Q.10 A Mod-N counter using a synchronous binary UP counter with asynchronous clear
input is shown in Fig. 4. What is the value of N? Show the complete solution.

Fig. 4
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