PRACTICE TEST VLSI DTECH.

& DESIGN MCQ

1.Which is not true for VLSI technology:
a. reduce cost b. reduce parasitic effect c. reduce size d. none of these
2. In nature silicon is available as :
a. Silicon b. Oxide silica c. silicate d. both b & c
3. Which is the fastest switching device?
a. BJT b. MOSFET c. JEFT d. Diode
4. Produce MGS by heating Silica with----------------------------.
a. SiC b. SiO2 c. Si d. SiO
5.In CMOS logic circuit the p-MOS transistor acts as:
a) Pull down network b) Pull up network c) Load d) Short to ground

6. Which model is used for scaling?

a) constant electric scaling b) constant voltage scaling
c) costant electric and voltage scaling d) costant current model

7. Gate area is scaled by

a) α b) 1/α c) 1/α2 d) α2

8. The Junction parasitic capacitance are produced due to

a) Source diffusion regions b) Gate diffusion regions
c) Drain diffusion region d) All of the mentioned

9. The evolution of PLD began with _

a) EROM b) RAM c) PROM d) EEPROM

10. When both the AND and OR are programmable, such PLDs are known as __________
a) PAL b) PPL c) PLA d) APL

11.The difference between FPGA and PLD is that __

a) FPGA incorporates logic blocks b) FPGA has high power dissipation
c) FPGA is slower than PLD d) All of the Mentioned
12. Dynamic memory cells use ___ as the storage device.
a) The reactance of a transistor b) The impedance of a transistor
c) The capacitance of a transistor d) The inductance of a transistor
13. The initial step involved in the IC fabrication is
a) Metallization b)Ion implantation c)Oxidation d)Silicon wafer preparation
14. SPICE in VLSI stand for
a) Software Process Improvement and Capability determination
b) Simulation Program with Integrated Circuit Emphasis
c) Scientific Personal Integrated Computing Environment d) None
15. Which one is not the SPICE model
a) Device model b) circuit model c) Sub-circuit model d) None of these
16. Pipelining is a technique where we
a) divide combinational path in to multiple parts b) divide the critical path in to multiple small paths
c)increase the clock speed and the throughput of the circuit d) All of these
17. Fan-out is maximum in
a) nMOS b) CMOS c) pMOS d) ECL

18. Propagation delay is least in

a) MOS b) CMOS c) TTL d) ECL

19.The CMOS gate circuit of NOT gate has

a) pMOS upper & nMOS lower b) nMOS upper & pMOS lower
c) MOS upper & FET lower d) none of these

20.In CMOS logic circuit the n-MOS transistor acts as:

a) Pull down network b) Pull up network
c) Load d) Short to ground
21. According to body effect, substrate is biased with respect to ___________

a) source b) drain
c) gate d) Vss

22. α is used for scaling

a) linear dimensions b) vdd c) oxide thickness d) non linear
23. Advantage of Scaling is/ are
a) Increase the switching speed b) Reduce the chip size
c) reduce power dissipation d) All of the mentioned

24. The evolution of PLD began with

a) EROM b) RAM c) PROM d) EEPROM

25. When only the AND array is programmable and OR array is not programmable, such PLDs are known as
a) PAL b) PPL c) PLA d) APL

26. If both the transistors are in saturation, then they act as ________
a) current source b) voltage source
c) divider d) buffer 8.
27. Which of the following is dominant component in input capacitance?
a) Gate diffusion capacitance
b) Gate parasitic capacitance
c) Gate oxide capacitance
d) All of the mentioned

28. The last step involved in the IC fabrication is

a) Metallization b) Packaging c) Simulation d) Silicon wafer preparation
29. Which one is not the scaling model?
a) constant electric field scaling (α = β) b) Full scaling model (α = β)
c) constant voltage scaling (β=1) d) constant electric field scaling ( β=1)
30. Device model & Sub-circuit model are
a) Scaling Model b) SPICE model c) CMOS model d) None of these
 31. What is a MOS transistor?
a) minority carrier device b) majority carrier device
c) majority & minority carrier device d) none of the mentioned

32. In CMOS

a) Fan-out is minimum b) Fan-out is maximum

c) Propagation delay is least d) None of these

33. In ECL

a) Propagation delay is least b) Propagation delay is maximum

c) Fan-out is maximum d) None of these
34. Vdd is scaled by
a) α b) β c) 1/α d) 1/β
35. VLSI technology uses ________ to form integrated circuit.
a) transistors b) switches c) diodes d) buffers

36. Medium scale integration has ____________

a) ten logic gates b) fifty logic gates c) hundred logic gates d) thousands logic gates

37. _________ is used to deal with effect of variation.

a) chip level technique b) logic level technique
c) switch level technique d) system level technique

38. ______ architecture is used to design VLSI.

a) system on a device b) single open circuit c) system on a chip d) system on a circuit

39. What is the design flow of VLSI system?

i. architecture design ii. market requirement iii. logic design iv. HDL coding

a) ii-i-iii-iv b) iv-i-iii-ii c) iii-ii-i-iv d) i-ii-iii-iv

40. ______ is used in logic design of VLSI.

a) LIFO b) FIFO c) FILO d) LILO

41.In negative logic convention, the Boolean Logic [1] is equivalent to:
a) +VDD b) 0 V c) –VDD d) None of the mentioned

42. In CMOS logic circuit the n-MOS transistor acts as:

a) Load b) Pull up network c) Pull down network d) Not used in CMOS circuits

43. In CMOS logic circuit the p-MOS transistor acts as:

a) Pull down network b) Pull up network c) Load d) Short to ground

44. In CMOS logic circuit, the switching operation occurs because:

a) Both n-MOSFET and p-MOSFET turns OFF simultaneously for input ‘0’ and turns ON simultaneously for input
‘1’
b) Both n-MOSFET and p-MOSFET turns ON simultaneously for input ‘0’ and turns OFF simultaneously for input
‘1’
c) N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF for input ‘1’ and N-MOS
transistor turns OFF, and p-MOS transistor turns ON for input ‘0’
d) None of the mentioned

45. When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is:
a) 1 or Vdd or HIGH state b) 0 or ground or LOW state
c) High impedance or floating(Z) d) None of the mentioned
46. When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is:
a) 1 or Vdd or HIGH state b) 0 or ground or LOW state
c) Crowbarred or Contention(X) d) None of the mentioned

47. Design rules does not specify __________

a) linewidths b) separations c) extensions d) colours
48. Which design method occupies or uses lesser area?
a) lambda rules b) micron rules c) layer rule d) source rule
49. Which model is used for scaling?
a) constant electric scaling b) constant voltage scaling
c) costant electric and voltage scaling d) costant current model
50. α & β are used for scaling
a) linear dimensions & vdd b) vdd
c) oxide thickness d) non linear dimension
51. For constant voltage model,
a) α = β b) α = 1 c) α = 1/β d) β = 1

52. For constant electric field model,

a) β = α b) α = 1 c) α = 1/β d) β = 1
53.Gate area can be given as
a) L/W b) L * W c) 2L/W d) L/2W
54. Gate area is scaled by
a) α b) 1/α c) 1/α2 d) α2
55. Gate capacitance per unit area is scaled by
a) α b) 1 c) 1/β d) β

56. Parasitic capacitance is given by

a) Ax/d b) Ax * d c) d/Ax d) Ax

57. Parasitic capacitance is scaled by

a) β b) 1/β c) α d) 1/α

58. Carrier density is scaled by

a) α b) β c) 1 d) α2

59. Channel resistance Ron is scaled by

a) α b) β c) 1 d) α2

60. Gate delay is given by

a) Ron/Cg b) Ron * Cg c) Cg/Ron d) Cg2 /Ron
61. Maximum operating frequency is scaled by
a) α/β b) β/α c) α2 /β d) β2 /α

62. Saturation current is scaled by

a) α b) β c) 1/α d) 1/β

63. In constant voltage model, the saturation current is scaled by

a) α b) β c) 1 d) β2

64. In constant field model, maximum operationg frequency is scaled by

a) α b) β c) α2 d) β2

65. In constant electric field model, power dissipation per unit area is scaled by
a) α b) β c) 1 d) β2

66.The junction parasitic capacitance are produced due to ____________

a) Source diffusion regions b) Gate diffusion regions
c) Drain diffusion region d) All of the mentioned
67. The amount of parasitic capacitance at the output node is determined by __________
a) Concentration of the impurity doped b) Size of the total drain diffusion area
c) Charges stored in the capacitor d) None of the mentioned
68. The dominant component of the total output capacitance in submicron technology is?
a) Drain diffusion capacitance b) Gate oxide capacitance
c) Interconnect capacitance d) Junction parasitic capacitance
69. Stick diagrams are those which convey layer information through?
a) thickness c) shapes d) layers
70. Which color is used for n-diffusion?
a) red b) blue c) green d) yellow
71. n and p transistors are separated by using __________
a) differentiation line b) separation line c) demarcation line d) black line

.72. The parameter which is not scaled to any factor is:

a) Power speed product
c) Channel resistance
73. nMOS devices are formed in ____________
a) p-type substrate of high doping level
c) p-type substrate of moderate doping level
b) Switching energy
d) All of the mentioned
b) n-type substrate of low doping level
d) n-type substrate of high doping level

74. In depletion mode, source and drain are connected by ____________

a) insulating channel b) conducting channel c) Vdd d) Vss
75. What is the condition for non saturated region?
a) Vds = Vgs – Vt b) Vgs lesser than Vt
c) Vds lesser than Vgs – Vt d) Vds greater than Vgs – Vt
76. In enhancement mode, device is in _________ condition.
a) conducting b) non conducting c) partially conducting d) insulating
77. nMOS is ____________
a) donor doped b) acceptor doped c) all of the mentioned d) none of the mentioned
78. Inversion layer in enhancement mode consists of excess of ____________
a) positive carriers b) negative carriers c) both in equal quantity d) neutral carriers
79. As source drain voltage increases, channel depth ____________
a) increases b) decreases c) logarithmically increases d) exponentially increases
80. Depletion mode MOSFETs are more commonly used as ____________
a) switches b) resistors c) buffers d) capacitors

81. Enhancement mode device acts as ____ switch, depletion mode acts as _____ switch.
a) open, closed b) closed, open
c) open, open d) close, close

82. If the gate is given sufficiently large charge, electrons will be attracted to ____________
a) drain region b) channel region c) switch region d) bulk region

83. In N channel MOSFET which is the more negative of the elements?

a) source b) gate c) drain d) source and drain

84. The gate region consists of ____________

a) insulating layer b) conducting layer c) lower metal layer d) p type layer

85. MOS transistors consist of which of the following?

a) semiconductor layer b) metal layer c) layer of silicon-di-oxide d) all of the mentioned

86. The PLL device is:

a) Feedback system that compares output frequency and input frequency
b) Feedback system that compares output phase and input phase
c) Linear system that compares output resistance and input resistance
d) Non Linear system that compares output current and input current

87. The Logic gate that works similar to phase detector is:
a) AND gate b) OR gate c) XOR gate d) NOT gate

88. The aligning of output phase of voltage controlled oscillator with reference is called:
a) Phase compensation b) Phase alignment c) Phase Locking d) Phase detecting

89. Instead of Phase detection, if Frequency detector is used the drawback PLL would face is:
a) Finite difference between input and output frequency
b) Equality cannot be established if PLL compared input and output frequency rather than pulses
c) Error between Vin and Vout cannot be removed d) All of the mentioned

90. If high pass filter is used instead of Low pass filter in the PLL the response of PLL would be:
a) Output Voltage is not a square wave
b) Output Voltage contains many high frequency waves
c) VCO will be unstable due to variations in control voltage d) All of the mentioned

91. Number of poles in Type 1 PLL is:

a) 0 b) 1 c) 2 d) None of the mentioned

92. The transfer function of Phase Detector is :

a) Constant b) Varies with frequency c) Varies with voltage d) None of the Mentioned

93. In which design, dissipation is less?

a) nMOS b) pMOS c) CMOS d) BiCMOS
94. Which implementation is slower?
a) NAND gate b) NOR gate c) AND gate d) OR gate

95. Static RAM uses ____________ transistors.

a) four b) five c) six d) seven

96. Flash memory is a non-volatile storage device in which data

a) can be erased physically b) can be erased magnetically
c) can be erased electrically d) cannot be erased

97. Which is a comparatively slower device?

a) ROM b) RAM c) flash memory d) SRAM

98. Noise in VLSI circuits mean:

a) Unwanted signals that arise due to vibration in the passive circuits
b) Unknown signal that limits the minimum signal level that a circuit can process with acceptable quality
c) Signal which undergoes distortion
d) All of the mentioned

99. Noise Margin is:

a) Amount of noise the logic circuit can withstand b) Difference between VOH and VIH
c) Difference between VIL and VOL d) All of the Mentioned

100. The Lower Noise Margin is given by:

a) VOL – VIL b) VIL – VOL
c) VIL ~ VOL(depends on which one is greater) d) All of the Mentioned

101. The Higher Noise Margin is given by:

a) VOH – VIH b) VIH – VOH c) VIH ~ VOH d) All of the mentioned

102. The noise immunity ____________ with noise margin.

a) Decreases b) Increases c) Constant d) None of the Mentioned

103. SSI refers to ___________

a) Small Scale Integration b) Short Scale Integration c)
Small Set Integration d) Short Set Integration

104. Small Scale Integration(SSI) refers to ICs with __________ gates on the same chip.
a) Fewer than 10 b) Greater than 10 c) Equal to 10 d) Greater than 50

105. MSI means ___________

a) Merged Scale Integration b) Main Scale Integration
c) Medium Scale Integration d) Main Set Integration

106. MSI includes _______ gates per chip.

a) 12 to 100 b) 13 to 50 c) greater than 10 d) greater than 100

107. LSI means ________ and refers to ________ gates per chip.
a) Long Scale Integration, more than 10 upto 10000
b) Large Scale Integration, more than 100 upto 5000
c) Large Short Integration, less than 10 and greater than 5000
d) Long Short Integration, more than 10 upto 10000
108. Integrated circuits are classified as ___________
a) Large, Small and Medium b) Very Large, Small and Linear
c) Linear and Digital d) Non-Linear and Digital

109. According to the IC fabrication process logic families can be divided into two broad categories as
a) RTL and TTL b) HTL and MOS c) ECL and DTL d) Bipolar and MOS

110. The full form of DIP is ___________

a) Dual-in-Long Package b) Dual-in-Line Package
c) Double Integrated Package d) Double-in-Line Package

111. MOS families includes __________

a) PMOS and NMOS b) CMOS and NMOS c)
PMOS, NMOS and CMOS d) EMOS, NMOS and PMOS

112. Fan-in is defined as __________

a) the number of outputs connected to gate without any degradation in the voltage levels
b) the number of inputs connected to gate without any degradation in the voltage levels
c) the number of outputs connected to gate with degradation in the voltage levels
d) the number of inputs connected to gate with degradation in the voltage levels

113. For enhancement mode n-MOSFET, the threshold voltage is:

a) Equal to 0 b) Greater than zero or Positive quantity
c) Negative voltage or lesser than zero d) All of the mentioned

114. The conductivity of the pure silicon is raised by:

a) Introducing Dopants b) Increasing Pressure
c) Decreasing Temperature d) Deformation of Lattice

115. The n-type semiconductor have _______ as majority carriers.

a) Holes b) Negative ions c) Electrons d) Positive ions

116. ROM consist of __________

a) NOR and OR arrays b) NAND and NOR arrays
c) NAND and OR arrays d) NOR and AND arrays

117. For reprogrammability, PLDs use __________

a) PROM b) EPROM c) CDROM d) PLA

118. PLDs with programmable AND and fixed OR arrays are called __________
a) PAL b) PLA c) APL d) PPL

119. When both the AND and OR are programmable, such PLDs are known as __________
a) PAL b) PPL c) PLA d) APL

120. ASIC stands for __________

a) Application Special Integrated Circuits b) Applied Special Integrated Circuits
c) Application Specific Integrated Circuits d) Applied Specific Integrated Circuits

121. The programmability and high density of PLDs make them useful in the design of __________
a) ISAC b) ASIC c) SACC d) CISF
122. FPGA stands for __________
a) Full Programmable Gate Array b) Full Programmable Genuine Array
c) First Programmable Gate Array d) Field Programmable Gate Array

123. Which of the following is a reprogrammable gate array?

a) EPROM b) FPGA c) Both EPROM and FPGA d) ROM

124. The difference between FPGA and PLD is that __________

a) FPGA is slower than PLD b) FPGA has high power dissipation
c) FPGA incorporates logic blocks d) All of the Mentioned

125. nMOS fabrication process is carried out in ____________

a) thin wafer of a single crystal b) thin wafer of multiple crystals
c) thick wafer of a single crystal d) thick wafer of multiple crystals

126. The photoresist layer is exposed to ____________

a) Visible light b) Ultraviolet light c) Infra red light d) LED

127. In diffusion process ______ impurity is desired.

a) n type b) p type c) n p type d) none of the mentioned

128. Oxidation process is carried out using __________

a) hydrogen b) low purity oxygen c) sulphur d) nitrogen

129. Photoresist layer is formed using __________

a) high sensitive polymer b) light sensitive polymer
c) polysilicon d) silicon di oxide

130. Few parts of photoresist layer is removed by using __________

a) acidic solution b) neutral solution c) pure water d) diluted water

131. What is Lithography?

a) Process used to transfer a pattern to a layer on the chip
b) Process used to develop an oxidation layer on the chip
c) Process used to develop a metal layer on the chip
d) Process used to produce the chip

132. Silicon oxide is patterned on a substrate using ____________

a) Physical lithography b) Photolithography
c) Chemical lithography d) Mechanical lithography

133. Positive photo resists are used more than negative photo resists because ___________
a) Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as
that of the positive photo resists
b) Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of
the negative photo resists
c) Negative photo resists are less sensitive to light
d) Positive photo resists are less sensitive to light

134. The ______ is used to reduce the resistivity of poly silicon.

a) Photo resist b) Etching
c) Doping impurities d) None of the mentioned
135. The dopants are introduced in the active areas of silicon by using which process?
a) Diffusion process b) Ion Implantation process
c) Chemical Vapour Deposition d) Either Diffusion or Ion Implantation Process

136. To grow the polysilicon gate layer, which of the following chemical is used for chemical vapour deposition?
a) Silicon Nitride(Si3N4) b) Silane gas(SiH4) c) Silicon oxide d) None of the mentioned

137. Chemical Mechanical Polishing is used to ___________

a) Remove silicon oxide b) Remove silicon nitride and pad oxide
c) Remove polysilicon gate layer d) Reduce the size of the layout

138. Simulator converts circuit information to

a) design plan b) does verification c) set of equations d) floor plan

139). The circuit should be tested at

a) design level b) chip level c) transistor level d) switch level

140).Moore’s law is related to

a)speed of operation of bipolar device b)level of integration of MOS devices

c) speed of operation of MOS device d) none of these

141) Submicron CMOS technology is

a) faster b) slower c) large d) slow and large

142) ________ is used with silicon to satisfy the need for very high speed integrated technology.
a) gallium oxide b) gallium arsenide c) silicon dioxide d) aluminium

143. In the process of Czochralski method which of the following relation is appropriate between the melt and the
growing crystals?
a) Melt and the growing crystals are usually not related to each other
b) Melt and the growing crystals are usually rotated counterclockwise
c) Melt and the growing crystals are usually rotated clockwise
d) Melt and the growing crystals are usually kept at a constant position

144). What is the advantage of using Czochralski method?

a) Gives small crystals b) High tech apparatus
c) Rapid growth rates d) Uses plasma torch

145). Chemical vapour deposition is a method which is used to obtain which of the following substance?
a) Semiconductors b) Non conducting polymers
c) Conducting compounds d) Crystalline semiconductor

146) In the chemical vapour deposition the films formed are formed by decomposition of what kind of substances?
a) Liquid molecules b) Conducting polymers
c) Gaseous molecules d) Solid molecules

147). Sheet resistance of a semiconductor is ___________

a) Inherent property of the material b) Function of thickness of the material
c) Also called as Specific Resistance d) All of the mentioned

148). MOS transistor structure is ____________

a) symmetrical b) non symmetrical c) semi symmetrical d) pseudo symmetrical
149). What is the condition for linear region?
a) Vgs lesser than Vt b) Vgs greater than Vt
c) Vds lesser than Vgs d) Vds greater than Vgs

150. The interconnect capacitance is formed by __________

a) Area between the interconnect lines b) Interconnect lines between the gates
c) Inter electrode capacitance of interconnect lines d) None of the mentioned