Lecture 26 – Buffered Op Amps (6/25/14) Page 26-1

LECTURE 26 – BUFFERED OP AMPS

LECTURE ORGANIZATION
Outline
• Introduction
• Open Loop Buffered Op Amps
• Closed Loop Buffered Op Amps
• Use of the BJT in Buffered Op Amps
• Summary
CMOS Analog Circuit Design, 3rd Edition Reference
Pages 354-370

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-2

INTRODUCTION
Buffered Op Amps
What is a buffered op amp?
Buffered op amps are op amps with the ability to drive a low output resistance and/or
a large output capacitance. This requires:
- An output resistance typically in the range of 10  Ro  1000
- Ability to sink and source sufficient current (CL·SR)
Rout Rout
+ Large Small
vIN vOUT
- vOUT’
Op Amp Buffer 070430-01

Types of buffered op amps:

- Open loop using output amplifiers
- Closed loop using negative shunt feedback to reduce the output resistance of the op
amp

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Lecture 26 – Buffered Op Amps (6/25/14) Page 26-3

OPEN LOOP BUFFERED OP AMPS

The Class A Source Follower as a Buffer
• Simple VDD
gm vIN M1
• Small signal gain ≈ g + g <1
m mbs + GL vOUT
• Low efficiency VNBias1
1 M2
• Rout = ≈ 500 to 1000
gm + gmbs
060118-10
• Level shift from input to output
• Maximum upper output voltage is limited
• Broadbanded as the pole and zero due to the source follower are close so compensation
is typically not a problem

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-4

The Push-Pull Follower as a Buffer

• Voltage loss from 2 cascaded followers VDD VDD
 gm3  gm1  VPBias1 M5
Av ≈ g + g  <1 I5 M1 I1
 m3 g
mbs3 m1 + g mbs1 + G L
VSG3 + V
• Higher efficiency DD V +
- GS1-
0.5 vIN M3 vOUT
• Rout ≈ g + g ≈ 250 to 500
m mbs VDD
M4
• Current in M1 and M2 determined by:
+ VSG2 + VDD
VGS4 + VSG3 = VGS1 + VSG2 VGS4 -
-
VNBias1 I6 I
2I6 2I5 M2 2
M6
Kn'(W4/L4) + Kp'(W3/L3) 060706-02

2I1 2I2
= Kn'(W1/L1) + Kp'(W2/L2)
Use the W/L ratios to define I1 and I2 from I5 and I6
• Maximum positive and negative output voltages are limited

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-5

Two-Stage Op Amp with Follower

VDD

M6
M3 M4 Cc M8

vout
- M1 M2
vin
+ CL
M5 I5 M7 I7 M9 I9
VNBias

060706-03

Power dissipation now becomes (I5 + I7 + I9)VDD

Gain becomes,
 gm1   gm6   gm8 
Av = g +g  g +g  g + g 
+g +g
 ds2 ds4  ds6 ds7  m8 mbs8 ds8 ds9

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-6

Source-Follower, Push-Pull Output Op Amp

VDD
M6 M9
M17

IBias M5 M10 I17

M22
R1 M8
M11
VSG18 + VSS
+
- VDD V
GS22
M7 M12 M18 - vout
Cc M19
R1 CL
M15 VSS
+
VGS19 VSG21 +
+ M1 M2 - -
R1 VDD
vin
M21
- M13 I20
M4 M3 M16 M20
M14
VSS Buffer Fig. 7.1-1

1
Rout ≈  1000, Av(0)=65dB (IBias=50µA), and GB = 60MHz for CL = 1pF
gm21+gm22
Note the bias currents through M18 and M19 vary with the signal.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-7

Compensation of Op Amps with Output Amplifiers

Compensation of a three-stage amplifier:
This op amp introduces a third pole, p’3
(what about zeros?)
With no compensation,
Vout(s) -Avo
Vin(s) =  s  s  s 
p’ - 1 p’ - 1p’ - 1
 1  2  3 
Illustration of compensation choices:

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-8

Crossover-Inverter, Buffer Stage Op Amp

Principle: If the buffer has high output resistance and voltage gain (common source), this
is okay if when loaded by a small RL the gain of this stage is approximately unity.

• This buffer trades gain for the ability to drive a low load resistance
• The load resistance should be fixed in order to avoid changes in the buffer gain
• The push-pull common source output will give good output voltage swing capability

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-9

Crossover-Inverter, Buffer Stage Op Amp - Continued

How does the output buffer work?
The two inverters, M1-M3 and M2-M4 are designed to work over different regions of the
buffer input voltage, vin’.
Consider the idealized voltage transfer characteristic of the crossover inverters:
VDD

VDD vout
M6
M7 M3 M4 M6 Active
IBias M1-M3 M2-M4
Inverter M6 Satur- Inverter
C1 C2 vout
M5 Saturated ated
M1 M2 M5 RL M5 Active
vin'
0 vin'
VSS VA VB VDD
VSS 060706-05

Crossover voltage  VC = VB-VA  0

VC is designed to be small and positive for worst case variations in processing.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-10

Large Output Current Buffer

In the case where the load consists of a large capacitor, the ability to sink and source a
large current is much more important than reducing the output resistance. Consequently,
the common-source, push-pull is ideal if the quiescent current can be controlled.
VDD
A possible implementation:
VDD M5
M7 I=2Ib Ib

M1
vin vout vin vout
M8 M3 M4 M9
M2
M6
Ib I=2Ib M10
If W4/L4 = W9/L9 and W3/L3 = VSS
W8/L8, then the quiescent VSS 070430-07

currents in M1 and M2 can be

determined by the following relationship:
W1/L1   W2/L2 
I1 = I2 = Ib W /L  = Ib W /L 
 7 7  10 10
When vin is increased, M6 turns off M2 and turns on M1 to source current. Similarly,
when vin is decreased, M5 turns off M1 and turns on M2 to sink current.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 26 – Buffered Op Amps (6/25/14) Page 26-11

CLOSED LOOP BUFFERED OP AMPS

Principle
Use negative shunt feedback to reduce the output resistance of the buffer.

- Ro ROUT
vIN + vOUT
Av
RL
070430-02

• Output resistance
Ro
ROUT = 1 + A
v
• Watch out for when small RL causes Av to decrease.
• The bandwidth will be limited by the feedback (i.e. at high frequencies, the gain of Av
decreases causing the output resistance to increase.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-12

Two Stage Op Amp with a Gain Boosted, Source Follower Buffer

VDD
1:K
M6 M9 M10
M3 M4 Cc
Rout
M8
- M1 M2 vout
vin
+
I7 M11 I11
VNBiasM5 I5
M7

070430-03

1
Rout ≈ g
m8K
Power dissipation now becomes (I5 + I7 + I11)VDD
Gain becomes,
 gm1   gm6   gm8K 
Av = g +g  g +g  g K+ g 
 ds2 ds4  ds6 ds7  m8 mbs8 K +G L

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-13

Gain Boosted, Source-Follower, Push-Pull Output Op Amp

VDD
+ M6 M9 1:K
VT+2VON M17
- M24 M23 M24
M10 I17
M5 M22
M8
M11
VSG18 +
+
IBias - VDD VGS22 Rout
M12 M18 -
M7 vout
Cc M19
M15 VSS
+
VGS19 VSG21 +
+ M1 M2 - -
R1
vin
M21
M23
- M13 I20
M4
M3 M16 M20 M25 M26
M14 1:K
070430-04 VSS Gain Enhanced Buffer

1 1000
Rout ≈ ≈ ≈ 100
K(gm21+gm22) K
Av(0)=65dB (IBias=50µA)
Note the bias currents through M18 and M19 vary with the signal.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-14

Common Source, Push Pull Buffer with Shunt Feedback

To get low output resistance using MOSFETs, negative feedback must be used.
Ideal implementation:

Comments:
• The output resistance will be equal to rds1||rds2 divided by the loop gain
• If the error amplifiers are not perfectly matched, the bias current in M1 and M2 is not
defined

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-15

Low Output Resistance Op Amp - Continued

Offset correction circuitry:

The feedback circuitry of the two error amplifiers tries to insure that the voltages in
the loop sum to zero. Without the M9-M12 feedback circuit, there is no way to adjust the
output for any error in the loop. The circuit works as follows:
When VOS is positive, M6 tries to turn off and so does M6A. IM9 reduces thus reducing
IM12. A reduction in IM12 reduces IM8A thus decreasing VGS8A. VGS8A ideally decreases
by an amount equal to VOS. A similar result holds for negative offsets and offsets in EA2.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 26 – Buffered Op Amps (6/25/14) Page 26-16

Low Output Resistance Op Amp - Continued

Error amplifiers:

VDD
+
VBias
M6 M5A -
M3 M4 Cc1
vin
vin MR1 M2A M1A
M1 M2 vout MR2
Cc2
+ M6A M4A M3A
VBias M5
-
A1 amplifier VSS A2 amplifier
070430-05

Basically a two-stage op amp with the output push-pull transistors as the second-stage of
the op amp.

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-17

Low Output Resistance Op Amp - Complete Schematic

RC CC
Short circuit protection(max. output 60mA):
MP3-MN3-MN4-MP4-MP5 gm1 gm6
MN3A-MP3A-MP4A-MN4A-MN5A
C1 CL
rds6||rds6A 50k R1 RL
Rout  Loop Gain ≈ 5000 = 10

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-18

Simpler Implementation of Negative Feedback to Achieve Low Output Resistance

VDD

M8 M3 M4 M6
200mA 10/1 1/1 1/1 10/1
vout
Output Resistance:
M1 M2 CL Ro
+ Rout =
vin 10/1 10/1 1+LG
-
1/1 where
M5 1
M10 1/1 Ro =
10/1 10/1 gds6+gds7
M9 M7 and
gm2
VSS Fig. 7.1-9 |LG| = 2g (gm6+gm7)Ro
m4
Therefore, the output resistance is:
1
Rout =
  gm2  

(gds6+gds7) 1 +   (gm6+gm7)Ro
 2g
 m4 

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-19

Example 26-1 - Low Output Resistance Using Shunt Negative Feedback Buffer
Find the output resistance of above op amp using the model parameters of KN’ =
120µA/V2, KP’ = 25µA/V2, N = 0.06V-1 and P = 0.08V-1.
Solution
The current flowing in the output transistors, M6 and M7, is 1mA which gives Ro of
1 1000
Ro = = 0.14 = 7.143kΩ
(N+P)1mA
To calculate the loop gain, we find that
gm2 = 2KN’·10·100µA = 490µS
gm4 = 2KP’·1·100µA = 70.7µS
and
gm6 = 2KP’·10·1000µA = 707µS
Therefore, the loop gain is
490
|LG| = 2·70.7 (0.707+0.071)7.143 = 19.26
Solving for the output resistance, Rout, gives
7.143k
Rout = 1 + 19.26 = 353 (Assumes that RL is large)

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-20

USE OF THE BJT IN BUFFERED OP AMPS

Substrate BJTs
Illustration of an NPN substrate BJT available in a p-well CMOS technology:
Emitter Base Collector
(VDD)
Collector (VDD)

n+ (Emitter) p+ n+
Base
p- well (Base)

n- substrate (Collector)
Fig. 7.1-10
Emitter

Comments:
• gm of the BJT is larger than the FET so that the output resistance w/o feedback is lower
• Collector current will be flowing in the substrate
• Current is required to drive the BJT
• Only an NPN or a PNP bipolar transistor is available

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Lecture 26 – Buffered Op Amps (6/25/14) Page 26-21

A Lateral Bipolar Transistor

VC B LC E LC
n-well CMOS technology:
n+ p+ p+ p+
• It is desirable to have the lateral
collector current much larger than the STI STI
vertical collector current.
n-well
• Triple well technology allows the Substrate
current of the vertical collector to avoid 060221-01
flowing in the substrate.
Vertical STI Lateral Collector
• Lateral BJT generally has good Collector
matching.
Emitter

Base

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Lecture 26 – Buffered Op Amps (6/25/14) Page 26-22

A Field-Aided Lateral BJT

Use minimum channel length to VC B LC E LC
enhance beta:
ßF  50 to 100 depending on the n+ p+ p+ pp++

process Keeps carriers from

STI flowing at the surface STI
and reduces 1/f noise
n-well
Substrate
060221-02

Vertical STI Lateral Collector Emitter

Collector

Base

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-23

Two-Stage Op Amp with a Class-A BJT Output Buffer Stage

VDD
Purpose of the M8-M9 source
follower: M5 M7
M12 M8
+ Q10
1.) Reduce the output resistance vin
(includes whatever is seen from the - M1 M2
vout
base to ground divided by 1+F)
IBias M9
Cc
M3 M4 CL RL
2.) Reduces the output load at the M6
M13 M11
drains of M6 and M7
VSS Output Buffer Fig. 7.1-11

r10 + (1/gm9) 1 1
Small-signal output resistance : Rout ≈ = +
1+ßF gm10 gm9(1+ßF)
= 51.6+6.7 = 58.3 where I10=500µA, I8=100µA, W9/L9=100 and ßF is 100
2KP’ Ic10
vOUT(max) = VDD - VSD8(sat) - vBE10 = VDD -  
I8(W8/L8) - Vt lnIs10 
Voltage gain:
vout  gm1  gm6  gm9  gm10RL 
    
vin ≈ gds2+gds4gds6+gds7gm9+gmbs9+gds8+g101+gm10RL
Compensation will be more complex because of the additional stages.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 26 – Buffered Op Amps (6/25/14) Page 26-24

Example 26-2 - Designing the Class-A, Buffered Op Amp

Use an n-well, 0.25µm CMOS technology to design an op amp using a class-A, BJT
output stage to give the following specifications. Assume the channel length is to be
0.5µm. The FETs have the model parameters of KN’ = 120µA/V2, KP’ = 25µA/V2, VTN
= |VTP| = 0.5V, N = 0.06V-1 and P = 0.08V-1 along with the BJT parameters of Is =
10-14A and ßF = 50.
VDD = 2.5V VSS = 0V GB = 10MHz Avd(0)  2500V/V Slew rate  10V/µs
RL = 500 Rout  50 CL = 100pF ICMR = +1V to 2V
Solution
VDD
A quick comparison shows that the VPB1 VPB1
I4 I5 M14
specifications of this problem are similar to
M4 M5 I15
the folded cascode op amp that was designed Rout
VPB2 vOUT
in Ex. 24-4. Borrowing that design for this I1 I2 I12
I6 I7
example results in the following op amp. M6 M7 CL
M1 M2 VNB2 M12
+
Therefore, the goal of this example will vIN
- M8 M9
be the design of M12 through Q15 to satisfy M3 M11 V
NB1
Q15
VNB1 I3
the slew rate and output resistance M10 M13

requirements. 070430-06

CMOS Analog Circuit Design © P.E. Allen - 2016

Lecture 26 – Buffered Op Amps (6/25/14) Page 26-25

Example 26-2 – Continued

BJT follower (Q15):
SR = 10V/µs and 100pF capacitor give I15 = 1mA.
 Assuming the gate of M14 is connected to the gate of M5, the W/L ratio of M14
becomes
W14/L14 = (1000µA/125µA)160 = 1280  W14 = 640µm
I15 = 1mA  1/gm15 = 0.0258V/1mA = 25.8
MOS follower:
To source 1mA, the BJT requires 20µA (ß =50) from the MOS follower (M12-M13).
Therefore, select a bias current of 100µA for M13. If the gates of M3 and M13 are
connected together, then
W13/L13 = (100µA/100µA)15 = 15  W13 = 7.5µm
To get Rout = 50, if 1/gm15 is 25.8, then design gm12 as
1 1 1 1
= = 24.2 g m12 (24.2)(1+ß ) 24.2·51 = 810µS
= =
gm15 gm12(1+ßF) F
 gm12 and I12  W/L = 27.3 ≈ 30  W12 = 15µm
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 26 – Buffered Op Amps (6/25/14) Page 26-26

Example 26-2 - Continued

To calculate the voltage gain of the MOS follower we need to find gmbs9 (N = 0.4 V).
gm12N 810·0.4
 gmbs12 = = = 158µS
2 2F + VBS12 2 0.5+0.55
where we have assumed that the value of VSB12 is approximately 1.25V – 0.7V = 0.55V.
810µS
 AMOS = = 0.825
810µS+158µS+6µS+8µS
The voltage gain of the BJT follower is
500
ABJT = 25.8+500 = 0.951 V/V
Thus, the gain of the op amp is
Avd(0) = (4,680)(0.825)(0.951) = 3,672 V/V
The power dissipation of this amplifier is,
Pdiss. = 2.5V(125µA+125µA+100µA+1000µA) = 3.375mW
The signal swing across the 500 load resistor will be restricted to ±0.5V due to the
1000µA output current limit.
CMOS Analog Circuit Design © P.E. Allen - 2016
Lecture 26 – Buffered Op Amps (6/25/14) Page 26-27

SUMMARY
• A buffered op amp requires an output resistance between 10  Ro  1000
• Output resistance using MOSFETs only can be reduced by,
- Source follower output (1/gm)
- Negative shunt feedback (frequency is a problem in this approach)
• Use of substrate (or lateral) BJT’s can reduce the output resistance because gm is larger
than the gm of a MOSFET
• Adding a buffer stage to lower the output resistance will most likely complicate the
compensation of the op amp

CMOS Analog Circuit Design © P.E. Allen - 2016